Design procedure for multifinger MOSFET two-stage OTA with shallow trench isolation effect (Englisch)
Freier Zugriff
- Neue Suche nach: Veldandi, Harikrishna
- Neue Suche nach: Rafi Aahmed, Shaik
- Neue Suche nach: Veldandi, Harikrishna
- Neue Suche nach: Rafi Aahmed, Shaik
In:
IET Circuits, Devices & Systems
;
12
, 5
;
513-522
;
2018
- Aufsatz (Zeitschrift) / Elektronische Ressource
-
Titel:Design procedure for multifinger MOSFET two-stage OTA with shallow trench isolation effect
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Beteiligte:Veldandi, Harikrishna ( Autor:in ) / Rafi Aahmed, Shaik ( Autor:in )
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Erschienen in:IET Circuits, Devices & Systems ; 12, 5 ; 513-522
-
Verlag:
- Neue Suche nach: The Institution of Engineering and Technology
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Erscheinungsdatum:26.06.2018
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Format / Umfang:10 pages
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ISSN:
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DOI:
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Medientyp:Aufsatz (Zeitschrift)
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Format:Elektronische Ressource
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Sprache:Englisch
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Schlagwörter:operational amplifiers , shallow trench isolation effect , small-signal parameter , multifinger layout technique , Miller-compensated two-stage OTA , MOSFET , nanoscale complementary metal-oxide-semiconductor circuit design , single-finger layout , CMOS analogue integrated circuits , current-voltage characteristics , standard UMC CMOS circuit design , multifinger MOSFET two-stage OTA , isolation technology , I-V characteristics , optimisation , operational transconductance amplifier , size 65 nm , STI effect , common source amplifier
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Datenquelle:
Metadata by IET is licensed under CC BY 3.0
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