Letters - Silicon Devices - Bonded Planar Double-Metal-Gate NMOS Transistors Down to 10 nm (Englisch)
- Neue Suche nach: Vinet, M.
- Neue Suche nach: Vinet, M.
- Neue Suche nach: Poiroux, T.
- Neue Suche nach: Widiez, J.
- Neue Suche nach: Lolivier, J.
- Neue Suche nach: Previtali, B.
- Neue Suche nach: Vizioz, C.
- Neue Suche nach: Guillaumot, B.
- Neue Suche nach: Tiec, Y.Le
- Neue Suche nach: Besson, P.
In:
IEEE electron device letters
;
26
, 5
; 317-319
;
2005
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ISSN:
- Aufsatz (Zeitschrift) / Print
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Titel:Letters - Silicon Devices - Bonded Planar Double-Metal-Gate NMOS Transistors Down to 10 nm
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Beteiligte:Vinet, M. ( Autor:in ) / Poiroux, T. / Widiez, J. / Lolivier, J. / Previtali, B. / Vizioz, C. / Guillaumot, B. / Tiec, Y.Le / Besson, P.
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Erschienen in:IEEE electron device letters ; 26, 5 ; 317-319
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Verlag:
- Neue Suche nach: IEEE
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Erscheinungsort:New York, NY
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Erscheinungsdatum:2005
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ISSN:
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ZDBID:
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Medientyp:Aufsatz (Zeitschrift)
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Format:Print
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Sprache:Englisch
- Neue Suche nach: 770/5670
- Neue Suche nach: 53.51
- Weitere Informationen zu Basisklassifikation
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Schlagwörter:
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Klassifikation:
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Datenquelle:
Inhaltsverzeichnis – Band 26, Ausgabe 5
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