BRIEF PAPERS - Simple Noise Margin Model for Optimal Design of Unipolar Thin-Film Transistor Logic Circuits (Englisch)
- Neue Suche nach: Cui, Q
- Neue Suche nach: Cui, Q
- Neue Suche nach: Si, M
- Neue Suche nach: Sporea, R A
- Neue Suche nach: Guo, X
In:
IEEE transactions on electron devices
;
60
, 5
; 1782-1785
;
2013
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ISSN:
- Aufsatz (Zeitschrift) / Print
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Titel:BRIEF PAPERS - Simple Noise Margin Model for Optimal Design of Unipolar Thin-Film Transistor Logic Circuits
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Beteiligte:
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Erschienen in:IEEE transactions on electron devices ; 60, 5 ; 1782-1785
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Verlag:
- Neue Suche nach: IEEE
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Erscheinungsort:New York, NY
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Erscheinungsdatum:2013
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ISSN:
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ZDBID:
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Medientyp:Aufsatz (Zeitschrift)
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Format:Print
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Sprache:Englisch
- Neue Suche nach: 53.50 / 53.00 / 52.50 / 54.20
- Weitere Informationen zu Basisklassifikation
- Neue Suche nach: 770/5670
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Schlagwörter:
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Klassifikation:
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Datenquelle:
Inhaltsverzeichnis – Band 60, Ausgabe 5
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Table of contents| 2013
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IEEE Transactions on Electron Devices publication information| 2013
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IEEE Transactions on Electron Devices information for authors| 2013
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High-Performance Ultrathin Body c-SiGe Channel FDSOI pMOSFETs Featuring SiGe Source and Drain: Vth Tuning, Variability, Access Resistance, and Mobility IssuesVillalon, A et al. | 2013
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[Blank page - back cover]| 2013