On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time (Englisch)
- Neue Suche nach: Wang, Y
- Neue Suche nach: Wang, Y
- Neue Suche nach: Liu, L
- Neue Suche nach: Yin, S
- Neue Suche nach: Zhu, M
- Neue Suche nach: Cao, P
- Neue Suche nach: Yang, J
- Neue Suche nach: Wei, S
In:
IEEE transactions on very large scale integration (VLSI) systems
;
22
, 5
; 983-994
;
2014
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ISSN:
- Aufsatz (Zeitschrift) / Print
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Titel:On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time
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Beteiligte:
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Erschienen in:IEEE transactions on very large scale integration (VLSI) systems ; 22, 5 ; 983-994
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Verlag:
- Neue Suche nach: Institute of Electrical and Electronics Engineers
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Erscheinungsort:New York, NY
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Erscheinungsdatum:2014
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ISSN:
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ZDBID:
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Medientyp:Aufsatz (Zeitschrift)
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Format:Print
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Sprache:Englisch
- Neue Suche nach: 53.52
- Weitere Informationen zu Basisklassifikation
- Neue Suche nach: 770/5670
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Schlagwörter:
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Klassifikation:
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Datenquelle:
Inhaltsverzeichnis – Band 22, Ausgabe 5
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