Error Detection Enhancement in PowerPC Architecture-based Embedded Processors (Englisch)
- Neue Suche nach: Fazeli, Mahdi
- Neue Suche nach: Farivar, Reza
- Neue Suche nach: Miremadi, Seyed Ghassem
- Neue Suche nach: Fazeli, Mahdi
- Neue Suche nach: Farivar, Reza
- Neue Suche nach: Miremadi, Seyed Ghassem
In:
Journal of Electronic Testing
;
24
, 1-3
; 21-33
;
2008
-
ISSN:
- Aufsatz (Zeitschrift) / Print
-
Titel:Error Detection Enhancement in PowerPC Architecture-based Embedded Processors
-
Beteiligte:
-
Erschienen in:Journal of Electronic Testing ; 24, 1-3 ; 21-33
-
Verlag:
- Neue Suche nach: Springer US
- Neue Suche nach: Kluwer
-
Erscheinungsort:Boston, Mass. [u.a.]
-
Erscheinungsdatum:2008
-
ISSN:
-
ZDBID:
-
DOI:
-
Medientyp:Aufsatz (Zeitschrift)
-
Format:Print
-
Sprache:Englisch
- Neue Suche nach: 53.00 / 53.55 / 53.03 / 53.15
- Weitere Informationen zu Basisklassifikation
- Neue Suche nach: 770/5670
-
Schlagwörter:
-
Klassifikation:
-
Datenquelle:
Inhaltsverzeichnis – Band 24, Ausgabe 1-3
Zeige alle Jahrgänge und Ausgaben
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
- 1
-
EditorialAgrawal, Vishwani D. et al. | 2008
- 3
-
New Editors| 2008
- 5
-
Test Technology Newsletter February 2008| 2008
- 7
-
List of 2007 Reviewers| 2008
- 9
-
Guest EditorialTouba, Nur / Salsano, Adelio / Choi, Minsu et al. | 2008
- 11
-
Circuit and Latch Capable of Masking Soft Errors with Schmitt TriggerSasaki, Yoichi / Namba, Kazuteru / Ito, Hideo et al. | 2008
- 21
-
Error Detection Enhancement in PowerPC Architecture-based Embedded ProcessorsFazeli, Mahdi / Farivar, Reza / Miremadi, Seyed Ghassem et al. | 2008
- 35
-
Software and Hardware Techniques for SEU Detection in IP ProcessorsBolchini, C. / Miele, A. / Rebaudengo, M. / Salice, F. / Sciuto, D. / Sterpone, L. / Violante, M. et al. | 2008
- 45
-
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETsRhod, Eduardo Luis / Lisbôa, Carlos Arthur Lang / Carro, Luigi / Sonza Reorda, Matteo / Violante, Massimo et al. | 2008
- 57
-
A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit TechniqueGong, Rui / Chen, Wei / Liu, Fang / Dai, Kui / Wang, Zhiying et al. | 2008
- 67
-
Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction CodingGanguly, Amlan / Pande, Partha Pratim / Belzer, Benjamin / Grecu, Cristian et al. | 2008
- 83
-
Majority Logic Mapping for Soft Error DependabilityPetroli, Lorenzo / Lisboa, Carlos Arthur Lang / Kastensmidt, Fernanda Lima / Carro, Luigi et al. | 2008
- 93
-
Checkers’ No-Harm Alarms and Design Approaches to Tolerate ThemRossi, Daniele / Omaña, Martin / Metra, Cecilia et al. | 2008
- 105
-
Analysis and Evaluations of Reliability of Reconfigurable FPGAsPontarelli, Salvatore / Ottavi, Marco / Vankamamidi, Vamsi / Cardarilli, Gian Carlo / Lombardi, Fabrizio / Salsano, Adelio et al. | 2008
- 117
-
Hierarchical Verification for Increasing Performance in Reliable ProcessorsYoo, Joonhyuk / Franklin, Manoj et al. | 2008
- 129
-
Performance-Optimized Design for Parametric ReliabilityDatta, Ramyanshu / Abraham, Jacob A. / Utku Diril, Abdulkadir / Chatterjee, Abhijit / Nowka, Kevin J. et al. | 2008
- 143
-
Design Considerations for High Performance RF Cores Based on Process Variation StudyUpadhyaya, Shambhu / Venugopal, Nandakumar P. / Shastry, Nihal / Gopalakrishnan, Srinivasan / Kuppuswamy, Bharath V. / Bhowmick, Rana / Mayor, Prerna et al. | 2008
- 157
-
Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired RedundancyGranhaug, Kristian / Aunet, Snorre et al. | 2008
- 165
-
Defect Analysis and Defect Tolerant Design of Multi-port SRAMsLiu, Lushan / Nagaraj, Pradeep / Upadhyaya, Shambhu / Sridhar, Ramalingam et al. | 2008
- 181
-
A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level RedundancyChang, Da-Ming / Li, Jin-Fu / Huang, Yu-Jen et al. | 2008
- 193
-
Substrate Testing on a Multi-Site/Multi-Probe ATEMa, Xiaojun / Lombardi, Fabrizio et al. | 2008
- 203
-
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test GenerationChristou, Kyriakos / Michael, Maria K. / Tragoudas, Spyros et al. | 2008
- 223
-
Adaptive Fault Diagnosis of Analog Circuits by Operation-Region Model and X–Y Zoning MethodMiura, Yukiya / Kato, Jiro et al. | 2008
- 235
-
Scan Test Response Compaction Combined with Diagnosis CapabilitiesWichlund, Sverre / Berntsen, Frank / Aas, Einar Johan et al. | 2008
- 247
-
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and InterleavingHe, Zhiyuan / Peng, Zebo / Eles, Petru / Rosinger, Paul / Al-Hashimi, Bashir M. et al. | 2008
- 259
-
A Methodology for Handling Complex Functional Constraints for Large Industrial DesignsJas, Abhijit / Chang, Yi-Shing / Chakravarty, Sreejit et al. | 2008
- 271
-
Monomer Control for Error Tolerance in DNA Self-AssemblyJang, Byunghyun / Kim, Yong-Bin / Lombardi, Fabrizio et al. | 2008
- 285
-
Bilateral Testing of Nano-scale Fault-Tolerant CircuitsFang, Lei / Hsiao, Michael S. et al. | 2008
- 297
-
Reversible Gates and Testability of One Dimensional Arrays of Molecular QCAMa, X. / Huang, J. / Metra, C. / Lombardi, F. et al. | 2008
- 313
-
Scalability of Globally Asynchronous QCA (Quantum-Dot Cellular Automata) Adder DesignChoi, Myungsu / Choi, Minsu et al. | 2008