Wiring requirement and three-dimensional integration technology for field programmable gate arrays (Englisch)
- Neue Suche nach: Rahman, A.
- Neue Suche nach: Das, S.
- Neue Suche nach: Chandrakasan, A.P.
- Neue Suche nach: Reif, R.
- Neue Suche nach: Rahman, A.
- Neue Suche nach: Das, S.
- Neue Suche nach: Chandrakasan, A.P.
- Neue Suche nach: Reif, R.
In:
IEEE Transactions on Very Large Scale Integration Systems
;
11
, 1
;
44-54
;
2003
-
ISSN:
- Aufsatz (Zeitschrift) / Print
-
Titel:Wiring requirement and three-dimensional integration technology for field programmable gate arrays
-
Beteiligte:Rahman, A. ( Autor:in ) / Das, S. ( Autor:in ) / Chandrakasan, A.P. ( Autor:in ) / Reif, R. ( Autor:in )
-
Erschienen in:IEEE Transactions on Very Large Scale Integration Systems ; 11, 1 ; 44-54
-
Verlag:
-
Erscheinungsdatum:2003
-
Format / Umfang:11 Seiten, 33 Quellen
-
ISSN:
-
Coden:
-
DOI:
-
Medientyp:Aufsatz (Zeitschrift)
-
Format:Print
-
Sprache:Englisch
-
Schlagwörter:feldprogrammierbare Gate-Array-Schaltung , Verbindung integrierter Schaltungen , Layout integrierter Schaltungen , Modellierung integrierter Schaltungen , integrierte Schaltungstechnologie , Logikentwurf , Leitweglenkung , Zufallsprozess , VLSI-Schaltung , stochastisches Modell , Verzögerung , analytisches Modell
-
Datenquelle:
Inhaltsverzeichnis – Band 11, Ausgabe 1
Zeige alle Jahrgänge und Ausgaben
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
- 1
-
GUEST EDITORIAL - System-Level Interconnect Prediction (SLIP)Christie, P. et al. | 2003
- 1
-
Guest editorial: System-level interconnect predictionChristie, P. et al. | 2003
- 3
-
Improved a priori interconnect predictions and technology extrapolation in the GTX systemYu Cao, / Chenming Hu, / Xuejue Huang, / Kahng, A.B. / Markov, I.L. / Oliver, M. / Stroobandt, D. / Sylvester, D. et al. | 2003
- 3
-
SPECIAL SECTION PAPERS - Improved A Priori Interconnect Predictions and Technology Extrapolation in the GTX SystemCao, Y. et al. | 2003
- 15
-
Multi-objective optimization of interconnect geometryWildman, R.A. / Kramer, J.I. / Weile, D.S. / Christie, P. et al. | 2003
- 15
-
SPECIAL SECTION PAPERS - Multi-Objective Optimization of Interconnect GeometryWildman, R.A. et al. | 2003
- 24
-
A comparison of various terminal-gate relationships for interconnect prediction in VLSI circuitsDambre, J. / Verplaetse, P. / Stroobandt, D. / Van Campenhout, J. et al. | 2003
- 24
-
SPECIAL SECTION PAPERS - A Comparison of Various Terminal-Gate Relationships for Interconnect Prediction in VLSI CircuitsDambre, J. et al. | 2003
- 35
-
SPECIAL SECTION PAPERS - A Priori Wire Length Distribution Models With Multiterminal NetsStroobandt, D. et al. | 2003
- 35
-
A priori wire length distribution models with multiterminal netsStroobandt, D. et al. | 2003
- 44
-
Wiring requirement and three-dimensional integration technology for field programmable gate arraysRahman, A. / Das, S. / Chandrakasan, A.P. / Reif, R. et al. | 2003
- 44
-
SPECIAL SECTION PAPERS - Wiring Requirement and Three-Dimensional Integration Technology for Field Programmable Gate ArraysRahman, A. et al. | 2003
- 55
-
SPECIAL SECTION TRANSACTIONS BRIEF - Prelayout Interconnect Yield PredictionChristie, P. et al. | 2003
- 55
-
Prelayout interconnect yield predictionChristie, P. / Jose Pineda de Gyvez, et al. | 2003
- 60
-
Adaptive delay estimation for partitioning-driven PLD placementHutton, M. / Adibsamii, K. / Leaver, A. et al. | 2003
- 60
-
SPECIAL SECTION TRANSACTIONS BRIEF - Adaptive Delay Estimation for Partitioning-Driven PLD PlacementHutton, M. et al. | 2003
- 64
-
Energy-efficient skewed static logic with dual Vt: design and synthesisChulwoo Kim, / Ki-Wook Kim, / Sung-Mo Kang, et al. | 2003
- 71
-
Multiterminal net routing for partial crossbar-based multi-FPGA systemsEjnioui, A. / Ranganathan, N. et al. | 2003
- 79
-
Noise-aware interconnect power optimization in domino logic synthesisKi-Wook Kim, / Seong-Ook Jung, / Narayanan, U. / Liu, C.L. / Sung-Mo Kang, et al. | 2003
- 90
-
A variable-radix digit-serial design methodology and its application to the discrete cosine transformLeong, M.P. / Leong, P.H.W. et al. | 2003
- 105
-
Wave steering to integrate logic and physical synthesesMukherjee, A. / Marek-Sadowska, M. et al. | 2003
- 121
-
Carry checking/parity prediction adders and ALUsNicolaidis, M. et al. | 2003
- 129
-
Relative TimingStevens, K.S. et al. | 2003
- 129
-
Relative timing [asynchronous design]Stevens, K.S. / Ginosar, R. / Rotem, S. et al. | 2003
- 141
-
Design and synthesis of dynamic circuitsThorp, T.J. / Yee, G.S. / Sechen, C.M. et al. | 2003
- 150
-
Low-power and area-efficient FIR filter implementation suitable for multiple tapsKyung-Saeng Kim, / Kwyro Lee, et al. | 2003
- 150
-
REGULAR SECTION BRIEF PAPERS - Low-Power and Area-Efficient FIR Filter Implementation Suitable for Multiple TapsKim, K.-S. et al. | 2003
- 155
-
IEEE COPYRIGHT FORM| 2003
-
SPECIAL SECTION ON SYSTEM-LEVEL INTERCONNECT PREDICTION (SLIP)| 2003