Versions and change notification in an object-oriented database system (Englisch)
- Neue Suche nach: Chou, H.T.
- Neue Suche nach: Kim, W.
- Neue Suche nach: Chou, H.T.
- Neue Suche nach: Kim, W.
In:
25th ACM/IEEE Design Automation Conference. Proceedings
;
275-281
;
1988
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ISBN:
- Aufsatz (Konferenz) / Print
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Titel:Versions and change notification in an object-oriented database system
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Weitere Titelangaben:Das Management von Versionen und Aenderungen in einem objektorientierten Datenbanksystem
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Beteiligte:Chou, H.T. ( Autor:in ) / Kim, W. ( Autor:in )
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Erschienen in:
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Verlag:
- Neue Suche nach: IEEE
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Erscheinungsort:New York
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Erscheinungsdatum:1988
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Format / Umfang:7 Seiten, 24 Quellen
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ISBN:
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DOI:
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Medientyp:Aufsatz (Konferenz)
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Format:Print
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Sprache:Englisch
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Schlagwörter:
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Datenquelle:
Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
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25th ACM/IEEE Design Automation Conference. Proceedings 1988 (Cat. No.88CH2540-3)| 1988
- 3
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An automated BIST approach for general sequential logic synthesisStroud, C.E. et al. | 1988
- 9
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Automatic insertion of BIST hardware using VHDLKim, K. / Tront, J.G. / Ha, D.S. et al. | 1988
- 16
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VLSI design synthesis with testabilityGebotys, C. / Elmasry, M.I. et al. | 1988
- 22
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A defect-tolerant and fully testable PLAWehn, N. / Glesner, M. / Caesar, K. / Mann, P. / Roth, A. et al. | 1988
- 28
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Experience with the VHDL environmentLoughzail, M. / Cote, M. / Aboulhamid, M. / Cerny, E. et al. | 1988
- 34
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The role of VHDL in the MCC CAD systemAcosta, R.D. / Alexandre, M. / Inken, G. / Read, B. et al. | 1988
- 40
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VHDL: a call for standardsCoelho, D.R. et al. | 1988
- 48
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Verification of VHDL designs using VALAugustin, L.M. / Gennart, B.A. / Huh, Y. / Luckham, D.C. / Stanculescu, A.G. et al. | 1988
- 54
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A module area estimator for VLSI layoutChen, X. / Bushnell, M.L. et al. | 1988
- 60
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A new area and shape function estimation technique for VLSI layoutsZimmerman, G. et al. | 1988
- 66
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Optimal aspect ratios of building blocks in VLSIWimer, S. / Koren, I. / Cederbaum, I. et al. | 1988
- 73
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Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealingSechen, C. et al. | 1988
- 82
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Opportunities in computer integrated manufacturingHodges, D.A. et al. | 1988
- 84
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CONTEST: a concurrent test generator for sequential circuitsAgrawal, V.D. / Cheng, K.T. / Agrawal, P. et al. | 1988
- 90
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A method of delay fault test generationGlover, C.T. / Mercer, M.R. et al. | 1988
- 96
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SPLIT circuit model for test generationCheng, W.T. et al. | 1988
- 102
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A notation for describing multiple views of VLSI circuitsBaer, J.-L. / Liem, M.-C. / McMurchie, L. / Nottrott, R. / Snyder, L. / Winder, W. et al. | 1988
- 108
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A graphical hardware design languageDrongowski, P.J. / Bammi, J.R. / Ramaswamy, R. / Iyengar, S. / Wang, T.-H. et al. | 1988
- 115
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A human machine interface for silicon compilationOdawara, G. / Tomita, M. / Hattori, K. / Okuzawa, O. / Hirata, T. / Ochiai, M. et al. | 1988
- 121
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Parallel placement on reduced array architectureKumar, C.P.R. / Sastry, S. et al. | 1988
- 128
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Parallel channel routingZargham, M.R. et al. | 1988
- 134
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Mask verification on the Connection MachineCarlson, E.C. / Rutenbar, R.A. et al. | 1988
- 142
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On path selection in combinational logic circuitsLi, W.N. / Reddy, S.M. / Sahni, S. et al. | 1988
- 148
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Pearl: a CMOS timing analyzerCherry, J.J. et al. | 1988
- 154
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ATV: an abstract timing verifierWallace, D.E. / Sequin, C.H. et al. | 1988
- 160
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An empirical study of on-chip parallelismBailey, M.L. / Snyder, L. et al. | 1988
- 166
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Parallel logic simulation on general purpose machinesSoule, L. / Blank, T. et al. | 1988
- 172
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A programmable hardware accelerator for compiled electrical simulationLewis, D.M. et al. | 1988
- 178
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Recursive channel routerHeyns, W. / Nieuwenhove, K.V. et al. | 1988
- 183
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Multi-pads, single layer power net routing in VLSI circuitsCai, H. et al. | 1988
- 189
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LocusRoute: a parallel global router for standard cellsRose, J. et al. | 1988
- 197
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Formal specification and verification of hardware: a comparative case studyStavridou, V. / Barringer, H. / Edwards, D.A. et al. | 1988
- 205
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Proving circuit correctness using formal comparison between expected and extracted behaviourMadre, J.-C. / Billon, J.-P. et al. | 1988
- 211
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Formal verification of the Sobel image processing chipNarendran, P. / Stillman, J. et al. | 1988
- 218
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The IBM engineering verification engineBeece, D.K. / Deiberg, G. / Papp, G. / Villante, F. et al. | 1988
- 225
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Logic simulation system using simulation processor (SP)Saitoh, M. / Iwata, K. / Nakamura, A. / Kakegawa, M. / Masuda, J. / Hamamura, H. / Hirose, F. / Kawato, N. et al. | 1988
- 231
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Algorithm for vectorizing logic simulation and evaluation of 'VELVET' performanceKazama, Y. / Knoshita, Y. / Nagafuji, M. / Murayama, H. et al. | 1988
- 237
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A structural representation for VLSI designBarth, R. / Serlet, B. et al. | 1988
- 243
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Parameterized schematics (VLSI)Barth, R. / Serlet, B. / Sindhu, P. et al. | 1988
- 250
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PatchWork: layout from schematic annotationsBarth, R. / Monier, L. / Serlet, B. et al. | 1988
- 257
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A database management system for a VLSI design systemChen, G.-D. / Parng, T.-M. et al. | 1988
- 263
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An enhanced data model for CAD/CAM database systemsYang, Y.K. et al. | 1988
- 269
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Browsing the chip design databaseGedye, D. / Katz, R. et al. | 1988
- 275
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Versions and change notification in an object-oriented database systemChou, H.-T. / Kim, W. et al. | 1988
- 282
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An accurate and efficient gate level delay calculator for MOS circuitsChang, F.-C. / Chen, C.-F. / Subramaniam, P. et al. | 1988
- 288
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Delay modeling and timing of bipolar digital circuitsSaab, D.G. / Yang, A.T. / Hajj, I.N. et al. | 1988
- 294
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Pattern-independent current estimation for reliability analysis of CMOS circuitsBurch, R. / Najm, F. / Yang, P. / Hocevar, D. et al. | 1988
- 300
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Improved methods of simulating RLC coupled and uncoupled transmission lines based on the method of characteristicsGura, C.V. / Abraham, J.A. et al. | 1988
- 306
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Performance of a new annealing scheduleLam, J. / Delosme, J.-M. et al. | 1988
- 312
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Clustering based simulated annealing for standard cell placementMallela, S. / Grover, L.K. et al. | 1988
- 477
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High-level synthesis: current status and future directionsBorriello, G. / Detjens, E. et al. | 1988
- 483
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HERCULES-a system for high-level synthesisde Micheli, G. / Ku, D.C. et al. | 1988
- 489
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Design process model in the Yorktown silicon compilerCamposano, R. et al. | 1988
- 495
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For incremental circuit analysis using extracted hierarchyBeatty, D.L. / Bryant, R.E. et al. | 1988
- 501
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Incremental-in-time algorithm for digital simulationChoi, K. / Hwang, S.Y. / Blank, T. et al. | 1988
- 506
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A dynamically-directed switch model for MOS logic simulationAdler, D. et al. | 1988
- 512
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A circuit comparison system with rule-based functional isomorphism checkingTakashima, M. / Ikeuchi, A. / Kojima, S. / Tanaka, T. / Saitou, T. / Sakata, J. et al. | 1988
- 517
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LOGEX-an automatic logic extractor from transistor to gate level for CMOS technologyBoehner, M. et al. | 1988
- 523
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A PROLOG-based connectivity verification toolPapaspyridis, A.C. et al. | 1988
- 529
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CORAL II: linking behavior and structure in an IC design systemBlackburn, R.L. / Thomas, D.E. / Koenig, P.M. et al. | 1988
- 536
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Splicer: a heuristic approach to connectivity bindingPangrle, B.M. et al. | 1988
- 542
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Module selection for pipelined synthesisJain, R. / Parker, A. / Park, N. et al. | 1988
- 548
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The use of Petri nets for modeling pipelined processorsRazouk, R.R. et al. | 1988
- 554
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Fast algorithm for optimal layer assignmentKuo, Y.S. / Chern, T.C. / Shih, W.-K. et al. | 1988
- 560
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Connectivity biased channel construction and ordering for building-block layoutCai, H. et al. | 1988
- 566
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A new approach to the pin assignment problemYao, X. / Yamada, M. / Liu, C.L. et al. | 1988
- 573
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The constrained via minimization problem for PCB and VLSI designXiong, X.-M. / Kuh, E.S. et al. | 1988
- 579
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Micro-operation perturbations in chip level fault modelingChao, C.-H. / Gray, F.G. et al. | 1988
- 583
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A new two task algorithm for clock mode fault simulation in sequential circuitsHill, F.J. / Abuelyamen, E. / Huang, W.-K. / Shen, G.-Q. et al. | 1988
- 587
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Switch level random pattern testability analysisCirit, M.A. et al. | 1988
- 591
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DYTEST: a self-learning algorithm using dynamic testability measures to accelerate test generationMao, W. / Ciletti, M.D. et al. | 1988
- 597
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CATAPULT: concurrent automatic testing allowing parallelization and using limited topologyGaede, R.K. / Mercer, M.R. / Butler, K. / Ross, D.E. et al. | 1988
- 601
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A graph compaction approach to fault simulationHarel, D. / Krishnamurthy, B. et al. | 1988
- 605
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Automatic functional test program generation for microprocessorsLin, C.S. / Ho, H.F. et al. | 1988
- 609
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Spare allocation and reconfiguration in large area VLSIKuo, S.-Y. / Fuchs, W.K. et al. | 1988
- 613
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A data structure for circuit net listsMeyer, S. et al. | 1988
- 617
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The architecture of a highly integrated simulation systemHeydemann, M. / Plaignaud, A. / Dure, D. et al. | 1988
- 622
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Circuit compilers don't have to be slowDiss, W.C. et al. | 1988
- 628
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Constraint propagation in an object-orientated IC design environmentLy, T.A. / Girczyc, E.F. et al. | 1988
- 634
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Design automation for the component parts industryChang, S.S.L. et al. | 1988
- 638
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Automatic building of graphs for rectangular dualisation (IC floorplanning)Jabri, M.A. et al. | 1988
- 645
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Automatic layout procedures for serial routing devicesOgawa, Y. / Terai, H. / Kozawa, T. et al. | 1988
- 646
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A digital-serial silicon compilerHartley, R.I. / Corbett, P.F. et al. | 1988
- 650
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DECOMPOSER: a synthesizer for systolic systemsHou, P.-P. / Owens, R.M. / Irwin, M.J. et al. | 1988
- 654
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SMART: tools and methods for synthesis of VLSI chips with processor architectureBergstraesser, T. / Gessner, J. / Hafner, K. / Wallstab, S. et al. | 1988
- 658
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Routing algorithm for gate array macro cellsChakraverti, A. / Chung, M.J. et al. | 1988
- 663
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How to obtain more compactable channel routing solutionsCong, J. / Wong, D.F. et al. | 1988
- 667
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A channelless, multilayer routerLunow, R.E. et al. | 1988
- 672
-
An interactive maze router with hintsArnold, M.H. / Scott, W.S. et al. | 1988
- 677
-
Improved channel routing by via minimization and shiftingCheng, C.-K. / Deutsch, D.N. et al. | 1988
- 681
-
The min-cut shuffle: toward a solution for the global effect problem of min-cut placementBhandari, I. / Hirsch, M. / Slewiorek, D. et al. | 1988
- 686
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Fault simulation in a distributed environmentDuba, P.A. / Roy, R.K. / Abraham, J.A. / Rogers, W.A. et al. | 1988
- 692
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The performance of the concurrent fault simulation algorithms in MOZARTGai, S. / Montessoro, P.L. / Somenzi, F. et al. | 1988
- 698
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An approach to fast hierarchical fault simulationMotohara, A. / Murakami, M. / Urano, M. / Masuda, Y. / Sugano, M. et al. | 1988
- 704
-
Why partial design verification works better than it shouldSavir, J. et al. | 1988
- 708
-
Advances in functional abstraction from structureLathrop, R.H. / Hall, R.J. / Duffy, G. / Alexander, K.M. / Kirk, R.S. et al. | 1988
- 712
-
Hardware logic simulation by compilationHansen, C. et al. | 1988
- 716
-
Clock event suppression algorithm of VELVET and its application to S-820 developmentTakamine, Y. / Miyamoto, S. / Nagashima, S. / Miyoshi, M. / Kawabe, S. et al. | 1988
- 720
-
A path selection algorithm for timing analysisYen, H.C. / Ghanta, S. / Du, H.C. et al. | 1988
- 724
-
Algorithms for timing requirement analysis and generationSherman, S.K. et al. | 1988