A fourth generation analog incircuit program generator (Englisch)
- Neue Suche nach: Crook, D.T.
- Neue Suche nach: Crook, D.T.
In:
Proceedings International Test Conference
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605-612
;
1990
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ISBN:
- Aufsatz (Konferenz) / Print
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Titel:A fourth generation analog incircuit program generator
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Weitere Titelangaben:Ein analoger in-circuit-Programmgenerator der vierten Generation
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Beteiligte:Crook, D.T. ( Autor:in )
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Erschienen in:
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Verlag:
- Neue Suche nach: IEEE Comput. Soc. Press
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Erscheinungsort:Los Alamitos
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Erscheinungsdatum:1990
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Format / Umfang:8 Seiten, 2 Quellen
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ISBN:
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DOI:
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Medientyp:Aufsatz (Konferenz)
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Format:Print
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Sprache:Englisch
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Schlagwörter:
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Datenquelle:
Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
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Proceedings International Test Conference 1990 (Cat. No.90CH2910-6)| 1990
- 23
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Challenge of design and test of ultra-large-scale circuitsYamada, A. et al. | 1990
- 25
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A method to calculate necessary assignments in algorithmic test pattern generationRajski, J. / Cox, H. et al. | 1990
- 35
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Global cost functions for test generationAbramovici, M. / Miller, D.T. / Henning, R. et al. | 1990
- 44
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ATPG for ultra-large structured designsWaicukauski, J.A. / Shupe, P.A. / Giramma, D.J. / Matin, A. et al. | 1990
- 52
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A diagnostic test pattern generation algorithmCamurati, P. / Medina, D. / Prinetto, P. / Sonza Reorda, M. et al. | 1990
- 59
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Analog test requirements of linear echo cancellation ISDN devicesOka, D.K. et al. | 1990
- 68
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Test features of the MC145472 ISDN U-transceiversBonet, L. / Ganger, J. / Girardeau, J. / Greaves, C. / Pendleton, M. / Yatim, D. et al. | 1990
- 80
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Fast and accurate testing of ISDN S/T interface devices using pseudo error rate techniquesSprinkle, B.W. et al. | 1990
- 86
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ATE-based functional ISDN testingLanier, K. et al. | 1990
- 95
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ASSIST (Allied Signal's Standardized Integrated Scan Test)Sapp, G. et al. | 1990
- 103
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Innovative techniques for improved testabilitySarkany, E.F. / Lusch, R.F. et al. | 1990
- 109
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Testability implemented in the VAX 6000 model 400Sweeney, J. et al. | 1990
- 115
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Scan based guided probe technology delivers Cyclone to the marketChoi, C.J. et al. | 1990
- 120
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Optimal placement of IEEE 1149.1 test port and boundary scan resources for wafer scale integrationLandis, D.L. / Singh, P. et al. | 1990
- 127
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Hierarchical self-test concept based on the JTAG standardMaierhofer, J. et al. | 1990
- 135
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Event qualification: a gateway to at-speed system testingWhetsel, L. et al. | 1990
- 142
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Mixed-mode ATPG under input constraintsGlover, C.T. et al. | 1990
- 152
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Multiple path sensitization for hierarchical circuit testingChau-Chin Su / Kime, C.R. et al. | 1990
- 162
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Functional test generation for finite state machinesCheng, K.T. / Jou, J.Y. et al. | 1990
- 169
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A comprehensive approach for modeling and testing analog and mixed-signal devicesSouders, T.M. / Stenbakken, G.N. et al. | 1990
- 177
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From specification to measurement: the bottleneck in analog industrial testingRijsinge, R.J. van / Haggenburg, A.A.R.M. / Vries, C. de / Wallinga, H. et al. | 1990
- 183
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A design-for-test methodology for active analog filtersSoma, M. et al. | 1990
- 193
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Stress profile derivation-an empirical approachWalker, A.C. et al. | 1990
- 208
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Automatic electro-optical testing of automobile dashboard displays in a factory environmentLangley, F.J. / Robinson, C.A. / Passero, R.A. et al. | 1990
- 214
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Time margin issues in disk drive testingGill, D. et al. | 1990
- 222
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A language for describing boundary-scan devicesParker, K.P. / Oresjo, S. et al. | 1990
- 235
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Boundary scan test used at board level: moving towards realityJong, F. de et al. | 1990
- 243
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ATPG issues for board designs implementing boundary scanSterba, D. / Halliday, A. / McClean, D. et al. | 1990
- 252
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Why, IDDQ? (CMOS IC testing)McEuen, S. et al. | 1990
- 253
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IDDQ testing because 'zero defects isn't enough': a Philips perspectiveBaker, K. / Verhelst, B. et al. | 1990
- 255
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Zero defects or zero stuck-at faults-CMOS IC process improvement with IDDQSoden, J.M. / Fritzemeier, R.R. / Hawkins, C.F. et al. | 1990
- 257
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Current testingMaly, W. et al. | 1990
- 258
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Concurrent engineeringLowenstein, A. / Schlosser, S. / Winter, G. et al. | 1990
- 260
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Obstacles and an approach towards concurrent engineeringBreuer, M.A. et al. | 1990
- 262
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QML (qualified manufacturing line): a method of providing high quality integrated circuitsDonlin, N.E. et al. | 1990
- 264
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Test engineers role in QMLThomas, R.W. et al. | 1990
- 265
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Testability preserving transformations in multi-level logic synthesisRajski, J. / Vasudevamurthy, J. et al. | 1990
- 274
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Sequential logic synthesis for testability using register-transfer level descriptionsGhosh, A. / Davadas, S. / Newton, A.R. et al. | 1990
- 284
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Design of integrated circuits fully testable for delay-faults and multifaultsDevadas, S. / Keutzer, K. et al. | 1990
- 294
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Functional test and diagnosis: a proposed JTAG sample mode scan testerLefebvre, M.E. et al. | 1990
- 304
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Scan test architectures for digital board testersFichtenbaum, M.L. / Robinson, G.D. et al. | 1990
- 311
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The boundary-scan master: target applications and functional requirementsYau, C.W. / Jarwala, N. et al. | 1990
- 316
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Efficient UBIST implementation for microprocessor sequencing partsNicolaidis, M. et al. | 1990
- 327
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Realization of an efficient design verification test used on a microinstruction controlled self testNozuyama, Y. et al. | 1990
- 337
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Testability considerations in the design of the MC68340 Integrated Processor UnitBishop, P.E. / Giles, G.L. / Iyengar, S.N. / Glover, C.T. / Law, W.-o. et al. | 1990
- 347
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A high-speed pin-memory architecture using multiport dynamic RAMsTsai, S.J. / Lee, W.J. et al. | 1990
- 355
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Sequencer Per Pin test system architectureWest, B. / Napier, T. et al. | 1990
- 362
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Multiplexing test system channels for data rates above 1 Gb/sKeezer, D.C. et al. | 1990
- 369
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Design of scan-testable CMOS sequential circuitsPark, B.H. / Menon, P.R. et al. | 1990
- 377
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An optimization based approach to the partial scan design problemChickermane, V. / Patel, J.H. et al. | 1990
- 387
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Arrangement of latches in scan-path design to improve delay fault coverageMao, W. / Ciletti, M.D. et al. | 1990
- 394
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An interactive environment for the transparent logic simulation and testing of integrated circuitsCastrodale, G.L. / Dollas, A. / Krakow, W.T. et al. | 1990
- 404
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ASIC CAD system based on hierarchical design-for-testabilityEmori, M. / Aikyo, T. / Machida, Y. / Shikatani, J.-i. et al. | 1990
- 410
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CMP3F: a high speed fault simulator for the Connection MachineAgrawal, A. / Bhattacharya, D. et al. | 1990
- 417
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On the charge sharing problem in CMOS stuck-open fault testingLee, K.J. / Breuer, M.A. et al. | 1990
- 427
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Increased CMOS IC stuck-at fault coverage with reduced IDDQ test setsFritzemeier, R.R. / Soden, J.M. / Treece, R.K. / Hawkins, C.F. et al. | 1990
- 436
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Testing for parametric faults in static CMOS circuitsFerguson, F.J. / Taylor, M. / Larrabee, T. et al. | 1990
- 444
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Frequency enhancement of digital VLSI test systemsAckner, L. / Barber, M.R. et al. | 1990
- 452
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Criteria for analyzing high frequency testing performance of VLSI automatic test equipmentBurlison, P. et al. | 1990
- 462
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Critical parameters for high-performance dynamic response measurementsMurray, D.F. / Nash, C.M. et al. | 1990
- 472
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Integrating boundary scan test into an ASIC design flowMuris, M. et al. | 1990
- 478
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A study of the optimization of DC parametric testsChang, J.M. et al. | 1990
- 488
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Direct access test scheme-design of block and core cells for embedded ASICsImmaneni, V. / Raman, S. et al. | 1990
- 493
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Color reproduction test for CCD image sensorsKato, H. et al. | 1990
- 498
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A rapid dither algorithm advances A/D converter testingWeimer, J. / Baade, K. / Fitzsimmons, J. / Lowe, B. et al. | 1990
- 508
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An advanced test system architecture for synchronous and asynchronous control of mixed signal device testingKurita, J. / Kasuga, N. / Hiwada, K. et al. | 1990
- 514
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An analysis of ATE computational architectureTaylor, A.R. et al. | 1990
- 520
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Hierarchical test assembly for macro based VLSI designLeenstra, J. / Spaanenburg, L. et al. | 1990
- 530
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enVision: the inside storyOrgan, D. et al. | 1990
- 537
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State transition graph analysis as a key to BIST fault coverageBrynestad, O. / Aas, E.J. / Vallestad, A.E. et al. | 1990
- 544
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Error masking in self-testable circuitsStroele, A.P. / Wunderlich, H.J. et al. | 1990
- 553
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A study of faulty signatures using a matrix formulationChan, J.C. / Abraham, J.A. et al. | 1990
- 562
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An architecture for high-speed analog in-circuit testingKlein, L. / Bridgeman, J. et al. | 1990
- 565
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Diagnosis for wiring interconnectsCheng, W.T. / Lewandowski, J.L. / Wu, E. et al. | 1990
- 572
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Interconnect testing of boards with partial boundary scanRobinson, G.D. / Deshayes, J.G. et al. | 1990
- 582
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Towards a standard approach for controlling board-level test functionsDervisoglu, B.I. et al. | 1990
- 591
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A new approach to mixed-signal diagnosisRastogi, R. / Sierzega, K. et al. | 1990
- 598
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Fast embedded A/D converter testing using the microcontroller's resourcesBobba, R. / Stevens, B. et al. | 1990
- 605
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A fourth generation analog incircuit program generatorCrook, D.T. et al. | 1990
- 613
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Jitter minimization technique for mixed signal testingFurukawa, Y. / Kimura, M. / Sugai, M. / Kimura, S. / Purtell, M. et al. | 1990
- 620
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Networking verification process and environments: an extension of the product realization process for new network capabilitiesMastoris, Y.M. / Nash, P.D. et al. | 1990
- 627
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Optimized testing of meshesMalek, M. / Ozden, B. et al. | 1990
- 638
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Identification of faulty processing elements by space-time compression of test responsesKarpovsky, M.G. / Levitin, L.B. / Vainstein, F.S. et al. | 1990
- 648
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Failure probability algorithm for test systems to reduce false alarmsAllen, D.R. et al. | 1990
- 657
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A multiple seed linear feedback shift registerSavir, J. / McAnney, W.H. et al. | 1990
- 660
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A new procedure for weighted random built-in self-testMuradali, F. / Agarwal, V.K. / Nadeau-Dostie, B. et al. | 1990
- 670
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Generating pseudo-exhaustive vectors for external testingHellebrand, S. / Wunderlich, H.J. / Haberl, O.F. et al. | 1990
- 680
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Computer-aided design of pseudoexhaustive BIST for semiregular circuitsChau-Chin Su / Kime, C.R. et al. | 1990
- 690
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Fault simulation of logic designs on parallel processors with distributed memoryHuisman, L.M. / Daoud, R. et al. | 1990
- 698
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Experimental evaluation of concurrent fault simulation algorithms on scalable, hierarchically defined test casesNicholls, W.H. / Nordsieck, A.W. / Soma, M. et al. | 1990
- 706
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Parallel pattern fault simulation based on stem faults in combinational circuitsSong, O. / Menon, P.R. et al. | 1990
- 712
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An experimental study on reject ratio prediction for VLSI circuits: Kokomo revisitedDas, D.V. / Seth, S.C. / Wagner, P.T. / Anderson, J.C. / Agrawal, V.D. et al. | 1990
- 721
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Extending binary searches to two and three dimensions (IC testing)Hickling, R.L. et al. | 1990
- 726
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AC product defect level and yield lossSavir, J. et al. | 1990
- 739
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Macro-testability and the VSPMehtani, R. / Baker, K. / Huizer, C.M. / Hynes, P.J. / Beers, J. van et al. | 1990
- 749
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Testability features of the 68040Gallup, M.G. / Ledbetter, W. jun. / McGarity, R. / McMahan, S. / Scheuer, K.C. / Shepard, C.G. / Sood, L. et al. | 1990
- 758
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Fault grading the Intel 80486Gollakota, N. / Zaidi, A. et al. | 1990
- 762
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Analysis of cellular automata used as pseudorandom pattern generatorsBardell, P.H. et al. | 1990
- 769
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Cellular automata based self-test for programmable data pathsSas, J. van / Catthoor, F. / De Man, H. et al. | 1990
- 779
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Design of signature circuits based on weight distributions of error-correcting codesIwasaki, K. / Yamaguchi, N. et al. | 1990
- 786
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Why is less information from logic simulation more useful in fault simulation?Akers, S.B. / Park, S. / Krishnamurthy, B. / Swaminathan, A. et al. | 1990
- 801
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The dynamic reduction of fault simulationMaamari, F. / Rajski, J. et al. | 1990
- 809
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Single-fault fault collapsing analysis in sequential logic circuitsChen, J.E. / Chung Len Lee / Wen Zen Shen et al. | 1990
- 815
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A BIST scheme using microprogram ROM for large capacity memoriesKoike, H. / Takeshima, T. / Takada, M. et al. | 1990
- 823
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Analysis of failures on memories using expert system techniquesViacroze, T. / Lequeux, M. et al. | 1990
- 833
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A novel built-in self-repair approach to VLSI memory yield enhancementMazumder, P. / Yih, J.S. et al. | 1990
- 842
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CMOS bridging fault detectionStorey, T.M. / Maly, W. et al. | 1990
- 852
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Bridging faults and their implication to PLAsChandramouli, V. / Gulati, R.K. / Dandapani, R. / Goel, D.K. et al. | 1990
- 860
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Diagnosing CMOS bridging faults with stuck-at fault dictionariesMillman, S.D. / McCluskey, E.J. / Acken, J.M. et al. | 1990
- 871
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EEODM: An effective BIST scheme for ROMsZorian, Y. / Ivanov, A. et al. | 1990
- 880
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Built-in self-test in a 24 bit floating point digital signal processorSakashita, N. / Sawai, H. / Teraoka, E. / Fujiyama, T. / Kengaku, T. / Shimazu, Y. / Tokuda, T. et al. | 1990
- 886
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Complete self-test architecture for a coprocessor (cryptography)Schwair, T.M. / Ritter, H.C. et al. | 1990
- 891
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High-speed fixture interconnects for mixed-signal IC testingMielke, J.A. / Pope, K.A. et al. | 1990
- 896
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Improving wafer sort yields with radius-tip probesSchleifer, S. et al. | 1990
- 900
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A fine pitch probe technology for VLSI wafer testingTada, T. / Takagi, R. / Nakao, S. / Hyozo, M. / Arakawa, T. / Sawada, K. / Ueda, M. et al. | 1990
- 907
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The capability of capability indices with an application to guardbanding in a test environmentMullenix, P. et al. | 1990
- 916
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Technique for transfer of analog prototypes (DV's) to productionPalumbo, M.P. et al. | 1990
- 924
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The use of tolerance intervals in the characterization of semiconductor devicesHadeed, Y.T. / Lewis, K.T. et al. | 1990
- 929
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Functional and IDDQ testing on a static RAMMeershoek, R. / Verhelst, B. / McInerney, R. / Thijssen, L. et al. | 1990
- 938
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Empirical failure analysis and validation of fault models in CMOS VLSIPancholy, A. / Rajski, J. / McNaughton, L.J. et al. | 1990
- 948
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On the evaluation of process-fault tolerance ability of CMOS integrated circuitsSicard, E. / Kinoshita, K. et al. | 1990
- 955
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A testable design of logic circuits under highly observable conditionXiaoqing, W. / Kinoshita, K. et al. | 1990
- 964
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Minimal overhead modification of iterative logic arrays for C-testabilityKu, T.W. / Soma, M. et al. | 1990
- 970
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Practical partitioning for testability with time-shared boundary scanMakki, R.Z. / Palaniswami, K. et al. | 1990
- 978
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The Waveform and Vector Exchange Specification (WAVES)Moran, L. / Hillman, R. / Burlison, P. / Gurda, T. et al. | 1990
- 988
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Development of a new standard for testSebesta, W.W. / Verhelst, B. / Wahl, M.G. et al. | 1990
- 994
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Wave+: An easy-to-use vector generation language for compilersHanda, M. / Steinweg, R.L. et al. | 1990
- 1000
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Weighted random test program generation for a per-pin testerGartner, J. / Driscoll, B. / Forlenza, D. / Forlenza, O. / Koprowski, T. / Lizambri, T. / Olsen, R. / Robertson, S. / Ryan, P. / Walter, A. et al. | 1990
- 1006
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An empirical relationship between test transparency and fault coverageElo, R.B. et al. | 1990
- 1012
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Failure coverage of functional test methods: a comparative experimental evaluationVelazco, R. / Bellon, C. / Martinet, B. et al. | 1990
- 1018
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Errors in testingWilliams, R.H. / Hawkins, C.F. et al. | 1990
- 1028
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An improved procedure to test CMOS ICs for latch-upMenozzi, R. / Lanzoni, M. / Selmi, L. / Ricco, B. et al. | 1990
- 1035
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A picosecond external electro-optic prober using laser diodesShinagawa, M. / Nagatsuma, T. et al. | 1990
- 1040
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New approach to integrate LSI design databases with e-beam testerHu, A. / Niijima, H. et al. | 1990
- 1049
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Marginal fault diagnosis based on e-beam static fault imaging with CAD interfaceKuji, N. / Matsumoto, K. et al. | 1990
- 1055
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TDRC-a symbolic simulation based design for testability rules checkerVarma, P. et al. | 1990
- 1065
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Testable design and support tool for cell based testOgihara, T. / Koseko, Y. / Yonemori, G. / Kawai, H. et al. | 1990
- 1072
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On automatic testpoint insertion in sequential circuitsGundlach, H.H.S. / Muller-Glaser, K.D. et al. | 1990