-Particle-Induced Soft Errors in Submicron SOI SRAM (Englisch)
- Neue Suche nach: Tosaka, Y.
- Neue Suche nach: Suzuki, K.
- Neue Suche nach: Sugii, T.
- Neue Suche nach: IEEE| Japan Society of Applied Physics
- Neue Suche nach: Tosaka, Y.
- Neue Suche nach: Suzuki, K.
- Neue Suche nach: Sugii, T.
- Neue Suche nach: IEEE| Japan Society of Applied Physics
In:
VLSI technology
;
39-40
;
1995
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ISBN:
-
ISSN:
- Aufsatz (Konferenz) / Print
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Titel:-Particle-Induced Soft Errors in Submicron SOI SRAM
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Beteiligte:Tosaka, Y. ( Autor:in ) / Suzuki, K. ( Autor:in ) / Sugii, T. ( Autor:in ) / IEEE| Japan Society of Applied Physics
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Kongress:15th Symposium, VLSI technology ; 1995 ; Kyoto; Japan
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Erschienen in:VLSI technology ; 39-40SYMPOSIUM ON VLSI TECHNOLOGY ; 39-40
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Verlag:
- Neue Suche nach: IEEE
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Erscheinungsdatum:01.01.1995
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Format / Umfang:2 pages
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Anmerkungen:IEEE cat no 95CB3578-1
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ISBN:
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ISSN:
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Medientyp:Aufsatz (Konferenz)
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Format:Print
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Sprache:Englisch
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Schlagwörter:
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Datenquelle:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
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High performance sub-tenth micron CMOS using advanced boron doping and WSi/sub 2/ dual gate processTakeuchi, K. / Yamamoto, T. / Furukawa, A. / Tamura, T. / Yoshida, K. et al. | 1995
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A 6.93-/spl mu/m/sup 2/ n-gate full CMOS SRAM cell technology with high-performance 1.8-V dual-gate CMOS for peripheral circuitsMinami, M. / Ohki, N. / Ishida, H. / Yamanaka, T. / Ishibashi, K. / Shimizu, A. / Kure, T. / Nishida, T. / Nagano, T. et al. | 1995
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A Fully Planarized 0.25 m CMOS Technology for 256 Mbit DRAM and BeyondBronner, G. / Aochi, H. / Gall, M. / Gambino, J. / IEEE| Japan Society of Applied Physics et al. | 1995
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A fully planarized 0.25 micron technology for 256 Mbit DRAM and beyondBronner, G. / Aochi, H. / Gall, M. / Gambino, J. / Gernhardt, S. / Hammerl, E. / Ho, H. / Iba, J. et al. | 1995
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- 17
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New CoSi/sub 2/ SALICIDE technology for 0.1 /spl mu/m processes and belowWang, Q.F. / Maex, K. / Kubicek, S. / Jonckheere, R. / Kerkwijk, B. / Verbeeck, R. / Biesemans, S. / De Meyer, K. et al. | 1995
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New CoSi2 SALICIDE technology for 0.1 micron processes and belowWang, Q.F. / Maex, K. / Kubicek, S. / Jonckheere, R. / Kerkwijk, B. / Verbeeck, R. et al. | 1995
- 19
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- 19
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Highly reliable 0.15 /spl mu/m MOSFETs with Surface Proximity Gettering (SPG) and nitrided oxide spacer using nitrogen implantationKuroi, T. / Shimizu, S. / Furukawa, A. / Komori, S. / Kawasaki, Y. / Kusunoki, S. / Okumura, Y. / Inuishi, N. / Tsubouchi, N. / Horie, K. et al. | 1995
- 21
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- 21
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The influence of oxygen at epitaxial Si/Si substrate interface for 0.1 /spl mu/m epitaxial Si channel N-MOSFETs grown by UHV-CVDOhguro, T. / Sugiyama, N. / Imai, K. / Usuda, K. / Saito, M. / Yoshitomi, T. / Ono, M. / Momose, H.S. / Iwai, H. et al. | 1995
- 23
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A Channel Engineering Combined with Channel Epitaxy Optimization and TED Suppression for 0.15 m n-n Gate CMOS TechnologyAbiko, H. / Ono, A. / Ueno, R. / Masuoka, S. / IEEE| Japan Society of Applied Physics et al. | 1995
- 23
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A channel engineering combined with channel epitaxy optimization and TED suppression for 0.15 /spl mu/m n-n gate CMOS technologyAbiko, H. / Ono, A. / Ueno, R. / Masuoka, S. / Shishiguchi, S. / Nakajima, K. / Sakai, I. et al. | 1995
- 25
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Copper Integration into 0.5 m BiCMOS TechnologyGelatos, A. V. / Nguyen, B.-Y. / Perry, K. / Marsh, R. / IEEE| Japan Society of Applied Physics et al. | 1995
- 25
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Copper integration into 0.5 /spl mu/m BiCMOS technologyGelatos, A.V. / Nguyen, B.-Y. / Perry, K. / Marsh, R. / Peschke, J. / Filipiak, S. / Travis, E. / Bhat, N. / La, L.B. / Thompson, M. et al. | 1995
- 25
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Copper integration into 0.5 micron BiCMOS technologyGelatos, A.V. / Nguyen, B.Y. / Perry, K. / Marsh, R. / Peschke, J. / Filipiak, S. / Travis, E. / Bhat, N. et al. | 1995
- 27
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A half-micron pitch Cu interconnection technologyUeno, K. / Ohto, K. / Tsunenari, K. et al. | 1995
- 29
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- 31
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- 33
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- 33
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High-Current, Small Parasitic Capacitance MOS FET on a Poly-Si Interlayered (PSI:psi) SOI WaferHoriuchi, M. / Teshima, T. / Tokumasu, K. / Yamaguchi, K. / IEEE| Japan Society of Applied Physics et al. | 1995
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High-Current, Small Parasitic Capacitance MOS FET on a Poly-Si Interlayered(PSI:cap psi) SOI WaferHoriuchi, M. / Teshima, T. / Tokumasu, K. / Yamaguchi, K. / IEEE| Japan Society of Applied Physics et al. | 1995
- 35
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Suppression of the floating-body effects in SOI MOSFETs by bandgap engineeringTerauchi, M. / Yoshimi, M. / Ushiku, Y. et al. | 1995
- 37
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A PELOX isolated sub-0.5 micron thin-film SOI technologyGilbert, P.V. / Sun, S.-W. et al. | 1995
- 39
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-Particle-Induced Soft Errors in Submicron SOI SRAMTosaka, Y. / Suzuki, K. / Sugii, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 39
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/spl alpha/-particle-induced soft errors in submicron SOI SRAMTosaka, Y. / Suzuki, K. / Sugii, T. et al. | 1995
- 41
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- 43
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- 45
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Application of force fill Al-plug technology to 64 Mbit DRAM and 0.35 micron logicMizobuchi, K. / Hamamoto, K. / Utsugi, M. / Dixit, G.A. / Poarch, S. / Havemann, R.H. et al. | 1995
- 45
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Application of force fill Al-plug technology to 64 Mb DRAM and 0.35 /spl mu/m logicMizobuchi, K. / Hamamoto, K. / Utsugi, M. / Dixit, G.A. / Poarch, S. / Havemann, R.H. / Dobson, C.D. / Jeffryes, A.I. / Holverson, P.J. / Rich, P. et al. | 1995
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Fully integrated multilevel interconnect process for low cost sub-half-micron ASIC applicationsNorishima, M. / Matsuno, T. / Anand, M.B. / Murota, M. / Inohara, M. / Inoue, K. / Ohtani, H. / Miyamoto, K. / Ogawa, R. / Seto, M. et al. | 1995
- 49
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Evolution of Integrated Electronics from Microelectronics to Nanoelectronics (Invited)Sugano, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 49
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Evolution of integrated electronics from microelectronics to nanoelectronicsSugano, T. et al. | 1995
- 53
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Manufacturing Gigachips in the Year 2005 (Invited)Chatterjee, P. K. / Doering, R. / IEEE| Japan Society of Applied Physics et al. | 1995
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Low Capacitance Multilevel Interconnection Using Low- Organic Spin-on Glass for Quarter-Micron High-Speed ULSIsFurusawa, T. / Homma, Y. / IEEE| Japan Society of Applied Physics et al. | 1995
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- 65
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- 65
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A symmetric 0.25 /spl mu/m CMOS technology for low-power, high-performance ASIC applications using 248 nm DUV lithographyBoulin, D.M. / O'Connor, K.J. / Bevk, J. / Brasen, D. / Cheng, M. / Cirelli, R.A. / Eshraghi, S.A. / Green, M.L. / Guinn, K.V. / Hillenius, S.J. et al. | 1995
- 67
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- 67
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A Self-Aligned Counter Well-Doping Technology Utilizing Channeling Ion Implantation and Its Application to 0.25 m CMOS ProcessNakamura, H. / Horiuchi, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 69
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- 71
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- 75
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- 75
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- 77
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- 77
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Analysis of Critical Dimension Control for Optical-, EB-, and X-Ray Lithography below the 0.2-m RegionFukuda, H. / Okazaki, S. / IEEE| Japan Society of Applied Physics et al. | 1995
- 79
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Phase Edge Lithography for Sub 0.1 m Electrical Channel Length in a 200 MM Full CMOS ProcessAgnello, P. / Newman, T. / Crabbe, E. / Subbanna, S. / IEEE| Japan Society of Applied Physics et al. | 1995
- 79
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Phase edge lithography for sub 0.1 /spl mu/m electrical channel length in a 200 mm full CMOS processAgnello, P. / Newman, T. / Crabbe, E. / Subbanna, S. / Ganin, E. / Liebmann, L. / Comfort, J. / Sunderland, D. et al. | 1995
- 81
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- 83
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- 85
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- 89
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- 91
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- 93
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Low-energy large-mass ion bombardment process for low-temperature high-quality silicon epitaxyShindo, W. / Ohmi, T. et al. | 1995
- 93
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- 97
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- 97
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- 97
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- 98
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- 98
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- 99
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- 105
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- 105
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- 107
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- 111
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High quality ultra-thin (4 nm) gate oxide by UV/O/sub 3/ surface pre-treatment of native oxideOhkubo, S. / Tamura, Y. / Sugino, R. / Nakanishi, T. / Sugita, Y. / Awaji, N. / Takasaki, K. et al. | 1995
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Isolation Dependence of Gate Oxide Quality at the LOCOS Edge Using an In-situ HCI-Based Pre-Gate PyrocleanAjuria, S. A. / Tobin, P. J. / Nguyen, B.-Y. / Limb, Y. / IEEE| Japan Society of Applied Physics et al. | 1995
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- 137
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0.29-/spl mu/m/sup 2/ trench cell technologies for 1G-bit DRAMs with open/folded-bit-line layout and selective growth techniqueNoguchi, M. / Ozaki, T. / Aoki, M. / Hamamoto, T. / Habu, M. / Kato, Y. / Takigami, Y. / Shibata, T. / Nakasugi, T. / Niiyama, H. et al. | 1995
- 137
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0.29-m^2 Trench Cell Technologies for 1G-Bit DRAMs with Open/Folded-Bit-Line Layout and Selective Growth TechniqueNoguchi, M. / Ozaki, T. / Aoki, M. / Hamamoto, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 137
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0.29 mum(exp2) trench cell technologies for 1-G-bit DRAMs with open/folded-bit-line layout and selective growth techniqueNoguchi, M. / Ozaki, T. / Aoki, M. / Hamamoto, T. / Habu, M. / Kato, Y. / Takigami, Y. et al. | 1995
- 139
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Planar gain cell for low voltage operation and gigabit memoriesKrautschneider, W.H. / Hofmann, F. / Ruderer, E. / Risch, L. et al. | 1995
- 141
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Leakage mechanism due to floating body and countermeasure on dynamic retention mode of SOI-DRAMMorishita, F. / Suma, K. / Hirose, M. / Tsuruda, T. / Yamaguchi, Y. / Eimori, T. / Oashi, T. / Arimoto, K. / Inoue, Y. / Nishimura, T. et al. | 1995
- 143
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A high performance 16M DRAM on a thin film SOIHyoung-Sub Kim, / Sang-Bo Lee, / Dong-Uk Choi, / Jae-Hoon Shim, / Kyu-Han Lee, / Kyu-Pil Lee, / Ki-Nam Kim, / Jong-Woo Park, et al. | 1995
- 145
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Direct measurement of the soft-error immunity on the DRAM well structure by using the nuclear microprobeOhno, Y. / Kishimoto, T. / Sayama, H. / Komori, S. / Kinomura, A. / Horino, Y. / Fujii, K. / Nishimura, T. / Takai, M. / Miyoshi, H. et al. | 1995
- 147
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Author index| 1995
- i
-
1995 Symposium on VLSI Technology. Digest of Technical Papers| 1995