Manufacturing technology challenges for low power electronics (Englisch)
- Neue Suche nach: Lemnios, Z.J.
- Neue Suche nach: Lemnios, Z.J.
In:
Symposium on VLSI Technology, 15
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5-8
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1995
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ISBN:
- Aufsatz (Konferenz) / Print
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Titel:Manufacturing technology challenges for low power electronics
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Weitere Titelangaben:Fertigungstechnologien für die Elektronik mit geringem Leistungsbedarf
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Beteiligte:Lemnios, Z.J. ( Autor:in )
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Erschienen in:
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Verlag:
- Neue Suche nach: IEEE Service Center
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Erscheinungsort:Piscataway
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Erscheinungsdatum:1995
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Format / Umfang:4 Seiten, 4 Bilder
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ISBN:
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Medientyp:Aufsatz (Konferenz)
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Format:Print
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Sprache:Englisch
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Schlagwörter:
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Datenquelle:
Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
- 1
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Semiconductor CIM system - innovation toward the year 2000Inoue, G. / Asakura, S. / Iiri, M. et al. | 1995
- 1
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Semiconductor CIM System; Innovation Toward The Year 2000 (Invited)Iiri, M. / Inoue, G. / Asakura, S. / IEEE| Japan Society of Applied Physics et al. | 1995
- 5
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Manufacturing Technology Challenges for Low Power Electronics (Invited)Lemnios, Z. J. / IEEE| Japan Society of Applied Physics et al. | 1995
- 5
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Manufacturing technology challenges for low power electronicsLemnios, Z.J. et al. | 1995
- 9
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High Performance Sub-Tenth Micron CMOS Using Advanced Boron Doping and WSi~2 Dual Gate ProcessTakeuchi, K. / Yamamoto, T. / Furukawa, A. / Tamura, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 11
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Silicided Silicon-Sidewall Source and Drain (S^4D) Structure for High-Performance 75-nm Gate Length pMOSFETsYoshitomi, T. / Saito, M. / Ohguro, T. / Ono, M. / IEEE| Japan Society of Applied Physics et al. | 1995
- 13
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A 6.93-m^2 n-Gate Full CMOS SRAM Cell Technology with High-Performance 1.8-V Dual-Gate CMOS for Peripheral CircuitsMinami, M. / Ohki, N. / Ishida, H. / Yamanaka, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 13
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A 6.93 micron2 n-gate full CMOS SRAM cell technology with high-performance 1.8 V dual-gate CMOS for peripheral circuitsMinami, M. / Ohki, N. / Ishida, H. / Yamanaka, T. / Ishibashi, K. / Shimidu, A. / Kure, T. et al. | 1995
- 15
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A Fully Planarized 0.25 m CMOS Technology for 256 Mbit DRAM and BeyondBronner, G. / Aochi, H. / Gall, M. / Gambino, J. / IEEE| Japan Society of Applied Physics et al. | 1995
- 15
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A fully planarized 0.25 micron technology for 256 Mbit DRAM and beyondBronner, G. / Aochi, H. / Gall, M. / Gambino, J. / Gernhardt, S. / Hammerl, E. / Ho, H. / Iba, J. et al. | 1995
- 17
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New CoSi~2 SALICIDE Technology for 0.1 m Processes and BelowWang, Q. F. / Maex, K. / Kubicek, S. / Jonckheere, R. / IEEE| Japan Society of Applied Physics et al. | 1995
- 17
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New CoSi2 SALICIDE technology for 0.1 micron processes and belowWang, Q.F. / Maex, K. / Kubicek, S. / Jonckheere, R. / Kerkwijk, B. / Verbeeck, R. et al. | 1995
- 19
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Highly Reliable 0.15 m MOSFETs with Surface Proximity Gettering(SPG) and Nitrided Oxide Spacer Using Nitrogen ImplantationKuroi, T. / Shimizu, S. / Furukawa, A. / Komori, S. / IEEE| Japan Society of Applied Physics et al. | 1995
- 21
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The Influence of Oxygen at Epitaxial Si/Si Substrate Interface for 0.1 m Epitaxial Si Channel N-MOSFETs Grown by UHV-CVDOhguro, T. / Sugiyama, N. / Imai, K. / Usuda, K. / IEEE| Japan Society of Applied Physics et al. | 1995
- 23
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A Channel Engineering Combined with Channel Epitaxy Optimization and TED Suppression for 0.15 m n-n Gate CMOS TechnologyAbiko, H. / Ono, A. / Ueno, R. / Masuoka, S. / IEEE| Japan Society of Applied Physics et al. | 1995
- 25
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Copper Integration into 0.5 m BiCMOS TechnologyGelatos, A. V. / Nguyen, B.-Y. / Perry, K. / Marsh, R. / IEEE| Japan Society of Applied Physics et al. | 1995
- 25
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Copper integration into 0.5 micron BiCMOS technologyGelatos, A.V. / Nguyen, B.Y. / Perry, K. / Marsh, R. / Peschke, J. / Filipiak, S. / Travis, E. / Bhat, N. et al. | 1995
- 27
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A Half-Micron Pitch Cu Interconnection TechnologyUeno, K. / Ohto, K. / Tsunenari, K. / IEEE| Japan Society of Applied Physics et al. | 1995
- 29
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Performance of MOCVD Tantalum Nitride Diffusion Barrier for Copper MetallizationSun, S. C. / Tsai, M. H. / Tsai, C. E. / Chiu, H. T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 31
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A Novel Self-Aligned Surface-Silicide Passivation Technology for Reliability Enhancement in Copper InterconnectsTakewaki, T. / Ohmi, T. / Nitta, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 33
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High-Current, Small Parasitic Capacitance MOS FET on a Poly-Si Interlayered (PSI:psi) SOI WaferHoriuchi, M. / Teshima, T. / Tokumasu, K. / Yamaguchi, K. / IEEE| Japan Society of Applied Physics et al. | 1995
- 33
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High-Current, Small Parasitic Capacitance MOS FET on a Poly-Si Interlayered(PSI:cap psi) SOI WaferHoriuchi, M. / Teshima, T. / Tokumasu, K. / Yamaguchi, K. / IEEE| Japan Society of Applied Physics et al. | 1995
- 35
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Suppression of the Floating-Body Effects in SOI MOSFETs by Bandgap EngineeringTerauchi, M. / Yoshimi, M. / Murakoshi, A. / Ushiku, Y. / IEEE| Japan Society of Applied Physics et al. | 1995
- 37
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A PELOX Isolated Sub-0.5 Micron Thin-Film SOI TechnologyGilbert, P. V. / Sun, S.-W. / IEEE| Japan Society of Applied Physics et al. | 1995
- 39
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-Particle-Induced Soft Errors in Submicron SOI SRAMTosaka, Y. / Suzuki, K. / Sugii, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 41
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Novel Si Surface Cleaning Technology with Plasma Hydrogenation and Its Application to Selective CVD-W Clad Layer FormationKosugi, T. / Ishii, H. / Arita, Y. / IEEE| Japan Society of Applied Physics et al. | 1995
- 43
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Pressure-Controlled Two-Step TEOS-O~3 CVD Eliminating the Base Material EffectSaito, M. / Kudoh, Y. / Homma, Y. / IEEE| Japan Society of Applied Physics et al. | 1995
- 45
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Application of Force Fill Al-Plug Technology to 64 Mb DRAM and 0.35 m LogicMizobuchi, K. / Hamamoto, K. / Utsugi, M. / Dixit, G. A. / IEEE| Japan Society of Applied Physics et al. | 1995
- 45
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Application of force fill Al-plug technology to 64 Mbit DRAM and 0.35 micron logicMizobuchi, K. / Hamamoto, K. / Utsugi, M. / Dixit, G.A. / Poarch, S. / Havemann, R.H. et al. | 1995
- 47
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Fully Integrated Multilevel Interconnect Process for Low Cost Sub-Half-Micron ASIC ApplicationsNorishima, M. / Matsuno, T. / Anand, M. B. / Murota, M. / IEEE| Japan Society of Applied Physics et al. | 1995
- 49
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Evolution of Integrated Electronics from Microelectronics to Nanoelectronics (Invited)Sugano, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 49
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Evolution of integrated electronics from microelectronics to nanoelectronicsSugano, T. et al. | 1995
- 53
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Manufacturing Gigachips in the Year 2005 (Invited)Chatterjee, P. K. / Doering, R. / IEEE| Japan Society of Applied Physics et al. | 1995
- 53
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Manufacturing gigachips in the year 2005Chatterjee, P.K. / Doering, R.R. et al. | 1995
- 57
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Sub-Quarter Micron Titanium Salicide Technology with In-Situ Silicidation Using High-Temperature SputteringFujii, K. / Kikuta, K. / Kikkawa, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 59
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Low Capacitance Multilevel Interconnection Using Low- Organic Spin-on Glass for Quarter-Micron High-Speed ULSIsFurusawa, T. / Homma, Y. / IEEE| Japan Society of Applied Physics et al. | 1995
- 59
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Low Capacitance Multilevel Interconnection Using Low-curly epsilon Organic Spin-on Glass for Quarter-Micron High-Speed ULSIsFurusawa, T. / Homma, Y. / IEEE| Japan Society of Applied Physics et al. | 1995
- 61
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Highly Porous Interlayer Dielectric for Interconnect Capacitance ReductionJeng, S.-P. / Taylor, K. / Seha, T. / Chang, M.-C. / IEEE| Japan Society of Applied Physics et al. | 1995
- 63
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Reoxidized Nitric Oxide(ReoxNO) Process and Its Effect on the Dielectric Reliability of the LOCOS EdgeMaiti, B. / Tobin, P. J. / Okada, Y. / Ajuria, S. / IEEE| Japan Society of Applied Physics et al. | 1995
- 65
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A symmetric 0.25 mum CMOS technology for low-power, high-performance ASIC applications using 248 nm DUV lithographyBaulin, D.M. / Mansfield, W.M. / O'Conor, K.J. / Berk, J. / Brasen, D. / Chena, M. / Cirelli, R.A. et al. | 1995
- 65
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A Symmetric 0.25 m CMOS Technology for Low-Power, High-Performance ASIC Applications Using 248 nm DUV LithographyBoulin, D. M. / Mansfield, W. M. / O'Connor, K. J. / Bevk, J. / IEEE| Japan Society of Applied Physics et al. | 1995
- 67
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A Self-Aligned Counter Well-Doping Technology Utilizing Channeling Ion Implantation and Its Application to 0.25 m CMOS ProcessNakamura, H. / Horiuchi, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 69
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Impact of the Reduction of the Gate to Drain Capacitance on Low Voltage Operated CMOS DevicesYamashita, K. / Nakaoka, H. / Kurimoto, K. / Umimoto, H. / IEEE| Japan Society of Applied Physics et al. | 1995
- 71
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Advantage of Small Geometry Silicon MOSFETs for High-Frequency Analog Applications under Low Power Supply Voltage of 0.5 VSaito, M. / Ono, M. / Fujimoto, R. / Takahashi, C. / IEEE| Japan Society of Applied Physics et al. | 1995
- 71
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Advantage of small geometry silicon MOSFETs for high-frequency analog applications under low power supply voltage 0.5 VSaito, M. / Ono, M. / Fujimoto, R. / Takahashi, C. / Tanimoto, H. / Ito, N. / Ohguro, T. et al. | 1995
- 73
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CVD SiNx Anti-Reflective Coating for Sub-0.5 m LithographyOng, T. P. / Roman, B. / Paulson, W. / Lin, J. H. / IEEE| Japan Society of Applied Physics et al. | 1995
- 75
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High Performance 0.3 m CMOS Using I-Line Lithography and BARCThakar, G. V. / Madan, S. K. / Garza, C. M. / Krisa, W. L. / IEEE| Japan Society of Applied Physics et al. | 1995
- 77
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Analysis of Critical Dimension Control for Optical-, EB-, and X-Ray Lithography below the 0.2-m RegionFukuda, H. / Okazaki, S. / IEEE| Japan Society of Applied Physics et al. | 1995
- 79
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Phase Edge Lithography for Sub 0.1 m Electrical Channel Length in a 200 MM Full CMOS ProcessAgnello, P. / Newman, T. / Crabbe, E. / Subbanna, S. / IEEE| Japan Society of Applied Physics et al. | 1995
- 81
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Boron as a Primary Source of Radiation in High Density DRAMSBaumann, R. / Hossain, T. / Smith, E. / Murata, S. / IEEE| Japan Society of Applied Physics et al. | 1995
- 83
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A New Method to Monitor Gate-Oxide Reliability DegradationCheung, K. P. / IEEE| Japan Society of Applied Physics et al. | 1995
- 85
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An ESD Protection Scheme for Deep Sub-Micron ULSI CircuitsSharma, U. / Campbell, J. / Choe, H. / Kuo, C. / IEEE| Japan Society of Applied Physics et al. | 1995
- 87
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Effects of Process-Induced Mechanical Stress on ESD PerformanceKubota, K. / Okuyama, K. / Miura, H. / Kawashima, Y. / IEEE| Japan Society of Applied Physics et al. | 1995
- 89
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An Etching Model to Predict Minimum-Microloading Gas PressureIzawa, M. / Kumihashi, T. / Ohji, Y. / IEEE| Japan Society of Applied Physics et al. | 1995
- 91
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Metal Etch with HI-Addition to Conventional ChemistryFrank, W. E. / IEEE| Japan Society of Applied Physics et al. | 1995
- 93
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Low-Energy Large-Mass Ion Bombardment Process for Low-Temperature High-Quality Silicon EpitaxyShindo, W. / Ohmi, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 93
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Low-energy large-mass ion bombardement process for low-temperature high-quality silicon epitaxyShindo, W. / Ohmi, T. et al. | 1995
- 95
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A Smart Batch Type RTA Technology for Beyond 256 Mbit DRAMLee, G. G. / Fujihara, K. / Kim, S. J. / Oh, C. W. / IEEE| Japan Society of Applied Physics et al. | 1995
- 97
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Gigabit DRAM vs Gigabit FlashKunio, T. / Ogura, S. / IEEE| Japan Society of Applied Physics et al. | 1995
- 97
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Mini-fabs vs Mega-fabsArai, E. / Doering, B. / IEEE| Japan Society of Applied Physics et al. | 1995
- 97
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Next Wafer Size -When Will It Happen?Abe, T. / Seidel, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 98
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Scaling Limit of Gate DielectricsTaniguchi, K. / Sun, J. Y.-C. / IEEE| Japan Society of Applied Physics et al. | 1995
- 98
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Interconnect Limitation for Sub-0.25 m Devices (Technology and Circuits Joint Session)Asada, K. / Ogawa, S. / Bidermann, W. / IEEE| Japan Society of Applied Physics et al. | 1995
- 99
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Accurate Modeling of Coulombic Scattering, and Its Impact on Scaled MOSFETsMujtaba, A. / Takagi, S. / Dutton, R. / IEEE| Japan Society of Applied Physics et al. | 1995
- 101
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Gate Current by Impact Ionization Feedback in Sub-Micron MOSFET TechnologiesBude, J. D. / IEEE| Japan Society of Applied Physics et al. | 1995
- 103
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Direct Observation of the Lateral Nonuniform Channel Doping Profile in Submicron MOSFET's from an Anomalous Charge Pumping Measurement ResultsChung, S. S. / Cheng, S. M. / Lee, G. H. / Guo, J. C. / IEEE| Japan Society of Applied Physics et al. | 1995
- 105
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Sub 0.1 m nMOSFETs Fabricated Using Experimental Design Techniques to Optimise Performance and Minimise Process SensitivityKubicek, S. / Biesemans, S. / Wang, Q. F. / Maex, K. / IEEE| Japan Society of Applied Physics et al. | 1995
- 105
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Sub 0.1 mum nMOSFETs fabricated using experimental design techniques to optimise performance and minimise process sensitivityKubicek, S. / Biesemann, S. / Wang, Q.F. / Maex, K. / Meyer, K. de et al. | 1995
- 107
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Novel oxynidridation technology for hihly reliable thin dielectricsJoo, Moon-Sig / Lee, Seok-Hee / Lee, Seok-Kiu / Ong, Byung-Jin / Kim, Jong-Choul et al. | 1995
- 107
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Novel Oxynitridation Technology for Highly Reliable Thin DielectricsJoo, M.-S. / Lee, S.-H. / Lee, S.-K. / Cho, B.-J. / IEEE| Japan Society of Applied Physics et al. | 1995
- 109
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Extending Gate Dielectric Scaling Limit by Use of Nitride or OxynitrideWang, X. W. / Shi, Y. / Ma, T. P. / Cui, G. J. / IEEE| Japan Society of Applied Physics et al. | 1995
- 111
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High Quality Ultra-Thin(4 nm) Gate Oxide by UV/O~3 Surface Pre-Treatment of Native OxideOhkubo, S. / Tamura, Y. / Sugino, R. / Nakanishi, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 113
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Isolation Dependence of Gate Oxide Quality at the LOCOS Edge Using an In-Situ HCI-Based Pre-Gate PyrocleanAjuria, S. A. / Tobin, P. J. / Nguyen, B.-Y. / Limb, Y. / IEEE| Japan Society of Applied Physics et al. | 1995
- 115
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High-Performance Sub-0.1-m CMOS with Low-Resistance T-Shaped Gates Fabricated by Selective CVD-WHisamoto, D. / Umeda, K. / Nakamura, Y. / Kobayashi, N. / IEEE| Japan Society of Applied Physics et al. | 1995
- 117
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A New SSS-OSELO Technology for 0.15-m Low-Defect IsolationSudoh, Y. / Kaga, T. / Yugami, J. / Kure, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 119
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Characteristics of CMOSFETs with Sputter-Deposited W/TiN Stack GateLee, D. H. / Joo, S. H. / Lee, G. H. / Moon, J. / IEEE| Japan Society of Applied Physics et al. | 1995
- 121
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Rapid Thermal Chemical Vapor Deposition of In-Situ Nitrogen-Doped Polysilicon for Dual Gate CMOSSun, S. C. / Wang, L. S. / Yeh, F. L. / Chen, C. H. / IEEE| Japan Society of Applied Physics et al. | 1995
- 123
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A Ferroelectric Capacitor over Bit-Line (F-COB) Cell for High Density Nonvolatile Ferroelectric MemoriesTanabe, N. / Matsuki, T. / Saitoh, S. / Takeuchi, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 125
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Ultra-Thin Fatigue Free Lead Zirconate Titanate Thin Films for Gigabit DRAMsTorii, K. / Kawakami, H. / Kushida, K. / Yano, F. / IEEE| Japan Society of Applied Physics et al. | 1995
- 127
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A Novel Low-Temperature Process for High Dielectric Constant BST Thin Films for ULSI DRAM ApplicationsKhamankar, R. / Jiang, B. / Tsu, R. / Hsu, W.-Y. / IEEE| Japan Society of Applied Physics et al. | 1995
- 129
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Fast and Accurate Programming Method for Multi-Level NAND EEPROMsHemink, G. J. / Tanaka, T. / Endoh, T. / Aritome, S. / IEEE| Japan Society of Applied Physics et al. | 1995
- 131
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A 62.8 GHz Fmax LP-CVD Epitaxially Grown Silicon Base Bipolar Transistor with Extremely High Early Voltage of 85.7 VYoshino, C. / Inou, K. / Matsuda, S. / Nakajima, H. / IEEE| Japan Society of Applied Physics et al. | 1995
- 133
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A Low Thermal Budget, Fully Self-Aligned Lateral BJT on Thin film SOI Substrate for Low Power BiCMOS ApplicationsChen, V. M. C. / Woo, J. C. S. / IEEE| Japan Society of Applied Physics et al. | 1995
- 135
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A New 3-D MCM Fabrication Technology for High-Speed Chip-to-Chip Communication: Vertically Connected Thin-Film Chip(VCTC) TechnologyTakahashi, S. / Onodera, T. / Hayashi, Y. / Kunio, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 137
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0.29-m^2 Trench Cell Technologies for 1G-Bit DRAMs with Open/Folded-Bit-Line Layout and Selective Growth TechniqueNoguchi, M. / Ozaki, T. / Aoki, M. / Hamamoto, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 137
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0.29 mum(exp2) trench cell technologies for 1-G-bit DRAMs with open/folded-bit-line layout and selective growth techniqueNoguchi, M. / Ozaki, T. / Aoki, M. / Hamamoto, T. / Habu, M. / Kato, Y. / Takigami, Y. et al. | 1995
- 139
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Planar Gain Cell for Low Voltage Operation and Gigabit MemoriesKrautschneider, W. H. / Hofmann, F. / Ruderer, E. / Risch, L. / IEEE| Japan Society of Applied Physics et al. | 1995
- 141
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Leakage Mechanism due to Floating Body and Countermeasure on Dynamic Retention Mode of SOI-DRAMMorishita, F. / Suma, K. / Hirose, M. / Tsuruda, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 143
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A High Performance 16M DRAM on a Thin Film SOIKim, H.-S. / Lee, S.-B. / Choi, D.-U. / Shim, J.-H. / IEEE| Japan Society of Applied Physics et al. | 1995
- 145
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Direct Measurement of the Soft-Error Immunity on the DRAM Well Structure by Using the Nuclear MicroprobeOhno, Y. / Kishimoto, T. / Sonoda, K. / Sayama, H. / IEEE| Japan Society of Applied Physics et al. | 1995