Low-latency digit-serial dual basis multiplier for lightweight cryptosystems (Englisch)
Freier Zugriff
- Neue Suche nach: Chiou, Che Wun
- Neue Suche nach: Lee, Chiou-Yng
- Neue Suche nach: Lin, Jim-Min
- Neue Suche nach: Yeh, Yun-Chi
- Neue Suche nach: Pan, Jeng-Shyang
- Neue Suche nach: Chiou, Che Wun
- Neue Suche nach: Lee, Chiou-Yng
- Neue Suche nach: Lin, Jim-Min
- Neue Suche nach: Yeh, Yun-Chi
- Neue Suche nach: Pan, Jeng-Shyang
In:
IET Information Security
;
11
, 6
;
301-311
;
2017
- Aufsatz (Zeitschrift) / Elektronische Ressource
-
Titel:Low-latency digit-serial dual basis multiplier for lightweight cryptosystems
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Beteiligte:Chiou, Che Wun ( Autor:in ) / Lee, Chiou-Yng ( Autor:in ) / Lin, Jim-Min ( Autor:in ) / Yeh, Yun-Chi ( Autor:in ) / Pan, Jeng-Shyang ( Autor:in )
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Erschienen in:IET Information Security ; 11, 6 ; 301-311
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Verlag:
- Neue Suche nach: The Institution of Engineering and Technology
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Erscheinungsdatum:13.07.2017
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Format / Umfang:11 pages
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ISSN:
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DOI:
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Medientyp:Aufsatz (Zeitschrift)
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Format:Elektronische Ressource
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Sprache:Englisch
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Schlagwörter:parallel processing , four-bit scheme , resource-constrained security applications , submultiplication units , systolic structures , critical path delay , computational complexity , low-latency digit-serial dual basis multiplier , finite field multiplication , space complexity , cryptosystems , resource allocation , cryptography , time complexity
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Datenquelle:
Metadata by IET is licensed under CC BY 3.0
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