Improving Defect Detection in Static-Voltage Testing (Englisch)
- Neue Suche nach: Renovell, M.
- Neue Suche nach: Azais, F.
- Neue Suche nach: Bertrand, Y.
- Neue Suche nach: Renovell, M.
- Neue Suche nach: Azais, F.
- Neue Suche nach: Bertrand, Y.
In:
IEEE DESIGN AND TEST OF COMPUTERS
;
19
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83-89
;
2002
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ISSN:
- Aufsatz (Zeitschrift) / Print
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Titel:Improving Defect Detection in Static-Voltage Testing
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Beteiligte:
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Erschienen in:IEEE DESIGN AND TEST OF COMPUTERS ; 19 ; 83-89
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Verlag:
- Neue Suche nach: IEEE INSTITUTE OF ELECTRICAL AND ELECTRONICS
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Erscheinungsdatum:01.01.2002
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Format / Umfang:7 pages
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ISSN:
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Medientyp:Aufsatz (Zeitschrift)
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Format:Print
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Sprache:Englisch
- Neue Suche nach: 621.395
- Weitere Informationen zu Dewey Decimal Classification
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Klassifikation:
DDC: 621.395 -
Datenquelle:
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Departments - EIC Message| 2002
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EIC Message| 2002
- 3
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Guest editor's introduction: what is infrastructure IP?Zorian, Y. et al. | 2002
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[Guest editor's introduction:] The reuse of complex architecturesMartin, G. et al. | 2002
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Theme Features - Characterizing Substrate Coupling in Deep-Submicron DesignsMiguel Silveira, Luis et al. | 2002
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Characterizing substrate coupling in deep-submicron designsSilveira, L.M. / Vargas, N. et al. | 2002
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Guest editors' introduction: defect-oriented testing in the deep-submicron eraSegura, J. / Maxwell, P. et al. | 2002
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Guest editor's introduction: processor-based designsMarwedel, P. et al. | 2002
- 5
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What Is Infrastructure IP?Zorian, Y. et al. | 2002
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Departments - News| 2002
- 6
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Developing architectural platforms: a disciplined approachMihal, A. / Kulkarni, C. / Moskewicz, M. / Tsai, M. / Shah, N. / Weber, S. / Yujia Jin, / Keutzer, K. / Vissers, K. / Sauer, C. et al. | 2002
- 6
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A large-area integrated multiprocessor system for video applicationsRudack, M. / Redeker, M. / Hilgenstock, J. / Moch, S. / Castagne, J. et al. | 2002
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SoC Multiprocessor Features - A Large-Area Integrated Multiprocessor System for Video ApplicationsRudack, Markus et al. | 2002
- 6
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ETM10 incorporates hardware segment of IEEE P1500McLaurin, T. / Ghosh, S. et al. | 2002
- 7
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Energy-monitoring tool for low-power embedded programsDongkun Shin, / Hojun Shim, / Yongsoo Joo, / Han-Saem Yun, / Jihong Kim, / Naehyuck Chang, et al. | 2002
- 8
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IDDQ Test: Will It Survive the DSM Challenge?Sabade, Sagar S. et al. | 2002
- 8
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ETM1O Incorporates Hardware Segment of IEEE P1500McLaurin, Teresa et al. | 2002
- 8
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I/sub DDQ/ test: will it survive the DSM challenge?Sabade, S.S. / Walker, D.M.H. et al. | 2002
- 12
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A strategy for mixed-signal yield improvementBordelon, J. / Tranchina, B. / Madangarli, V. / Craig, M. et al. | 2002
- 16
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Online testing approach for very deep-submicron ICsFavalli, M. / Metra, C. et al. | 2002
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Theme Features - Online Testing Approach for Very Deep-Submicron ICsFavalli, Michele et al. | 2002
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StepNP: a system-level exploration platform for network processorsPaulin, P.G. / Pilkington, C. / Bensoudane, E. et al. | 2002
- 18
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A complete strategy for testing an on-chip multiprocessor architectureAktouf, C. et al. | 2002
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Embedded software-based self-test for programmable core-based designsKrstic, A. / Wei-Cheng Lai, / Kwang-Ting Cheng, / Chen, L. / Dey, S. et al. | 2002
- 18
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Resistance characterization for weak open defectsMontanes, R.R. / de Gyvez, J.P. / Volf, P. et al. | 2002
- 18
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SoC Multiprocessor Features - A Complete Strategy for Testing an On-Chip Multiprocessor ArchitectureAktouf, Chouki et al. | 2002
- 22
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Embedded timing analysis: a soc infrastructureTabatabaei, S. / Ivanov, A. et al. | 2002
- 24
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I/sub DDQ/ testing for deep-submicron ICs: challenges and solutionsZhanping Chen, / Liqiong Wei, / Keshavarzi, A. / Roy, K. et al. | 2002
- 24
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Theme Features - Testing for Deep-Submicron ICs: Challenges and SolutionsChen, Zhanping et al. | 2002
- 24
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IDDQ Testing for Deep-Submicron ICs: Challenges and SolutionsChen, Z. / Wei, L. / Keshavarzi, A. / Roy, K. et al. | 2002
- 27
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Noise generation and coupling mechanisms in deep-submicron ICsAragones, X. / Gonzalez, J.L. / Moll, F. / Rubio, A. et al. | 2002
- 27
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Noise Generation and Coupling Mechanisms in Deep-Submicron lCsAragonès, Xavier et al. | 2002
- 27
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Embedded tools for a configurable and customizable DSP architectureLiem, C. / Breant, F. / Jadhav, S. / O'Farrell, R. / Ryan, R. / Levia, O. et al. | 2002
- 28
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A retargetable embedded in-circuit emulation module for microprocessorsIng-Jer Huang, / Chung-Fu Kao, / Hsin-Ming Chen, / Ching-Nan Juan, / Tai-An Lu, et al. | 2002
- 29
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Special ITC Feature - Modeling the Economics of Testing: A DFT PerspectiveNag, Pranab K. et al. | 2002
- 29
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Modeling the economics of testing: a DFT perspectiveNag, P.K. / Gattiker, A. / Sichao Wei, / Blanton, R.D. / Maly, W. et al. | 2002
- 34
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CMOS circuits with subvolt supply voltagesStan, M.R. et al. | 2002
- 34
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Theme Features - CMOS Circuits with Subvolt Supply VoltagesStan, Mircea R. et al. | 2002
- 35
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Design for debug: catching design errors in digital chipsVermeulen, B. / Goel, S.K. et al. | 2002
- 36
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Energy advantages of microprocessor platforms with on-chip configurable logicStitt, G. / Vahid, F. et al. | 2002
- 36
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Leakage and process variation effects in current testing on future CMOS circuitsKeshavarzi, A. / Tschanz, J.W. / Narendra, S. / De, V. / Daasch, W.R. / Roy, K. / Sachdev, M. / Hawkins, C.F. et al. | 2002
- 39
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A heterogeneous multiprocessor architecture for flexible media processingRutten, M.J. / van Eijndhoven, J.T.J. / Jaspers, E.G.T. / van der Wolf, P. / Gangwal, O.P. / Timmer, A. / Pol, E.-J.D. et al. | 2002
- 42
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Cost-effective deterministic partitioning for rapid diagnosis in scan-based BISTBayraktaroglu, I. / Orailoglu, A. et al. | 2002
- 42
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Special Features - Cost-Effective Deterministic Partitioning for Rapid Diagnosis in Scan-Based BISTBayraktaroglu, Ismet et al. | 2002
- 44
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High defect coverage with low-power test sequences in a BIST environmentGirard, P. / Landrault, C. / Pravossoudovitch, S. / Virazel, A. / Wunderlich, H.-J. et al. | 2002
- 44
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A hardware-software real-time operating system framework for SoCsMooney, V.J. / Blough, D.M. et al. | 2002
- 44
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Theme Features - Image Processing Techniques for Wafer Defect Cluster IdentificationHuang, Chenn-Jung et al. | 2002
- 44
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IP for embedded diagnosisPateras, S. et al. | 2002
- 44
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Image processing techniques for wafer defect cluster identificationChenn-Jung Huang, / Chi-Feng Wu, / Chua-Chin Wang, et al. | 2002
- 50
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Resizing rules for MOS analog-design reuseGalup-Montoro, C. / Schneider, M.C. / Coitinho, R.M. et al. | 2002
- 50
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Theme Features - Resizing Rules for MOS Analog Design ReuseGalup-Montoro, Carlos et al. | 2002
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Compiler design issues for embedded processorsLeupers, R. et al. | 2002
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Multiprocessor SoC platforms: a component-based design approachCesario, W.O. / Lyonnard, D. / Nicolescu, G. / Paviot, Y. / Sungjoo Yoo, / Jerraya, A.A. / Gauthier, L. / Diaz-Nava, M. et al. | 2002
- 54
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Special ITC Section - Guest Editors' Introduction: Stressing the FundamentalsAitken, Robert C. et al. | 2002
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Embedded robustness IPs for transient-error-free ICsDupont, E. / Nicolaidis, M. / Rohr, P. et al. | 2002
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Analyzing and diagnosing interconnect faults in bus-structured systemsJun Zhao, / Meyer, F.J. / Lombardi, F. et al. | 2002
- 54
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Guest editors' introduction: stressing the fundamentalsAitken, R.C. / Wheater, D.L. et al. | 2002
- 54
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Special Features - Analyzing and Diagnosing Interconnect Faults in Bus-Structured SystemsZhao, Jun et al. | 2002
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Special ITC Section - Efficient Sequential Test Generation Based on Logic SimulationSheng, Shuo et al. | 2002
- 56
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Efficient sequential test generation based on logic simulationShuo Sheng, / Hsiao, M.S. et al. | 2002
- 59
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FlexWare: a retargetable, embedded-software development environmentPaulin, P.G. / Santana, M. et al. | 2002
- 60
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Special Feature - Multilevel Testing for Design Verification of Embedded SystemsSchulz, Stephan et al. | 2002
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Multilevel testing for design verification of embedded systemsSchulz, S. / Buchenrieder, K.J. / Rozenblit, J.W. et al. | 2002
- 64
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Practical oscillation-based test of integrated filtersHuertas, G. / Vazquez, D. / Peralias, E.J. / Rueda, A. / Huertas, J.L. et al. | 2002
- 64
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Special Features - Practical Oscillation-Based Test of Integrated FiltersHuertas, Gloria et al. | 2002
- 65
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Special ITC Section - Extending OPMISR Beyond 10x Scan Test EfficiencyBarnhart, Carl et al. | 2002
- 65
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Extending OPMISR Beyond 10x Scan Test EfficiencyBarnhart, C. / Brunkhorst, V. / Distler, F. / Farnsworth, O. / Ferko, A. / Keller, B. / Scott, D. / Koenemann, B. / Onodera, T. et al. | 2002
- 65
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Extending OPMISR beyond 10/spl times/ scan test efficiencyBarnhart, C. / Brunkhorst, V. / Distler, F. / Farnsworth, O. / Ferko, A. / Keller, B. / Scott, D. / Koenemann, B. / Onodera, T. et al. | 2002
- 66
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Jitter testing for gigabit serial communication transceiversYi Cai, / Laquai, B. / Luehman, K. et al. | 2002
- 66
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Special Features - Jitter Testing for Gigabit Serial Communication TransceiversCai, Yi et al. | 2002
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Toward CAD-IP reuse: a web bookshelf of fundamental algorithmsCaldwell, A.E. / Markov, I.L. / Kahng, A.B. et al. | 2002
- 70
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The Road Ahead - Shared red bricksKahng, A.B. et al. | 2002
- 72
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Guest editors' introduction: hot topics at this year's design automation conferenceBlaauw, D. / Lavagno, L. et al. | 2002
- 72
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Special DAC Section - Guest Editors' Introduction: Hot Topics at This Year's Design Automation ConferenceBlaauw, David et al. | 2002
- 72
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Standards - The IEEE standards processAshenden, P.J. et al. | 2002
- 72
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Special Features - Toward CAD-IP Reuse: A Web Bookshelf of Fundamental AlgorithmsCaldwell, Andrew E. et al. | 2002
- 73
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Testing mixed-signal cores: a practical oscillation-based test in an analog macrocellHuertas, G. / Vazquez, D. / Peralias, E.J. / Rueda, A. / Huertas, J.L. et al. | 2002
- 73
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Special Features - Testing Mixed-Signal Cores: A Practical Oscillation-Based Test in an Analog MacrocellHuertas, Gloria et al. | 2002
- 74
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Panel Summaries - ITC 2001 panels: part 2Stolicny, C. et al. | 2002
- 74
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Behavioral simulation of fractional-N frequency synthesizers and other PLL circuitsPerrott, M.H. et al. | 2002
- 74
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Neighborhood selection for I/sub DDQ/ outlier screening at wafer sortDaasch, W.R. / McNames, J. / Madge, R. / Cota, K. et al. | 2002
- 74
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Special ITC Section - Neighborhood Selection for IDDQ Outlier Screening at Wafer SortDaasch, W.Robert et al. | 2002
- 74
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Special DAC Section - Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL CircuitsPerrott, Michael H. et al. | 2002
- 74
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Neighborhood Selection for I~D~D~Q Outlier Screening at Wafer SortDaasch, W. R. / McNames, J. / Madge, R. / Cota, K. et al. | 2002
- 76
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Improving SoC design quality through a reproducible design flowMagarshack, P. et al. | 2002
- 76
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Special Features - Improving SoC Design quality through a Reproducible Design FlowMagarshack, Philippe et al. | 2002
- 80
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The last byte - Yet another thiotimoline applicationNelson, R. et al. | 2002
- 82
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Special Features - Survey of Low-Power Testing of VLSI CircuitsGirard, Patrick et al. | 2002
- 82
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Survey of low-power testing of VLSI circuitsGirard, P. et al. | 2002
- 82
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Multilevel testability analysis and solutions for integrated Bluetooth transceiversOzev, S. / Orailoglu, A. / Olgaard, C.V. et al. | 2002
- 82
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Special ITC Section - Multilevel Testability Analysis and Solutions for Integrated Bluetooth TransceiversOzev, Sule et al. | 2002
- 83
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Improving defect detection in static-voltage testingRenovell, M. / Azais, F. / Bertrand, Y. et al. | 2002
- 83
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Special Features - Improving Defect Detection in Static-Voltage TestingRenovell, Michel et al. | 2002
- 84
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Automatic synthesis of communication controller hardware from protocol specificationsSiegmund, R. / Muller, D. et al. | 2002
- 84
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Departments - Standards| 2002
- 84
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Special DAC Section - Automatic Synthesis of Communication Controller Hardware from Protocol SpecificationsSiegmund, Robert et al. | 2002
- 86
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Departments - Conference Reports| 2002
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Departments - Panel Summaries| 2002
- 90
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Special Features - A Methodology for Synthesis of Data Path CircuitsChowdhary, Amit et al. | 2002
- 90
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A methodology for synthesis of data path circuitsChowdhary, A. / Gupta, R.K. et al. | 2002
- 91
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Departments - New Products| 2002
- 92
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Virtual simulation of distributed IP-based designsDalpasso, M. / Benini, L. / Bogliolo, A. et al. | 2002
- 92
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Special Feature - Virtual Simulation of Distributed IP-Based DesignsDalpasso, Marcello et al. | 2002
- 92
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Departments - TTTC Newsletter| 2002
- 94
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DFT and BIST of a multichip module for high-energy physics experimentsBenso, A. / Chiusano, S. / Prinetto, P. et al. | 2002
- 94
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Special Features - DFT and BIST of a Multichip Module for High-Energy Physics ExperimentsBenso, Alfredo et al. | 2002
- 94
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Departments - DATC Newsletter| 2002
- 96
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Using formal specifications for functional validation of hardware designsShimizu, K. / Dill, D.L. et al. | 2002
- 96
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Special DAC Section - Using Formal Specifications for Functional Validation of Hardware DesignsShimizu, Kanna et al. | 2002
- 96
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Departments - The Last Byte| 2002
- 104
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Design and test education in Latin America| 2002
- 105
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Formal verification: current use and future perspectives| 2002
- 105
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Roundtable| 2002
- 107
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Design of asynchronous circuits using synchronous CAD toolsKondratyev, A. / Lwin, K. et al. | 2002
- 107
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Special DAC Section - Design of Asynchronous Circuits Using Synchronous CAD ToolsKondratyev, Alex et al. | 2002
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Author index| 2002
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Subject index| 2002
- 114
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Standards| 2002
- 114
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Conference Reports| 2002
- 116
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TTTC Newsletter| 2002
- 117
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DATC Newsletter| 2002
- 118
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Communication-based power managementLahiri, K. / Dey, S. / Raghunathan, A. et al. | 2002
- 118
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Special DAC Section - Communication-Based Power ManagementLahiri, Kanishka et al. | 2002
- 120
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Panel Summarles| 2002
- 120
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The Road Ahead| 2002
- 131
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Panel Summaries| 2002