IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
Table of contents
- 1937
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A 0.64 mm$^{2}$ Real-Time Cascade Face Detection Design Based on Reduced Two-Field ExtractionChih-Rung Chen, / Wei-Su Wong, / Ching-Te Chiu, et al. | 2011
- 1937
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A 0.64 mm Formula Not Shown Real-Time Cascade Face Detection Design Based on Reduced Two-Field ExtractionChen, C. R. / Wong, W. S. / Chiu, C. T. et al. | 2011
- 1937
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VLSI Design - A 0.64 mm2 Real-Time Cascade Face Detection Design Based on Reduced Two-Field ExtractionChen, C-R et al. | 2011
- 1949
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A Hybrid Scheme for On-Chip Voltage Regulation in System-On-a-Chip (SOC)Gjanci, J. / Chowdhury, M. H. et al. | 2011
- 1960
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Power-Supply Noise Reduction Using Active Inductors in Mixed-Signal SystemsTaparia, A. / Banerjee, B. / Viswanathan, T. R. et al. | 2011
- 1960
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Noise Reduction - Power-Supply Noise Reduction Using Active Inductors in Mixed-Signal SystemsTaparia, A et al. | 2011
- 1969
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Path Delay Test Generation Toward Activation of Worst Case Coupling EffectsMinjin Zhang, / Huawei Li, / Xiaowei Li, et al. | 2011
- 1969
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Testing/Fault Tolerance - Path Delay Test Generation Toward Activation of Worst Case Coupling EffectsZhang, M et al. | 2011
- 1983
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A Low-Cost Built-In Redundancy-Analysis Scheme for Word-Oriented RAMs With 2-D RedundancyTsu-Wei Tseng, / Jin-Fu Li, et al. | 2011
- 1996
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Full Fault Resilience and Relaxed Synchronization Requirements at the Cache-Memory InterfaceChengmo Yang, / Orailoglu, Alex et al. | 2011
- 2010
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Reconfigurable Architectures - Application-Aware Topology Reconfiguration for On-Chip NetworksModarressi, M et al. | 2011
- 2010
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Application-Aware Topology Reconfiguration for On-Chip NetworksModarressi, M. / Tavakkol, A. / Sarbazi-Azad, H. et al. | 2011
- 2023
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FPGA Based on Integration of CMOS and RRAMTanachutiwat, S. / Ming Liu, / Wei Wang, et al. | 2011
- 2033
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Configurable Multimode Embedded Floating-Point Units for FPGAsYee Jern Chong, / Parameswaran, S. et al. | 2011
- 2045
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Reconfigurable Routers for Low Power and High PerformanceMatos, D. / Concatto, C. / Kreutz, M. et al. | 2011
- 2058
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A 14-GHz AC-Coupled Clock Distribution Scheme With Phase Averaging Technique Using Single LC-VCO and Distributed Phase InterpolatorsNiitsu, K. / Kulkarni, V. V. / Shinmo Kang, et al. | 2011
- 2058
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Clock Distribution - A 14-GHz AC-Coupled Clock Distribution Scheme With Phase Averaging Technique Using Single LC-VCO and Distributed Phase InterpolatorsNiitsu, K et al. | 2011
- 2067
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Dynamically Adaptive I-Cache Partitioning for Energy-Efficient Embedded MultitaskingPaul, M. / Petrov, P. et al. | 2011
- 2067
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Power/Energy Optimization - Dynamically Adaptive I-Cache Partitioning for Energy-Efficient Embedded MultitaskingPaul, M et al. | 2011
- 2081
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Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size ManagementHomayoun, Houman / Sasan, A. / Gaudiot, J. et al. | 2011
- 2095
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Linear and Switch-Mode Conversion in 3-D CircuitsRosenfeld, J. / Friedman, E. G. et al. | 2011
- 2095
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3-D Circuits - Linear and Switch-Mode Conversion in 3-D CircuitsRosenfeld, J et al. | 2011
- 2109
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Vibration Energy Scavenging System With Maximum Power Tracking for Micropower ApplicationsChao Lu, / Chi-Ying Tsui, / Wing-Hung Ki, et al. | 2011
- 2109
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Energy Scavenging - Vibration Energy Scavenging System With Maximum Power Tracking for Micropower ApplicationsLu, C et al. | 2011
- 2120
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TRANSACTIONS BRIEFS - Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric VariationsWang, J et al. | 2011
- 2120
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Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric VariationsJiajing Wang, / Calhoun, B. H. et al. | 2011
- 2125
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Digit-Level Semi-Systolic and Systolic Structures for the Shifted Polynomial Basis Multiplication Over Binary Extension FieldsHariri, A. / Reyhani-Masoleh, A. et al. | 2011
- 2130
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A Bias-Dependent Model for the Impact of Process Variations on the SRAM Soft Error ImmunityMostafa, H. / Anis, M. / Elmasry, M. et al. | 2011
- 2135
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Security Evaluation of Balanced 1-of- $n$ CircuitsBurns, F. / Bystrov, A. / Koelmans, A. et al. | 2011
- 2135
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Security Evaluation of Balanced 1-of- Formula Not Shown CircuitsBurns, F. / Bystrov, A. / Koelmans, A. et al. | 2011
- 2140
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors| 2011
- C1
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Table of contents| 2011
- C2
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information| 2011
- C3
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information| 2011