IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
Table of contents
- 565
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A nonseparable VLSI architecture for two-dimensional discrete periodized wavelet transformKing-Chu Hung, / Yao-Shan Hung, / Yu-Jung Huang, et al. | 2001
- 565
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PAPERS - A Nonseparable VLSI Architecture for Two-Dimensional Discrete Periodized Wavelet TransformHung, K.-C. et al. | 2001
- 577
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Technology mapping for high-performance static CMOS and pass transistor logic designsYanbin Jiang, / Sapatnekar, S.S. / Bamji, C. et al. | 2001
- 577
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PAPERS - Technology Mapping for High-Performance Static CMOS and Pass Transistor Logic DesignsJiang, Y. et al. | 2001
- 590
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A low-power high-performance current-mode multiport SRAMKhellah, M.M. / Elmasry, M.I. et al. | 2001
- 590
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PAPERS - A Low-Power High-Performance Current-Mode Multiport SRAMKhellah, M.M. et al. | 2001
- 599
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Multiclock selection and synthesis for CDFGs using optimal clock sets and genetic algorithmsTorbey, E. / Knight, J.P. et al. | 2001
- 599
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PAPERS - Multiclock Selection and Synthesis for CDFGs Using Optimal Clock Sets and Genetic AlgorithmsTorbey, E. et al. | 2001
- 608
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PAPERS - Power Estimation in Adiabatie Circuits: A Simple and Accurate ModelAlioto, M. et al. | 2001
- 608
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Power estimation in adiabatic circuits: a simple and accurate modelAlioto, M. / Palumbo, G. et al. | 2001
- 616
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On gate level power optimization using dual-supply voltagesChunhong Chen, / Srivastava, A. / Sarrafzadeh, M. et al. | 2001
- 616
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PAPERS - On Gate Level Power Optimization Using Dual-Supply VoltagesChen, C. et al. | 2001
- 630
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PAPERS - Discrete-Time Battery Models for System-Level Low-Power DesignBenini, L. et al. | 2001
- 630
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Discrete-time battery models for system-level low-power designBenini, L. / Castelli, G. / Macii, A. et al. | 2001
- 641
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High-speed architectures for Reed-Solomon decodersSarwate, D.V. / Shanbhag, N.R. et al. | 2001
- 641
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PAPERS - High-Speed Architectures for Reed-Solomon DecodersSarwate, D.V. et al. | 2001
- 656
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PAPERS - Narrow Bus Encoding for Low-Power DSP SystemsShin, Y. et al. | 2001
- 656
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Narrow bus encoding for low-power DSP systemsYoungsoo Shin, / Kiyoung Choi, / Young-Hoon Chang, et al. | 2001
- 661
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PAPERS - Delay Fault Testing of IP-Based Designs via Symbolie Path ModelingKim, H. et al. | 2001
- 661
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Delay fault testing of IP-based designs via symbolic path modelingHyungwon Kim, / Hayes, J.P. et al. | 2001
- 679
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Resynthesis of combinational logic circuits for improved path delay fault testability using comparison unitsPomeranz, I. / Reddy, S.M. et al. | 2001
- 679
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PAPERS - Resynthesis of Combinational Logic Circuits for Improved Path Delay Fault Testability Using Comparison UnitsPomeranz, I. et al. | 2001
- 690
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Modeling of mixed control and dataflow systems in MASCOTBjureus, P. / Jantsch, A. et al. | 2001
- 690
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PAPERS - Modeling of Mixed Control and Dataflow Systems in MASCOTBjuréus, P. et al. | 2001
- 704
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PAPERS - Statistical Skew Modeling for General Clock Distribution Networks in Presence of Process VariationsJiang, X. et al. | 2001
- 704
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Statistical skew modeling for general clock distribution networks in presence of process variationsXiaohong Jiang, / Horiguchi, S. et al. | 2001
- 718
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On effective IDDQ testing of low-voltage CMOS circuits using leakage control techniquesChen, Zhanping / Wei, Liqiong / Roy, K. et al. | 2001
- 718
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On effective I/sub DDQ/ testing of low-voltage CMOS circuits using leakage control techniquesZhanping Chen, / Liqiong Wei, / Roy, K. et al. | 2001
- 718
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PAPERS - On Effective IDDQ Testing of Low-Voltage CMOS Circuits Using Leakage Control TechniquesChen, Z. et al. | 2001
- 726
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TRANSACTIONS BRIEFS - Highly Parallel and Energy-Efficient Exhaustive Minimum Distance Search Engine Using Hybrid Digital-Analog Circuit TechniquesKwon, C.K. et al. | 2001
- 726
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Highly parallel and energy-efficient exhaustive minimum distance search engine using hybrid digital/analog circuit techniquesChang Ki Kwon, / Kwyro Lee, et al. | 2001
- 730
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TRANSACTIONS BRIEFS - An On-Chip March Pattern Generator for Testing Embedded Memory CoresWang, W.-L. et al. | 2001
- 730
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An on-chip march pattern generator for testing embedded memory coresWei-Lun Wang, / Kuen-Jong Lee, / Jhing-Fa Wang, et al. | 2001
- 736
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CALLS FOR PAPERS - SLIP 2002 4th Intemational Workshop on System Level Interconnect Prediciton| 2001
- 737
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CALLS FOR PAPERS - IEEE Custom Integrated Circuits Conferenee 2002| 2001
- 738
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CALLS FOR PAPERS - 2002 IEEE Radio Frequeney Integrated Circuits Symposium RFIC| 2001
- 739
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CALLS FOR PAPERS - On Chip Inductance in High Speed lntegrated Circuits| 2001