IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
Table of contents
- 173
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The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and AnalysisWenping Wang, / Shengqi Yang, / Bhardwaj, S. et al. | 2010
- 173
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Reliability - The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and AnalysisWang, W et al. | 2010
- 184
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Efficient BISR Techniques for Embedded Memories Considering Cluster FaultsShyue-Kung Lu, / Chun-Lin Yang, / Yuang-Cheng Hsiao, et al. | 2010
- 184
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Memories - Efficient BISR Techniques for Embedded Memories Considering Cluster FaultsLu, S-K et al. | 2010
- 194
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Optimal $ \Sigma \Delta$ Modulator Architectures for Fractional-$ {N}$ Frequency SynthesisSleiman, S.B. / Atallah, J.G. / Rodriguez, S. et al. | 2010
- 194
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VLSI Architectures - Optimal ΣΔ Modulator Architectures for Fractional-N Frequency SynthesisSleiman, S Bou et al. | 2010
- 201
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A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth AlgorithmYoung-Ho Seo, / Dong-Wook Kim, et al. | 2010
- 209
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CAPPS: A Framework for Power–Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture SynthesisPasricha, S. / Young-Hwan Park, / Kurdahi, F.J. et al. | 2010
- 209
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Network-on-Chip - CAPPS: A Framework for Power — Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture SynthesisPasricha, S et al. | 2010
- 222
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Circuit Design - A Novel Overlap-Based Logic Cell: An Efficient Implementation of Flip-Flops With Embedded LogicSarbishei, O et al. | 2010
- 222
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A Novel Overlap-Based Logic Cell: An Efficient Implementation of Flip–Flops With Embedded LogicSarbishei, O. / Maymandi-Nejad, M. et al. | 2010
- 232
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Leakage–Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk TechnologyAgostinelli, M. / Alioto, M. / Esseni, D. et al. | 2010
- 246
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An Efficient Wake-Up Strategy Considering Spurious Glitches Phenomenon for Power Gating DesignsDa-Cheng Juan, / Yu-Ting Chen, / Ming-Chao Lee, et al. | 2010
- 246
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Power Management - An Efficient Wake-Up Strategy Considering Spurious Glitches Phenomenon for Power Gating DesignsJuan, D-C et al. | 2010
- 256
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Built-In Sensor for Signal Integrity Faults in Digital Interconnect SignalsChampac, V. / Avendano, V. / Figueras, J. et al. | 2010
- 256
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Fault Tolerant Designs - Built-In Sensor for Signal Integrity Faults in Digital Interconnect SignalsChampac, V et al. | 2010
- 270
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On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing FailuresKunhyuk Kang, / Sang Phill Park, / Keejong Kim, et al. | 2010
- 281
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ABRM: Adaptive β-Ratio Modulation for Process-Tolerant Ultradynamic Voltage ScalingHwang, M-E et al. | 2010
- 281
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ABRM: Adaptive $ \beta$-Ratio Modulation for Process-Tolerant Ultradynamic Voltage ScalingMyeong-Eun Hwang, / Roy, K. et al. | 2010
- 291
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High-Efficiency Soft-Error-Tolerant Digital Signal Processing Using Fine-Grain Subword-Detection ProcessingYuan-Hao Huang, et al. | 2010
- 305
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DSP-Driven Self-Tuning of RF Circuits for Process-Induced Performance VariabilityDonghoon Han, / Byung Sung Kim, / Chatterjee, A. et al. | 2010
- 315
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Preprocessing and Partial Rerouting Techniques for Accelerating Reconfiguration of Degradable VLSI ArraysWu Jigang, / Srikanthan, T. / Xiaogang Han, et al. | 2010
- 315
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TRANSACTIONS BRIEFS - Preprocessing and Partial Rerouting Techniques for Accelerating Reconfiguration of Degradable VLSI ArraysJigang, W et al. | 2010
- 319
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Built-in Self-Detection/Correction Architecture for Motion Estimation Computing ArraysChun-Lung Hsu, / Chang-Hsin Cheng, / Yu Liu, et al. | 2010
- 324
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A Novel x-ploiting Strategy for Improving Performance of Test Data CompressionYi, M et al. | 2010
- 324
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A Novel $ {\rm x}$-ploiting Strategy for Improving Performance of Test Data CompressionMaoxiang Yi, / Huaguo Liang, / Lei Zhang, et al. | 2010
- 329
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Self-Test Techniques for Crypto-DevicesDi Natale, G. / Doulcier, M. / Flottes, M.-L. et al. | 2010
- 333
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Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based TestsPomeranz, I. / Reddy, S.M. et al. | 2010
- 338
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Analysis of the Impacts of Signal Slew and Skew on the Behavior of Coupled RLC Interconnects for Different Switching PatternsRoy, A. / Jingye Xu, / Chowdhury, M.H. et al. | 2010
- 343
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors| 2010
- 344
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IEEE Foundation| 2010
- C1
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Table of contents| 2010
- C2
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information| 2010
- C3
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information| 2010