IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
Table of contents
- 1
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Guest editorial low power electronics and design| 2001
- 3
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Estimation of lower and upper bounds on the power consumption from scheduled data flow graphsKruse, L. / Schmidt, E. / Jochens, G. et al. | 2001
- 15
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Energy-efficient design of battery-powered embedded systemsSimunic, T. / Benini, L. / De Micheli, G. et al. | 2001
- 15
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SPECIAL SECTION PAPERS - Design Tools, Systems and Software - Energy-Efficient Design of Battery-Powered Embedded SystemsSimunic, T. et al. | 2001
- 29
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Nonideal battery and main memory effects on CPU speed-setting for low powerMartin, T.L. / Siewiorek, D.P. et al. | 2001
- 29
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SPECIAL SECTION TRANSACTIONS BRIEFS - Nonideal Battery and Main Memory Effects on CPU Speed-Setting for Low PowerMartin, T.L. et al. | 2001
- 34
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SPECIAL SECTION TRANSACTIONS BRIEFS - Reducing Power Consumption of Turbo-Code Decoder Using Adaptive Iteration with Variable Supply VoltageLeung, O.Y.-H. et al. | 2001
- 34
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Reducing power consumption of turbo-code decoder using adaptive iteration with variable supply voltageLeung, O.Y.-H. / Chi-Ying Tsui, / Cheng, R.S.-K. et al. | 2001
- 42
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SPECIAL SECTION PAPERS - Architecture, Circuits, and Technology - Speed, Power, Area and Latency Tradeoffs in Adaptive FIR Filtering for PRML Read ChannelsMuhammad, K. et al. | 2001
- 42
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Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channelsMuhammad, K. / Staszewski, R.B. / Balsara, P.T. et al. | 2001
- 52
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True single-phase adiabatic circuitrySuhwan Kim, / Papaefthymiou, M.C. et al. | 2001
- 52
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SPECIAL SECTION PAPERS - Architecture, Circuits, and Technology - True Single-Phase Adiabatic CircuitryKim, S. et al. | 2001
- 64
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SPECIAL SECTION PAPERS - Architecture, Circuits, and Technology - Vibration-to-Electric Energy ConversionsMeninger, S. et al. | 2001
- 64
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Vibration-to-electric energy conversionMeninger, S. / Mur-Miranda, J.O. / Amirtharajah, R. et al. | 2001
- 77
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Reducing leakage in a high-performance deep-submicron instruction cachePowell, M. / Se-Hyun Yang, / Falsafi, B. et al. | 2001
- 77
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SPECIAL SECTION PAPERS - Architecture, Circuits, and Technology - Reducing Leakage in a High-Performance Deep-Submicron Instruction CachePowell, M. et al. | 2001
- 90
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Robust subthreshold logic for ultra-low power operationSoeleman, H. / Roy, K. / Paul, B.C. et al. | 2001
- 90
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SPECIAL SECTION PAPERS - Architecture, Circuits, and Technology - Robust Subthreshold Logic for Ultra-Low Power OperationSoeleman, H. et al. | 2001
- 100
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Implementation of a CMOS LNA plus mixer for GPS applications with no external componentsSvelto, F. / Deantoni, S. / Montagna, G. et al. | 2001
- 100
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SPECIAL SECTION TRANSACTIONS BRIEFS - Implementation of a CMOS LNA Plus Mixer for GPS Applications with No External ComponentsSvelto, F. et al. | 2001
- 104
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SPECIAL SECTION TRANSACTIONS BRIEFS - Design Considerations for Databus Charge RecoveryBishop, B. et al. | 2001
- 104
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Design considerations for databus charge recoveryBishop, B. / Lyuboslavsky, V. / Vijaykrishnan, N. et al. | 2001
- 107
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Guest editorial reconfigurable and adaptive VLSI systemsVemuri, R. / Gupta, R.K. et al. | 2001
- 109
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SPECIAL SECTION PAPERS - Solving Satisfiability Problems Using Reconfigurable ComputingSuyama, T. et al. | 2001
- 109
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Solving satisfiability problems using reconfigurable computingSuyama, T. / Yokoo, M. / Sawada, H. et al. | 2001
- 117
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SPECIAL SECTION PAPERS - ATPG for Combinational Circuits on Configurable HardwareKocan, F. et al. | 2001
- 117
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ATPG for combinational circuits on configurable hardwareKocan, F. / Saab, D.G. et al. | 2001
- 130
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An automated process for compiling dataflow graphs into reconfigurable hardwareRinker, R. / Carter, M. / Patel, A. et al. | 2001
- 130
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SPECIAL SECTION PAPERS - An Automated Process for Compiling Dataflow Graphs into Reconfigurable HardwareRinker, R. et al. | 2001
- 140
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SPECIAL SECTION PAPERS - Fine-Grained and Coarse-Grained Behavioral Partitioning With Effective Utilization of Memory and Design Space Exploration for Multi-FPGA ArchitecturesSrinivasan, V. et al. | 2001
- 140
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Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architecturesSrinivasan, V. / Govindarajan, S. / Vemuri, R. et al. | 2001
- 159
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SPECIAL SECTION PAPERS - BIST-Based Test and Diagnosis of FPGA Logic BlocksAbramovici, M. et al. | 2001
- 159
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BIST-based test and diagnosis of FPGA logic blocksAbramovici, M. / Stroud, C.E. et al. | 2001
- 173
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SPECIAL SECTION PAPERS - A Formal Approach to Context Scheduling for Multicontext Reconfigurable ArchitecturesMaestre, R. et al. | 2001
- 173
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A formal approach to context scheduling for multicontext reconfigurable architecturesMaestre, R. / Kurdahl, F. / Fernandez, M. et al. | 2001
- 186
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Design and analysis of a dynamically reconfigurable three-dimensional FPGAChiricescu, S. / Leeser, M. / Vai, M.M. et al. | 2001
- 186
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SPECIAL SECTION PAPERS - Design and Analysis of a Dynamically Reconfigurable Three-Dimensional FPGAChiricescu, S. et al. | 2001
- 197
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A bitstream reconfigurable FPGA implementation of the WSAT algorithmLeong, P.H.W. / Sham, C.W. / Wong, W.C. et al. | 2001
- 197
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SPECIAL SECTION TRANSACTIONS BRIEFS - A Bitstream Reconfigurable FPGA Implementation of the WSAT AlgorithmLeong, P.H.W. et al. | 2001
- 201
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SPECIAL SECTION TRANSACTIONS BRIEFS - Unifying Simulation and Execution in a Design Environment for FPGA SystemsHutchings, B.L. et al. | 2001
- 201
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Unifying simulation and execution in a design environment for FPGA systemsHutchings, B.L. / Nelson, B.E. et al. | 2001
- 205
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Object-oriented domain specific compilers for programming FPGAsMencer, O. / Platzner, M. / Morf, M. et al. | 2001
- 205
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SPECIAL SECTION TRANSACTIONS BRIEFS - Object-Oriented Domain Specific Compilers for Programming FPGAsMencer, O. et al. | 2001
- 210
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SPECIAL SECTION TRANSACTIONS BRIEFS - A Temporal Bipartitioning Algorithm for Dynamically Reconfigurable FPGAsCanto, E. et al. | 2001
- 210
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A temporal bipartitioning algorithm for dynamically reconfigurable FPGAsCanto, E. / Moreno, J.M. / Cabestany, J. et al. | 2001
- 218
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The COBRA-ABS high-level synthesis system for multi-FPGA custom computing machinesDuncan, A.A. / Hendry, D.C. / Gray, P. et al. | 2001
- 218
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SPECIAL SECTION TRANSACTIONS BRIEFS - The COBRA-ABS High-Level Synthesis System for Multi-FPGA Custom Computing MachinesDuncan, A.A. et al. | 2001
- 223
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SPECIAL SECTION TRANSACTIONS BRIEFS - Structural Analysis and Generation of Synthetic Digital Circuits with MemoryWilton, S.J.E. et al. | 2001
- 223
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Structural analysis and generation of synthetic digital circuits with memoryWilton, S.J.E. / Rose, J. / Vranesic, Z. et al. | 2001
- 227
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Reconfigurable VLSI architectures for evolvable hardware: from experimental field programmable transistor arrays to evolution-oriented chipsStoica, A. / Zebulum, R. / Keymeulen, D. et al. | 2001
- 227
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SPECIAL SECTION TRANSACTIONS BRIEFS - Reconfigurable VLSI Architectures for Evolvable Hardware: From Experimental Field Programmable Transistor Arrays to Evolution-Oriented ChipsStoica, A. et al. | 2001
- 233
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CALLS FOR PAPERS - ISSCC2002 IC's for Information Technologies| 2001
- 234
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CALLS FOR PAPERS - IEEE Solid-State CIrcuits Society Predoctoral Fellowship for 2001-1002| 2001
- 235
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CALLS FOR PAPERS - Special Issue on System-Level Interconnect Prediction| 2001
- 236
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CALLS FOR PAPERS - IEEE-NANO 2001: First IEEE Conference on Nanotechnology| 2001
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SPECIAL SECTION PAPERS - Design Tools, Systems and Software - Estimation of Lower and Upper Bounds on the Power Consumption from Scheduled Data Flow GraphsKruse, L. et al. | 2001