IEEE Journal of Solid-State Circuits
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
Table of contents
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Table of contents| 2006
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Introduction to the Special Issue on the 2005 Symposium on VLSI Circuits| 2006
- 749
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Enhancing microprocessor immunity to power supply noise with clock-data compensationWong, K.L. / Rahal-Arabi, T. / Ma, M. et al. | 2006
- 749
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DIGITAL PAPERS - Enhancing Microprocessor Immunity to Power Supply Noise With Clock-Data CompensationWong, K.L. et al. | 2006
- 759
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A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processorHwa-Joon Oh, / Mueller, S.M. / Jacobi, C. et al. | 2006
- 759
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DIGITAL PAPERS - A Fully Pipelined Single-Precision Floating-Point Unit in the Synergistic Processor Element of a CELL ProcessorOh, H.-J. et al. | 2006
- 772
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Pulsed current-mode signaling for nearly speed-of-light intrachip communicationJose, A.P. / Patounakis, G. / Shepard, K.L. et al. | 2006
- 772
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DIGITAL PAPERS - Pulsed Current-Mode Signaling for Nearly Speed-of-Light Intrachip CommunicationJose, A.P. et al. | 2006
- 781
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DIGITAL PAPERS - AES-Based Security Coprocessor IC in 0.18-mm CMOS With Resistance to Differential Power Analysis Side-Channel AttacksHwang, D.D. et al. | 2006
- 781
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AES-Based Security Coprocessor IC in 0.18-$muhbox m$CMOS With Resistance to Differential Power Analysis Side-Channel AttacksHwang, D.D. / Tiri, K. / Hodjat, A. et al. | 2006
- 792
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DIGITAL PAPERS - A Self-Tuning DVS Processor Using Delay-Error Detection and CorrectionDas, S. et al. | 2006
- 792
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A self-tuning DVS processor using delay-error detection and correctionDas, S. / Roberts, D. / Seokwoo Lee, et al. | 2006
- 805
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Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modesNomura, M. / Ikenaga, Y. / Takeda, K. et al. | 2006
- 805
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DIGITAL PAPERS - Delay and Power Monitoring Schemes for Minimizing Power Consumption by Means of Supply and Threshold Voltage Control in Active and Standby ModesNomura, M. et al. | 2006
- 815
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A low leakage SRAM macro with replica cell biasing schemeTakeyama, Y. / Otake, H. / Hirabayashi, O. et al. | 2006
- 815
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MEMORY PAPERS - A Low Leakage SRAM Macro With Replica Cell Biasing SchemeTakeyama, Y. et al. | 2006
- 823
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An autonomous SRAM with on-chip sensors in an 80-nm double stacked cell technologySohn, K. / Hyun-Sun Mo, / Young-Ho Suh, et al. | 2006
- 823
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MEMORY PAPERS - An Autonomous SRAM With On-Chip Sensors in an 80-nm Double Stacked Cell TechnologySohn, K. et al. | 2006
- 831
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A 512-mb DDR3 SDRAM prototype with C/sub IO/ minimization and self-calibration techniquesChuroo Park, / HoeJu Chung, / Yun-Sang Lee, et al. | 2006
- 831
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MEMORY PAPERS - A 512-Mb DDR3 SDRAM Prototype With CIO Minimization and Self-Calibration TechniquesPark, C. et al. | 2006
- 831
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A 512-Mb DDR3 SDRAM Prototype With Minimization and Self-Calibration TechniquesPark, C. / Chung, H. / Lee, Y.-S. et al. | 2006
- 839
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ANALOG PAPERS - A Direct Digital Frequency Synthesizer With Fourth-Order Phase Domain DS Noise Shaper and 12-bit Current-Steering DACDai, F.F. et al. | 2006
- 839
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A Direct Digital Frequency Synthesizer With Fourth-Order Phase Domain Delta Sigma Noise Shaper and 12-bit Current-Steering DACDai, F. F. / Ni, W. / Yin, S. et al. | 2006
- 839
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A direct digital frequency synthesizer with fourth-order phase domain /spl Delta//spl Sigma/ noise shaper and 12-bit current-steering DACFa Foster Dai, / Weining Ni, / Shi Yin, et al. | 2006
- 851
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A sensitivity and linearity improvement of a 100-dB dynamic range CMOS image sensor using a lateral overflow integration capacitorAkahane, N. / Sugawa, S. / Adachi, S. et al. | 2006
- 851
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ANALOG PAPERS - A Sensitivity and Linearity Improvement of a 100-dB Dynamic Range CMOS Image Sensor Using a Lateral Overflow Integration CapacitorAkahane, N. et al. | 2006
- 859
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ANALOG PAPERS - Managing Subthreshold Leakage in Charge-Based Analog Circuits With Low-VTH Transistors by Analog T-Switch (AT-Switch) and Super Cut-off CMOS (SCCMOS)Ishida, K. et al. | 2006
- 859
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Managing Subthreshold Leakage in Charge-Based Analog Circuits With Low-V_rm Transistors by Analog T- Switch (AT-Switch) and Super Cut-off CMOS (SCCMOS)Ishida, K. / Kanda, K. / Tamtrakarn, A. et al. | 2006
- 859
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Managing subthreshold leakage in charge-based analog circuits with low-V/sub TH/ transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS)Ishida, K. / Kanda, K. / Tamtrakarn, A. et al. | 2006
- 868
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A CMOS oversampled DAC with multi-bit semi-digital filtering and boosted subcarrier SNR for ADSL central office modemsLin, A.C.Y. / Su, D.K. / Hester, R.K. et al. | 2006
- 868
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ANALOG PAPERS - A CMOS Oversampled DAC With Multi-Bit Semi-Digital Filtering and Boosted Subcarrier SNR for ADSL Central Office ModemsLin, A.C.Y. et al. | 2006
- 876
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An energy-efficient analog front-end circuit for a sub-1-V digital hearing aid chipSunyoung Kim, / Jae-Youl Lee, / Seong-Jun Song, et al. | 2006
- 876
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ANALOG PAPERS - An Energy-Efficient Analog Front-End Circuit for a Sub-1-V Digital Hearing Aid ChipKim, S. et al. | 2006
- 883
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A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/sIizuka, K. / Matsui, H. / Ueda, M. et al. | 2006
- 883
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ANALOG PAPERS - A 14-bit Digitally Self-Calibrated Pipelined ADC With Adaptive Bias Optimization for Arbitrary Speeds Up to 40 MS-sIizuka, K. et al. | 2006
- 891
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A CMOS Ultra-Wideband Impulse Radio Transceiver for 1-Mb/s Data Communications and$pm$2.5-cm Range FindingTerada, T. / Yoshizumi, S. / Muqsith, M. et al. | 2006
- 891
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COMMUNICATION PAPERS - A CMOS Ultra-Wideband Impulse Radio Transceiver for 1-Mb-s Data Communications and (plus-minus)2.5-cm Range FindingTerada, T. et al. | 2006
- 891
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A CMOS ultra-wideband impulse radio transceiver for 1-mb/s data communications and /spl plusmn/2.5-cm range findingTerada, T. / Yoshizumi, S. / Muqsith, M. et al. | 2006
- 899
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COMMUNICATION PAPERS - A 20-GHz Phase-Locked Loop for 40-Gb-s Serializing Transmitter in 0.13-mm CMOSKim, J. et al. | 2006
- 899
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A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13- mu m CMOSKim, Jaeha / Kim, Jeong-Kyoum / Lee, Bong-Joon et al. | 2006
- 899
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A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-/spl mu/m CMOSJaeha Kim, / Jeong-Kyoum Kim, / Bong-Joon Lee, et al. | 2006
- 899
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A 20-GHz Phase-Locked Loop for 40-Gb/s Serializing Transmitter in 0.13-mu CMOSKim, J. / Kim, J.-K. / Lee, B.-J. et al. | 2006
- 909
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COMMUNICATION PAPERS - A CMOS Finite Impulse Response Filter With a Crossover Traveling Wave Topology for Equalization up to 30 Gb-sSewter, J. et al. | 2006
- 909
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A CMOS finite impulse response filter with a crossover traveling wave topology for equalization up to 30 Gb/sSewter, J. / Carusone, A.C. et al. | 2006
- 918
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A Multi-Rate 9.95312.5-GHz 0.2-mu SiGe BiCMOS LC Oscillator Using a Resistor-Tuned Varactor and a Supply Pushing Cancellation CircuitMaxim, A. et al. | 2006
- 918
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COMMUNICATION PAPERS - A Multi-Rate 9.953-12.5-GHz 0.2-mm SiGe BiCMOS LC Oscillator Using a Resistor-Tuned Varactor and a Supply Pushing Cancellation CircuitMaxim, A. et al. | 2006
- 935
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A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converterVarzaghani, A. / Chih-Kong Ken Yang, et al. | 2006
- 935
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COMMUNICATION PAPERS - A 6-GSamples-s Multi-Level Decision Feedback Equalizer Embedded in a 4-Bit Time-Interleaved Pipeline A-D ConverterVarzaghani, A. et al. | 2006
- 945
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A 13-dB IIP3 improved low-power CMOS RF programmable gain amplifier using differential circuit transconductance linearization for various terrestrial mobile D-TV applicationsTae Wook Kim, / Bonkee Kim, et al. | 2006
- 945
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COMMUNICATION PAPERS - A 13-dB IIP3 Improved Low-Power CMOS RF Programmable Gain Amplifier Using Differential Circuit Transconductance Linearization for Various Terrestrial Mobile D-TV ApplicationsKim, T.W. et al. | 2006
- 954
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COMMUNICATION PAPERS - A 22-Gb-s PAM-4 Receiver in 90-nm CMOS SOI TechnologyToifl, T. et al. | 2006
- 954
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A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technologyToifl, T. / Menolfi, C. / Ruegg, M. et al. | 2006
- 966
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COMMUNICATION PAPERS - A 1-MRZ Bandwidth 3.6-GHz 0.18-mm CMOS Fractional-N Synthesizer Utilizing a Hybrid PFD-DAC Structure for Reduced Broadband Phase NoiseMeninger, S.E. et al. | 2006
- 966
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A 1-MHZ bandwidth 3.6-GHz 0.18-/spl mu/m CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noiseMeninger, S.E. / Perrott, M.H. et al. | 2006
- 966
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A 1-MHZ Bandwidth 3.6-GHz 0.18-mu CMOS Fractional-N Synthesizer Utilizing a Hybrid PFD/DAC Structure for Reduced Broadband Phase NoiseMeninger, S. E. / Perrott, M. H. et al. | 2006
- 981
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COMMUNICATION PAPERS - A 0.13 mm CMOS Front-End, for DCS1800-UMTS-802.11b-g With Multiband Positive Feedback Low-Noise AmplifierLiscidini, A. et al. | 2006
- 981
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A 0.13mu CMOS Front-End, for DCS1800/UMTS/802.11b-g With Multiband Positive Feedback Low-Noise AmplifierLiscidini, A. / Brandolini, M. / Sanzogni, D. et al. | 2006
- 981
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A 0.13 /spl mu/m CMOS front-end, for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifierLiscidini, A. / Brandolini, M. / Sanzogni, D. et al. | 2006
- 990
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Pulse-width modulation pre-emphasis applied in a wireline transmitter, achieving 33 dB loss compensation at 5-Gb/s in 0.13-/spl mu/m CMOSSchrader, J.-R. / Klumperink, E.A.M. / Visschers, J.L. et al. | 2006
- 990
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Pulse-width modulation pre-emphasis applied in a wireline transmitter, achieving 33 dB loss compensation at 5-Gb/s in 0.13- mu m CMOSSchrader, J.R. / Klumperink, E.A.M. / Visschers, J.L. et al. | 2006
- 990
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Pulse-Width Modulation Pre-Emphasis Applied in a Wireline Transmitter, Achieving 33 dB Loss Compensation at 5-Gb/s in 0.13-mu CMOSSchrader, J.-R. / Klumperink, E. A. M. / Visschers, J. L. et al. | 2006
- 990
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COMMUNICATION PAPERS - Pulse-Width Modulation Pre-Emphasis Applied in a Wireline Transmitter, Achieving 33 dB Loss Compensation at 5-Gb-s in 0.13-mm CMOSSchrader, J.-R. et al. | 2006
- 1000
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IEEE Asian Solid-State Circuits Conference (A-SSCC) 2006| 2006
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AES-Based Security Coprocessor IC in 0.18-mu CMOS With Resistance to Differential Power Analysis Side-Channel AttacksHwang, D. D. / Tiri, K. / Hodjat, A. et al. | 2006
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[Front cover]| 2006
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IEEE Journal of Solid-State Circuits publication information| 2006
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IEEE Journal of Solid-State Circuits information for authors| 2006