IEEE transactions on electron devices
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
Table of contents
- 2515
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Editorial Kudos to Our ReviewersVerret, et al. | 2005
- 2516
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The Golden List| 2005
- 2533
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Changes to the Editorial BoardVerret, et al. | 2005
- 2533
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Changes in the Editorial Board| 2005
- 2534
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Field-plate engineering for HFETsKarmalkar, S. / Shur, M.S. / Simin, G. et al. | 2005
- 2534
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Compound Semiconductor Devices - Field-Plate Engineering for HFETsKarmalkar, S. et al. | 2005
- 2541
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Analysis of transit times and minority carrier mobility in n-p-n 4H-SiC bipolar junction transistorsFeng Zhao, / Perez, I. / Chih-Fang Huang, et al. | 2005
- 2541
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Compound Semiconductor Devices - Analysis of Transit Times and Minority Carrier Mobility in NPN 4H-SiC Bipolar Junction TransistorsZhao, F. et al. | 2005
- 2546
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Compound Semiconductor Devices - Effect of Basal Plane Dislocations on Characteristics of Diffused 4H-SiC p-i-n DiodesGrekov, A. et al. | 2005
- 2546
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Effect of basal plane dislocations on characteristics of diffused 4H-SiC p-i-n diodesGrekov, A. / Maximenko, S. / Sudarshan, T.S. et al. | 2005
- 2552
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A 3-D model for concentrator solar cells based on distributed circuit unitsGaliana, B. / Algora, C. / Rey-Stolle, I. et al. | 2005
- 2552
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Compound Semiconductor Devices - A 3-D Model for Concentrator Solar Cells Based on Distributed Circuit UnitsGaliana, B. et al. | 2005
- 2559
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Physical layout design optimization of integrated spiral inductors for silicon-based RFIC applicationsChoon Beng Sia, / Beng Hwee Ong, / Kwok Wai Chan, et al. | 2005
- 2559
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Materials Processing and Packaging - Physical Layout Design Optimization of Integrated Spiral Inductors for Silicon-Based RFIC ApplicationsSia, C.B. et al. | 2005
- 2568
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Nanoelectronics - Comparing Carbon Nanotube Transistors -- The Ideal Choice: A Novel Tunneling Device DesignAppenzeller, J. et al. | 2005
- 2568
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Comparing carbon nanotube transistors - the ideal choice: a novel tunneling device designAppenzeller, J. / Yu-Ming Lin, / Knoch, J. et al. | 2005
- 2577
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Accelerated stress testing of a-Si:H pixel circuits for AMOLED displaysSakariya, K. / Ng, C.K.M. / Servati, P. et al. | 2005
- 2577
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Optoelectronics, Displays, and Imaging - Accelerated Stress Testing of a-Si:H Pixel Circuits for AMOLED DisplaysSakariya, K. et al. | 2005
- 2584
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Optimization of electron beam focusing for gated carbon nanotube field emitter arraysJun Hee Choi, / Zoulkarneev, A.R. / Young-Jun Park, et al. | 2005
- 2584
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Optoelectronics, Displays, and Imaging - Optimization of Electron Beam Focusing for Gated Carbon Nanotube Field Emitter ArraysChoi, J.H. et al. | 2005
- 2591
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A digital pixel sensor array with programmable dynamic rangeKitchen, A. / Bermak, A. / Bouzerdoum, A. et al. | 2005
- 2591
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Optoelectronics, Displays, and Imaging - A Digital Pixel Sensor Array With Programmable Dynamic RangeKitchen, A. et al. | 2005
- 2602
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Electromigration lifetime improvement of copper interconnect by cap/dielectric interface treatment and geometrical designLin, M.H. / Lin, Y.L. / Chen, J.M. et al. | 2005
- 2602
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Reliability - Electromigration Lifetime Improvement of Copper Interconnect by Cap-Dielectric Interface Treatment and Geometrical DesignLin, M.H. et al. | 2005
- 2609
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NBTI degradation and its impact for analog circuit reliabilityJha, N.K. / Reddy, P.S. / Sharma, D.K. et al. | 2005
- 2609
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Reliability - NBTI Degradation and Its Impact for Analog Circuit ReliabilityJha, N.K. et al. | 2005
- 2616
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Silicon Devices - 0.18-mm Nondestructive Readout FeRAM Using Charge Compensation TechniqueKato, Y. et al. | 2005
- 2616
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0.18-mum Nondestructive Readout FeRAM Using Charge Compensation TechniqueKato, Y. / Yamada, T. / Shimada, Y. et al. | 2005
- 2616
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0.18-/spl mu/m nondestructive readout FeRAM using charge compensation techniqueKato, Y. / Yamada, T. / Shimada, Y. et al. | 2005
- 2622
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Dependence of single-crystalline Si TFT characteristics on the channel position inside a location-controlled grainRana, V. / Ishihara, R. / Hiroshima, Y. et al. | 2005
- 2622
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Silicon Devices - Dependence of Single-Crystalline Si TFF Characteristics on the Channel Position Inside a Location-Controlled GrainRana, V. et al. | 2005
- 2629
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Silicon Devices - A New Polysilicon CMOS Self-Aligned Double-Gate TFT TechnologyXiong, Z. et al. | 2005
- 2629
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A new polysilicon CMOS self-aligned double-gate TFT technologyZhibin Xiong, / Haitao Liu, / Chunxiang Zhu, et al. | 2005
- 2634
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Process and design tradeoffs between minimum RC signal propagation delay and interconnect current density and resistance for deep submicrometer ICsInohara, M. / Toyoshima, Y. et al. | 2005
- 2634
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Silicon Devices - Process and Design Tradeoffs Between Minimum RC Signal Propagation Delay and Interconnect Current Density and Resistance for Deep Submicrometer ICsInohara, M. et al. | 2005
- 2640
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A new and improved physics-based model for MOS transistorsHauser, J.R. et al. | 2005
- 2640
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Silicon Devices - A New and Improved Physics-Based Model for MOS TransistorsHauser, J.R. et al. | 2005
- 2648
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Silicon Devices - An Asymmetric Two-Side Program With One-Side Read (ATPOR) Device for MultiBit Per Cell MLC Nitride-Trapping Flash MemoriesWu, J.-Y. et al. | 2005
- 2648
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An asymmetric two-side program with one-side read (ATPOR) device for MultiBit per cell MLC nitride-trapping flash memoriesJau-Yi Wu, / Ming-Hsiu Lee, / Tzu-Hsuan Hsu, et al. | 2005
- 2654
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Silicon Devices - High Work-Function Metal Gate and High-k Dielectrics for Charge Trap Flash Memory Device ApplicationsJeon, S. et al. | 2005
- 2654
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High work-function metal gate and high-/spl kappa/ dielectrics for charge trap flash memory device applicationsSanghun Jeon, / Jeong Hee Han, / Jung Hoon Lee, et al. | 2005
- 2654
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High Work-Function Metal Gate and High-kappa Dielectrics for Charge Trap Flash Memory Device ApplicationsJeon, S. / Han, J. H. / Lee, J. H. et al. | 2005
- 2660
-
Silicon Devices - Optimal Doping Profiles via Geometric ProgrammingJoshi, S. et al. | 2005
- 2660
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Optimal doping profiles via geometric programmingJoshi, S. / Boyd, S. / Dutton, R.W. et al. | 2005
- 2676
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Silicon Devices - Self-Convergent Scheme for Logic-Process-Based Multilevel-Analog MemoryLee, K.-H. et al. | 2005
- 2676
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Self-convergent scheme for logic-process-based multilevel/analog memoryKung-Hong Lee, / Shih-Chen Wang, / Ya-Chin King, et al. | 2005
- 2682
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Silicon Devices - Design and Integration of Novel SCR-Based Devices for ESD Protection in CMOS-BiCMOS TechnologiesSalcedo, J.A. et al. | 2005
- 2682
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Design and integration of novel SCR-based devices for ESD protection in CMOS/BiCMOS technologiesSalcedo, J.A. / Liou, J.J. / Bernier, J.C. et al. | 2005
- 2690
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Silicon Devices - High-Speed Source-Heterojunction-MOS-Transistor (SHOT) Utilizing High-Velocity Electron InjectionMizuno, T. et al. | 2005
- 2690
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High-speed source-heterojunction-MOS-transistor (SHOT) utilizing high-velocity electron injectionMizuno, T. / Sugiyama, N. / Tezuka, T. et al. | 2005
- 2697
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Nonvolatile memory with a metal nanocrystal/nitride heterogeneous floating-gateChungho Lee, / Tuo-Hung Hou, / Kan, E.C.-C. et al. | 2005
- 2697
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Silicon Devices - Nonvolatile Memory With a Metal Nanocrystal-Nitride Heterogeneous Floating-GateLee, C. et al. | 2005
- 2703
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The Impact of TiN Capping Layer on NiSi, CoSi~2 and Co~xNi~1~-~xSi~2 FUSI Metal Gate Work Function AdjustmentLiu, J. / Wen, H.-C. / Lu, J.-P. et al. | 2005
- 2703
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Silicon Devices - The Impact of TiN Capping Layer on NiSi, CoSi2 and CoxNi1-xSi2 FUSI Metal Gate Work Function AdjustmentLiu, J. et al. | 2005
- 2703
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The impact of TiN capping Layer on NiSi, CoSi/sub 2/, and Co/sub x/Ni/sub 1-x/Si/sub 2/ FUSI metal gate work function adjustmentJun Liu, / Huang-Chun Wen, / Jiong-Ping Lu, et al. | 2005
- 2710
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Silicon Devices - Scaling Analysis of Multilevel Interconnect Temperatures for High-Performance ICsIm, S. et al. | 2005
- 2710
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Scaling analysis of multilevel interconnect temperatures for high-performance ICsSungjun Im, / Srivastava, N. / Banerjee, K. et al. | 2005
- 2720
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Silicon Devices - Integration of PtSi-Based Schottky-Barrier p-MOSFETs With a Midgap Tungsten GateLarrieu, G. et al. | 2005
- 2720
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Integration of PtSi-based Schottky-barrier p-MOSFETs with a midgap tungsten gateLarrieu, G. / Dubois, E. et al. | 2005
- 2727
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Silicon Devices - Understanding Quasi-Ballistic Transport in Nano-MOSFETs: Part I -- Scattering in the Channel and in the DrainPalestri, P. et al. | 2005
- 2727
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Understanding quasi-ballistic transport in nano-MOSFETs: part I-scattering in the channel and in the drainPalestri, P. / Esseni, D. / Eminente, S. et al. | 2005
- 2736
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Silicon Devices - Understanding Quasi-Ballistic Transport in Nano-MOSFETs: Part II -- Technology Scaling Along the ITRSEminente, S. et al. | 2005
- 2736
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Understanding quasi-ballistic transport in nano-MOSFETs: part II-Technology scaling along the ITRSEminente, S. / Esseni, D. / Palestri, P. et al. | 2005
- 2744
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Structure optimization of trench-isolated SiGe HBTs for simultaneous improvements in thermal and electrical performancesJae-Sung Rieh, / Greenberg, D. / Qizhi Liu, et al. | 2005
- 2744
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Solid-State Device Phenomena - Structure Optimization of Trench-Isolated SiGe HBTs for Simultaneous Improvements in Thermal and Electrical PerformancesRieh, J.-S. et al. | 2005
- 2753
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Effects of layout methods of RFCMOS on noise performanceWen Wu, / Sang Lam, / Chan, M. et al. | 2005
- 2753
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Solid-State Device Phenomena - Effects of Layout Methods of RF CMOS on Noise PerformanceWu, W. et al. | 2005
- 2760
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Analyses of the picosecond range transient in a high-power switch based on a bipolar GaAs transistor structureVainshtein, S.N. / Yuferev, V.S. / Kostamovaara, J.T. et al. | 2005
- 2760
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Solid-State Power and High-Voltage - Analyses of the Picosecond Range Transient in a High-Power Switch Based on a Bipolar GaAs Transistor StructureVainshtein, S.N. et al. | 2005
- 2769
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A new dynamic gate capacitance measurement protocol to evaluate integrated high-voltage devices' switching loss performances in power management applicationsGrelu, C. / Baboux, N. / Bianchi, R.A. et al. | 2005
- 2769
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Solid-State Power and High-Voltage - A New Dynamic Gate Capacitance Measurement Protocol to Evaluate Integrated High-Voltage Devices' Switching Loss Performances in Power Management ApplicationsGrelu, C. et al. | 2005
- 2776
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Modeling Voltage derivative during inductive turnoff in thin SOI LIGBTNapoli, E. / Pathirana, V. / Udrea, F. et al. | 2005
- 2776
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Solid-State Power and High-Voltage - Modeling Voltage Derivative During Inductive Turnoff in Thin SOI LIGBTNapoli, E. et al. | 2005
- 2784
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Solid-State Sensors and Actuators - Temperature Sensitivity of SOI-CMOS Transistors for Use in Uncooled Thermal SensingSocher, E. et al. | 2005
- 2784
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Temperature sensitivity of SOI-CMOS transistors for use in uncooled thermal sensingSocher, E. / Beer, S.M. / Nemirovsky, Y. et al. | 2005
- 2791
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Modifications to harmonic current bunching of electron beams from RF cavities due to radial boundary conditionsCarlsten, B.E. / Roybal, W.T. / Tallerico, P.J. et al. | 2005
- 2791
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Vacuum Electron Devices - Modifications to Harmonic Current Bunching of Electron Beams From RF Cavities Due to Radial Boundary ConditionsCarlsten, B.E. et al. | 2005
- 2800
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Controlled porosity cathodes from sintered tungsten wiresIves, R.L. / Falce, L.R. / Schwartzkopf, S. et al. | 2005
- 2800
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Vacuum Electron Devices - Controlled Porosity Cathodes From Sintered Tungsten WiresIves, R.L. et al. | 2005
- 2806
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BRIEFS - Design of a-Si TFT Demultiplexers for Driving Gate Lines in Active Matrix ArraysMoez, K.K. et al. | 2005
- 2806
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Design of a-Si TFT demultiplexers for driving gate lines in active matrix arraysMoez, K.K. et al. | 2005
- 2809
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BRIEFS - 130-nm Partially Depleted SOI MOSFET Nonlinear Model Including the Kink Effect for Linearity Properties InvestigationSiligaris, A. et al. | 2005
- 2809
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130-nm partially depleted SOI MOSFET nonlinear model including the kink effect for linearity properties investigationSiligaris, A. / Dambrine, G. / Schreurs, D. et al. | 2005
- 2812
-
Threshold voltage reduction in strained-Si/SiGe MOS devices due to a difference in the dielectric constants of Si and GeZainuddin, A.N.M. / Haque, A. et al. | 2005
- 2812
-
BRIEFS - Threshold Voltage Reduction in Strained-Si-SiGe MOS Devices Due to a Difference in the Dielectric Constants of Si and GeZainuddin, A.N.M. et al. | 2005
- 2814
-
The influence of source and drain junction depth on the short-channel effect in MOSFETsSleva, S. / Taur, Y. et al. | 2005
- 2814
-
BRIEFS - The Influence of Source and Drain Junction Depth on the Short-Channel Effect in MOSFETsSleva, S. et al. | 2005
- 2817
-
BRIEFS - Nanoscale Post-Breakdown Conduction of HfO2-SiO2 MOS Gate Stacks Studied by Enhanced-CAFMBlasco, X. et al. | 2005
- 2817
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Nanoscale Post-Breakdown Conduction of HfO~2/SiO~2 MOS Gate Stacks Studied by Enhanced-CAFMBlasco, X. / Nafria, M. / Aymerich, X. et al. | 2005
- 2817
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Nanoscale post-breakdown conduction of HfO/sub 2//SiO/sub 2/ MOS gate stacks studied by enhanced-CAFMBlasco, X. / Nafria, M. / Aymerich, X. et al. | 2005
- 2819
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Low-voltage organic transistors and depletion-load inverters with high-K pyrochlore BZN gate dielectric on polymer substrateYongWoo Choi, / Il-Doo Kim, / Tuller, H.L. et al. | 2005
- 2819
-
BRIEFS - Low-Voltage Organic Transistors and Depletion-Load Inverters With High-K Pyrochlore BZN Gate Dielectric on Polymer SubstrateChoi, Y. et al. | 2005
- 2824
-
BRIEFS - Dependence of a Wall Voltage Variation on Priming Effects During a Reset Discharge in AC Plasma Display PanelsShin, B.J. et al. | 2005
- 2824
-
Dependence of a wall voltage variation on priming effects during a reset discharge in AC plasma display panelsBhum Jae Shin, / Kyung Cheol Choi, / Young Su Roh, et al. | 2005
- 2827
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2005 Index| 2005
- 2880
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Call for papers on advanced compact models and 45-nm modeling challenges| 2005
- 2880
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ANNOUNCEMENTS - Call for Papers for a Special Issue of the IEEE TRANSACTIONS ON ELECTRON DEVICES on Advanced Compact Models and 45-nm Modeling Challenges| 2005
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Table of contents| 2005
- c2
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IEEE Transactions on Electron Devices publication information| 2005
- c3
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IEEE Transactions on Electron Devices information for authors| 2005