IEEE Journal of Solid-State Circuits
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
Table of contents
- 1599
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Introduction To The Digital SectionGerosa, G. et al. | 1998
- 1599
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - DIGITAL PAPERS - Introduction to the Digital SectionGerosa, G. et al. | 1998
- 1600
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A 1.0-GHz Single-Issue 64-Bit PowerPC Integer ProcessorSilberman, J. / Aoki, N. / Boerstler, D. et al. | 1998
- 1600
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - DIGITAL PAPERS - A 1.0-GHz Single-Issue 64-Bit PowerPC Integer ProcessorSilberman, J. et al. | 1998
- 1609
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - DIGITAL PAPERS - A 480-MHz RISC Microprocessor in a 0.12-mm Leff CMOS Technology with Copper InterconnectsAkrout, C. et al. | 1998
- 1609
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A 480-MHz RISC microprocessor in a 0.12- mu m Leff CMOS technology with copper interconnectsAkrout, C. / Bialas, J. / Canada, M. et al. | 1998
- 1609
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A 480-MHz RISC Microprocessor in a 0.12-m L~e~f~f CMOS Technology with Copper InterconnectsAkrout, C. / Bialas, J. / Canada, M. et al. | 1998
- 1617
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - DIGITAL PAPERS - A 2.6-GByte-s Multipurpose Chip-to-Chip InterfaceLau, B. et al. | 1998
- 1617
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A 2.6-GByte/s Multipurpose Chip-to-Chip InterfaceLau, B. / Chan, Y.-F. / Moncayo, A. et al. | 1998
- 1627
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Clocking Design and Analysis for a 600-MHz Alpha MicroprocessorBailey, D. W. / Benschneider, B. J. et al. | 1998
- 1627
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - DIGITAL PAPERS - Clocking Design and Analysis for a 600-MHz Alpha MicroprocessorBailey, D.W. et al. | 1998
- 1634
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - DIGITAL PAPERS - A High-Speed, Low-Power Clock Generator for a Microprocessor ApplicationKaenel, V.R.von et al. | 1998
- 1634
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A High-Speed, Low-Power Clock Generator for a Microprocessor ApplicationVon Kaenel, V. R. et al. | 1998
- 1640
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - DIGITAL PAPERS - A 1.2-W, 2.16-GOPS-720-MFLOPS Embedded Superscalar Microprocessor for Multimedia ApplicationsKubosawa, H. et al. | 1998
- 1640
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A 1.2-W, 2.16-GOPS/720-MFLOPS Embedded Superscalar Microprocessor for Multimedia ApplicationsKubosawa, H. / Takahashi, H. / Ando, S. et al. | 1998
- 1649
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY PAPERS - Introduction to the Memory SectionDreibelbis, J. et al. | 1998
- 1649
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Introduction to the memory sectionDreibelbis, J. et al. | 1998
- 1650
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A 1.8-ns Access, 550-MHz, 4.5-Mb CMOS SRAMNambu, H. / Kanetani, K. / Yamasaki, K. et al. | 1998
- 1650
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY PAPERS - A 1.8-ns Access, 550-MHz, 4.5-Mb CMOS SRAMNambu, H. et al. | 1998
- 1659
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY PAPERS - Low-Power SRAM Design Using Half-Swing Pulse-Mode TechniquesMai, K.W. et al. | 1998
- 1659
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Low-Power SRAM Design Using Half-Swing Pulse-Mode TechniquesMai, K. W. / Mori, T. / Amrutur, B. S. et al. | 1998
- 1672
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY PAPERS - A 5-MHz, 3.6-mW, 1.4-V SRAM with Nonboosted, Vertical Bipolar Bit-Line Contact Memory CellSato, H. et al. | 1998
- 1672
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A 5-MHz, 3.6-mW, 1.4-V SRAM with Nonboosted, Vertical Bipolar Bit-Line Contact Memory CellSato, H. / Nagaoka, H. / Honda, H. et al. | 1998
- 1682
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64-KByte Sum-Addressed-Memory Cache with 1.6-ns Cycle and 2.6-ns LatencyHeald, R. / Shin, K. / Reddy, V. et al. | 1998
- 1682
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY PAPERS - 64-KByte Sum-Addressed-Memory Cache with 1.6-ns Cycle and 2.6-ns LatencyHeald, R. et al. | 1998
- 1690
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Fully Parallel 30-MHz, 2.5-Mb CAMShafai, F. / Schultz, K. J. / Gibson, G. F. R. et al. | 1998
- 1690
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY PAPERS - Fully Parallel 30-MHz, 2.5-Mb CAMShafai, F. et al. | 1998
- 1697
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY PAPERS - A 1-Gb SDRAM with Ground-Level Precharged Bit Line and Nonboosted 2.1-V Word LineEto, S. et al. | 1998
- 1697
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A 1-Gb SDRAM with Ground-Level Precharged Bit Line and Nonboosted 2.1-V Word LineEto, S. / Matsumiya, M. / Takita, M. et al. | 1998
- 1703
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A 64-Mbit, 640-MByte/s Bidirectional Data Strobed, Double-Data-Rate SDRAM with a 40-mW DLL for a 256-MByte Memory SystemKim, C. H. / Lee, J. H. / Lee, J. B. et al. | 1998
- 1703
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY PAPERS - A 64-Mbit, 640-MByte-s Bidirectional Data Strobed, Double-Data-Rate SDRAM with a 40-mW DLL for a 256-MByte Memory SystemKim, C.H. et al. | 1998
- 1711
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY PAPERS - A 220-mm2, Four- and Eight-Bank, 256-Mb SDRAM with Single-Sided Stitched WL ArchitectureKirihata, T. et al. | 1998
- 1711
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A 220-mm^2, Four- and Eight-Bank, 256-Mb SDRAM with Single-Sided Stitched WL ArchitectureKirihata, T. / Gall, M. / Hosokawa, K. et al. | 1998
- 1720
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500-Mb/s Nonprecharged Data Bus for High-Speed DRAM'sSaito, M. / Ogawa, J. / Tamura, H. et al. | 1998
- 1720
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY PAPERS - 500-Mb-s Nonprecharged Data Bus for High-Speed DRAM'sSaito, M. et al. | 1998
- 1731
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Processor-Based Built-In Self-Test for Embedded DRAMDreibelbis, J. / Barth, J. / Kalter, H. et al. | 1998
- 1731
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY PAPERS - Processor-Based Built-In Self-Test for Embedded DRAMDreibelbis, J. et al. | 1998
- 1741
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A Process-Independent, 800-MB/s, DRAM Byte-Wide Interface Featuring Command Interleaving and Concurrent Memory OperationGriffin, M. M. / Zerbe, J. / Tsang, G. et al. | 1998
- 1741
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY PAPERS - A Process-Independent, 800-MB-s, DRAM Byte-Wide Interface Featuring Command Interleaving and Concurrent Memory OperationGriffin, M.M. et al. | 1998
- 1752
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A Configurable DRAM Macro Design for 2112 Derivative Organizations to be Synthesized Using a Memory GeneratorYabe, T. / Miyano, S. / Sato, K. et al. | 1998
- 1752
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY BRIEF PAPERS - A Configurable DRAM Macro Design for 2112 Derivative Organizations to be Synthesized Using a Memory GeneratorYabe, T. et al. | 1998
- 1758
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY BRIEF PAPERS - An 8-Bit-Resolution, 360-ms Write Time Nonvolatile Analog Memory Based on Differentially Balanced Constant-Tunneling-Current Scheme (DBCS)Kim, K.-H. et al. | 1998
- 1758
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An 8-Bit-Resolution, 360-s Write Time Nonvolatile Analog Memory Based on Differentially Balanced Constant-Tunneling-Current Scheme (DBCS)Kim, K.-H. / Lee, K. / Jung, T.-S. et al. | 1998
- 1763
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Introduction To The Signal Processing SectionThon, L.E. et al. | 1998
- 1763
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - SIGNAL PROCESSING PAPERS - Introduction to the Signal Processing SectionThon, L.E. et al. | 1998
- 1765
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A 1.2-W Single-Chip MPEG2 MP@ML Video Encoder LSI Including Wide Search Range (H: 288, V: 96) Motion Estimation and 81-MOPS ControllerOgura, E. / Takashima, M. / Hiranaka, D. et al. | 1998
- 1765
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - SIGNAL PROCESSING PAPERS - A 1.2-W Single-Chip MPEG2 MP@ML Video Encoder LSI Including Wide Search Range (H: (plus-minus)288, V: (plus-minus)96) Motion Estimation and 81-MOPS ControllerOgura, E. et al. | 1998
- 1765
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A 1.2-W single-chip MPEG2 MP ML video encoder LSI including wide search range (H+or-288, V:+or-96) motion estimation and 81-MOPS controllerOgura, E. / Takashima, M. / Hiranaka, D. et al. | 1998
- 1772
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A 60-mW MPEG4 Video Codec Using Clustered Voltage Scaling with Variable Supply-Voltage SchemeTakahashi, M. / Hamada, M. / Nishikawa, T. et al. | 1998
- 1772
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - SIGNAL PROCESSING PAPERS - A 60-mW MPEG4 Video Codec Using Clustered Voltage Scaling with Variable Supply-Voltage SchemeTakahashi, M. et al. | 1998
- 1781
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - SIGNAL PROCESSING PAPERS - 0.5-mm CMOS Circuits for Demodulation and Decoding of an OFDM-Based Digital TV Signal Conforming to the European DVB-T StandardToso, C.Del et al. | 1998
- 1781
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0.5-m CMOS Circuits for Demodulation and Decoding of an OFDM-Based Digital TV Signal Conforming to the European DVB-T StandardDel Toso, C. / Combelles, P. / Galbrun, J. et al. | 1998
- 1793
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - SIGNAL PROCESSING PAPERS - A Power-Efficient Single-Chip OFDM Demodulator and Channel Decoder for Multimedia BroadcastingHuisken, J.A. et al. | 1998
- 1793
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A Power-Efficient Single-Chip OFDM Demodulator and Channel Decoder for Multimedia BroadcastingHuisken, J. A. / Van de Laar, F. A. M. / Bekooij, M. J. G. et al. | 1998
- 1799
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - SIGNAL PROCESSING PAPERS - An Energy-Security Scalable Encryption Processor Using an Embedded Variable Voltage DC-DC ConverterGoodman, J. et al. | 1998
- 1799
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An Energy/Security Scalable Encryption Processor Using an Embedded Variable Voltage DC/DC ConverterGoodman, J. / Dancy, A. P. / Chandrakasan, A. P. et al. | 1998
- 1810
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - SIGNAL PROCESSING PAPERS - A Low-Power, Voice-Controlled, H.263 Video Decoder for Portable ApplicationsBolcioni, L. et al. | 1998
- 1810
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A Low-Power, Voice-Controlled, H.263 Video Decoder for Portable ApplicationsBolcioni, L. / Borgatti, M. / Felici, M. et al. | 1998
- 1820
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - SIGNAL PROCESSING PAPERS - An 800-MOPS, 110-mW, 1.5-V, Parallel DSP for Mobile Multimedia ProcessingIgura, H. et al. | 1998
- 1820
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An 800-MOPS, 110-mW, 1.5-V, Parallel DSP for Mobile Multimedia ProcessingIgura, H. / Naito, Y. / Kazama, K. et al. | 1998
- 1829
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - SIGNAL PROCESSING PAPERS - A Low-Cost, 300-MHz, RISC CPU with Attached Media ProcessorSanthanam, S. et al. | 1998
- 1829
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A Low-Cost, 300-MHz, RISC CPU with Attached Media ProcessorSanthanam, S. / Baum, A. J. / Bertucci, D. et al. | 1998
- 1840
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A 240-Mbps, 1-W CMOS EPRML Read-Channel LSI Chip Using an Interleaved Subranging Pipeline A/D ConverterMatsuura, T. / Nara, T. / Komatsu, T. et al. | 1998
- 1840
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - SIGNAL PROCESSING PAPERS - A 240-Mbps, 1-W CMOS EPRML Read-Channel LSI Chip Using an Interleaved Subranging Pipeline A-D ConverterMatsuura, T. et al. | 1998
- 1851
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An EPR4 Read/Write Channel with Digital Timing RecoveryVishakhadatta, G. D. / Croman, R. / Goldenberg, M. et al. | 1998
- 1851
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - SIGNAL PROCESSING BRIEF PAPERS - An EPR4 Read-Write Channel with Digital Timing RecoveryVishakhadatta, G.D. et al. | 1998
- 1858
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SPECIAL ISSUE ON THE 1998 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - ANNOUNCEMENTS - Events Calendar| 1998