IEEE Journal of Solid-State Circuits
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
Table of contents
- 1427
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - Best Paper Award| 1999
- 1428
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Introduction to the Digital SectionGreenhill, D. et al. | 1999
- 1428
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - DIGITAL PAPERS - Introduction to the Digital SectionGreenhill, D. et al. | 1999
- 1430
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - DIGITAL PAPERS - A 0.2-mm, 1.8-V, SOI, 550-MHz, 64-b PowerPC Microprocessor with Copper InterconnectsAipperspach, A.G. et al. | 1999
- 1430
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A 0.2-m, 1.8-V, SOI, 550-MHz, 64-b PowerPC Microprocessor with Copper InterconnectsAipperspach, A. G. / Allen, D. H. / Cox, D. T. et al. | 1999
- 1436
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A 0.25-m, 600-MHz, 1.5-V, Fully Depleted SOI CMOS 64-Bit MicroprocessorPark, S. B. / Kim, Y. W. / Ko, Y. G. et al. | 1999
- 1436
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - DIGITAL PAPERS - A 0.25-mm, 600-MHz, 1.5-V, Fully Depleted SOI CMOS 64-Bit MicroprocessorPark, S.B. et al. | 1999
- 1446
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Performance Characteristics of SOI DRAM for Low-Power ApplicationPark, J.-W. / Kim, Y.-G. / Kim, I.-K. et al. | 1999
- 1446
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - DIGITAL PAPERS - Performance Characteristics of SOI DRAM for Low-Power ApplicationPark, J.-W. et al. | 1999
- 1454
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - DIGITAL PAPERS - A 650-MHz, IA-32 Microprocessor with Enhanced Data Streaming for Graphics and VideoSenthinathan, R. et al. | 1999
- 1454
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A 650-MHz, IA-32 Microprocessor with Enhanced Data Streaming for Graphics and VideoSenthinathan, R. / Fischer, S. / Rangchi, H. et al. | 1999
- 1466
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - DIGITAL PAPERS - A Seventh-Generation x86 MicroprocessorGolden, M. et al. | 1999
- 1466
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A Seventh-Generation x86 MicroprocessorGolden, M. / Hesley, S. / Scherer, A. et al. | 1999
- 1478
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A 450-MHz RISC Microprocessor with Enhanced Instruction Set and Copper InterconnectNicoletta, C. / Alvarez, J. / Barkin, E. et al. | 1999
- 1478
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - DIGITAL PAPERS - A 450-MHz RISC Microprocessor with Enhanced Instruction Set and Copper InterconnectNicoletta, C. et al. | 1999
- 1492
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An 18-A Standby Current 1.8-V, 200-MHz Microprocessor with Self-Substrate-Biased Data-Retention ModeMizuno, H. / Ishibashi, K. / Shimura, T. et al. | 1999
- 1492
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - DIGITAL PAPERS - An 18-mA Standby Current 1.8-V, 200-MHz Microprocessor with Self-Substrate-Biased Data-Retention ModeMizuno, H. et al. | 1999
- 1501
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A Versatile 3.3/2.5/1.8-V CMOS I/O Driver Built in a 0.2-m, 3.5-nm Tox, 1.8-V CMOS TechnologySanchez, H. / Siegel, J. / Nicoletta, C. et al. | 1999
- 1501
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - DIGITAL PAPERS - A Versatile 3.3-2.5-1.8-V CMOS I-O Driver Built in a 0.2-mm, 3.5-nm Tox, 1.8-V CMOS TechnologySánchez, H. et al. | 1999
- 1512
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High-Voltage-Tolerant I/O Buffers with Low-Voltage CMOS ProcessSingh, G. P. / Salem, R. B. et al. | 1999
- 1512
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - DIGITAL PAPERS - High-Voltage-Tolerant I-O Buffers with Low-Voltage CMOS ProcessSingh, G.P. et al. | 1999
- 1526
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110-GB/s Simultaneous Bidirectional Transceiver Logic Synchronized with a System ClockTakahashi, T. / Muto, T. / Shirai, Y. et al. | 1999
- 1526
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - DIGITAL PAPERS - 110-GB-s Simultaneous Bidirectional Transceiver Logic Synchronized with a System ClockTakahashi, T. et al. | 1999
- 1534
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Introduction to the memory sectionPathak, J. et al. | 1999
- 1534
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY PAPERS - Introduction to the Memory SectionPathak, J. et al. | 1999
- 1536
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY PAPERS - A 130-mm2, 256-Mbit NAND Flash with Shallow Trench Isolation TechnologyImamiya, K. et al. | 1999
- 1536
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A 130-mm^2, 256-Mbit NAND Flash with Shallow Trench Isolation TechnologyImamiya, K. / Sugiura, Y. / Nakamura, H. et al. | 1999
- 1544
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY PAPERS - A 256-Mb Multilevel Flash Memory with 2-MB-s Program Rate for Mass Storage ApplicationsNozoe, A. et al. | 1999
- 1544
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A 256-Mb Multilevel Flash Memory with 2-MB/s Program Rate for Mass Storage ApplicationsNozoe, A. / Kotani, H. / Tsujikawa, T. et al. | 1999
- 1551
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A 29-mm^2, 1.8-V-Only, 16-Mb DINOR Flash Memory with Gate-Protected-Poly-Diode (GPPD) Charge PumpMiyawaki, Y. / Ishizaki, O. / Okihara, Y. et al. | 1999
- 1551
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY PAPERS - A 29-mm2, 1.8-V-Only, 16-Mb DINOR Flash Memory with Gate-Protected-Poly-Diode (GPPD) Charge PumpMiyawaki, Y. et al. | 1999
- 1557
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY PAPERS - A Sub-40-ns Chain FRAM Architecture with 7-ns Cell-Plate-Line DriveTakashima, D. et al. | 1999
- 1557
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A Sub-40-ns Chain FRAM Architecture with 7-ns Cell-Plate-Line DriveTakashima, D. / Shuto, S. / Kunishima, I. et al. | 1999
- 1564
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY PAPERS - An 18-Mb, 12.3-GB-s CMOS Pipeline-Burst Cache SRAM with 1.54 Gb-s-pinZhao, C. et al. | 1999
- 1564
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An 18-Mb, 12.3-GB/s CMOS Pipeline-Burst Cache SRAM with 1.54 Gb/s/pinZhao, C. / Bhattacharya, U. / Denham, M. et al. | 1999
- 1571
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A 500-MHz Pipelined Burst SRAM with Improved SER ImmunitySato, H. / Wada, T. / Ohbayashi, S. et al. | 1999
- 1571
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY PAPERS - A 500-MHz Pipelined Burst SRAM with Improved SER ImmunitySato, H. et al. | 1999
- 1580
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A 390-mm^2, 16-Bank, 1-Gb DDR SDRAM with Hybrid Bitline ArchitectureKirihata, T. / Mueller, G. / Ji, B. et al. | 1999
- 1580
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY PAPERS - A 390-mm2, 16-Bank, 1-Gb DDR SDRAM with Hybrid Bitline ArchitectureKirihata, T. et al. | 1999
- 1589
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A 2.5-V, 333-Mb/s/pin, 1-Gbit, Double-Data-Rate Synchronous DRAMYoon, H. / Cha, G.-W. / Yoo, C. et al. | 1999
- 1589
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY PAPERS - A 2.5-V, 333-Mb-s-pin, 1-Gbit, Double-Data-Rate Synchronous DRAMYoon, H. et al. | 1999
- 1600
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A 1.6-GByte/s DRAM with Flexible Mapping Redundancy Technique and Additional Refresh SchemeTakase, S. / Kushiyama, N. et al. | 1999
- 1600
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - MEMORY PAPERS - A 1.6-GByte-s DRAM with Flexible Mapping Redundancy Technique and Additional Refresh SchemeTakase, S. et al. | 1999
- 1607
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - SIGNAL PROCESSING PAPERS - Introduction to the Signal Processing SectionMolloy, S. et al. | 1999
- 1607
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Introduction to the signal processing sectionMolloy, S. et al. | 1999
- 1608
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - SIGNAL PROCESSING PAPERS - A Microprocessor with a 128-Bit CPU, Ten Floating-Point MAC's, Four Floating-Point Dividers, and an MPEG-2 DecoderSuzuoki, M. et al. | 1999
- 1608
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A Microprocessor with a 128-Bit CPU, Ten Floating-Point MAC's, Four Floating-Point Dividers, and an MPEG-2 DecoderSuzuoki, M. / Kutaragi, K. / Hiroi, T. et al. | 1999
- 1619
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A 2.5-GFLOPS, 6.5 Million Polygons per Second, Four-Way VLIW Geometry Processor with SIMD Instructions and a Software Bypass MechanismKubosawa, H. / Higaki, N. / Ando, S. et al. | 1999
- 1619
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - SIGNAL PROCESSING PAPERS - A 2.5-GFLOPS, 6.5 Million Polygons per Second, Four-Way VLIW Geometry Processor with SIMD Instructions and a Software Bypass MechanismKubosawa, H. et al. | 1999
- 1627
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A Single-Chip CIF 30-Hz, H261, H263, and H263+ Video Encoder/Decoder with Embedded Display ControllerHarrand, M. / Sanches, J. / Bellon, A. et al. | 1999
- 1627
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - SIGNAL PROCESSING PAPERS - A Single-Chip CIF 30-Hz, H261, H263, and H263+ Video Encoder-Decoder with Embedded Display ControllerHarrand, M. et al. | 1999
- 1634
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - SIGNAL PROCESSING PAPERS - A Single-Chip Universal Digital Satellite Receiver with 480-MHz IF InputKwentus, A. et al. | 1999
- 1634
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A Single-Chip Universal Digital Satellite Receiver with 480-MHz IF InputKwentus, A. / Pai, P. / Jaffe, S. et al. | 1999
- 1647
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - SIGNAL PROCESSING PAPERS - A Single-Chip Universal Cable Set-Top Box-Modem TransceiverD'Luna, L.J. et al. | 1999
- 1647
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A Single-Chip Universal Cable Set-Top Box/Modem TransceiverD'Luna, L. J. / Tan, L. K. / Mueller, D. et al. | 1999
- 1661
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A 450-Mb/s Analog Front End for PRML Read ChannelsBloodworth, B. E. / Siniscalchi, P. P. / De Veirman, G. A. et al. | 1999
- 1661
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - SIGNAL PROCESSING PAPERS - A 450-Mb-s Analog Front End for PRML Read ChannelsBloodworth, B.E. et al. | 1999
- 1676
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - SIGNAL PROCESSING BRIEF PAPERS - A 3-V, 10-100-MHz Continuous-Time Seventh-Order 0.05(degree) Equiripple Linear Phase FilterRao, N. et al. | 1999
- 1676
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A 3-V, 10-100-MHz Continuous-Time Seventh-Order 0.05 Equiripple Linear Phase FilterRao, N. / Balan, V. / Contreras, R. et al. | 1999
- 1683
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - ANNOUNCEMENTS - Call for Papers -- Custom Integrated Circuits Conference 2000| 1999
- 1684
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SPECIAL ISSUE ON THE 1999 ISSCC: DIGITAL, MEMORY, AND SIGNAL PROCESSING - ANNOUNCEMENTS - First Announcement and Call for Papers -- 2000 Symposium in VLSI Circuits| 1999