Exponentiation Using Division Chains (English)
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In:
Computer arithmetic
7
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757-765
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1997
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ISBN:
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ISSN:
- Conference paper / Print
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Title:Exponentiation Using Division Chains
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Contributors:
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Conference:Symposium; 13th, Computer arithmetic ; 1997 ; Asilomar; CA
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Published in:Computer arithmetic , 7 ; 757-765IEEE TRANSACTIONS ON COMPUTERS C ; 47, 7 ; 757-765
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Publisher:
- New search for: IEEE
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Publication date:1997-01-01
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Size:9 pages
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Remarks:See also 8585.1633 13th 1997 for papers
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ISBN:
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ISSN:
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Type of media:Conference paper
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Type of material:Print
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Language:English
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Keywords:
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Source:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 2
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A Radix-8 CMOS S/390 MultiplierSchwarz, E. / Averill, R. / Sigal, L. / IEEE et al. | 1997
- 10
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A GaAs 32-Bit AdderBeaumont-Smith, A. / Burgess, N. / IEEE et al. | 1997
- 18
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SRT Division Architectures and ImplementationsHarris, D. / Oberman, S. / Horowitz, M. / IEEE et al. | 1997
- 26
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Power-Delay Characteristics of CMOS MultipliersCallaway, T. / Swartzlander, E. / IEEE et al. | 1997
- 34
-
On Radix Representation of RingsNielsen, A. M. / Kornerup, P. / IEEE et al. | 1997
- 44
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Theory and Applications for a Double-Base Number SystemDimitrov, V. / Jullien, G. / Miller, W. / IEEE et al. | 1997
- 54
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On the Design of IEEE Compliant Floating Point UnitsEven, G. / Paul, W. / IEEE et al. | 1997
- 64
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A Priori Worst-Case Error Bounds for Floating-Point ComputationsKraemer, W. / IEEE et al. | 1997
- 74
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Multiprecision Division on an 8-Bit ProcessorRice, E. / Hughey, R. / IEEE et al. | 1997
- 82
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Faithful Interpolation in Reciprocal TablesDas Sarma, D. / Matula, D. / IEEE et al. | 1997
- 92
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Exponentiation using Division ChainsWalter, C. / IEEE et al. | 1997
- 99
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Implementing Multiply-Accumulate Operation In Multiplication TimeStelling, P. / Oklobdzija, V. / IEEE et al. | 1997
- 108
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CORDIC Vectoring with Arbitrary Target ValueLang, T. / Antelo, E. / IEEE et al. | 1997
- 116
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Fast Rotations: Low-Cost Arithmetic Methods for Orthonormal RotationHekstra, G. / Deprettere, E. / IEEE et al. | 1997
- 126
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Generating a Power of an Operand by a Table Look-Up and a MultiplicationTakagi, N. / IEEE et al. | 1997
- 132
-
Towards Correctly Rounded TranscendentalsLefevre, V. / Muller, J.-M. / Tisserand, A. / IEEE et al. | 1997
- 140
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Pipelined Packet-Forwarding Floating Point: I. Foundations and a RounderMatula, D. / Nielsen, A. / IEEE et al. | 1997
- 148
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Pipelined Packet-Forwarding Floating Point: II. An AdderNielsen, A. / Matula, D. / Lyu, C. / Even, G. / IEEE et al. | 1997
- 156
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The SNAP Project: Design of Floating Point Arithmetic UnitsOberman, S. / Al-Twaijry, H. / Flynn, M. / IEEE et al. | 1997
- 168
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Fast Table-Driven Algorithms for Interval Elementary FunctionsPriest, D. / IEEE et al. | 1997
- 175
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Symmetric Bipartite Tables for Accurate Function ApproximationSchulte, M. / Stine, J. / IEEE et al. | 1997
- 184
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High-Performance Hardware for Function GenerationCao, J. / Wei, B. / IEEE et al. | 1997
- 190
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Arithmetic Co-Transformations in the Real and Complex Logarithmic Number SystemsArnold, M. / Bailey, T. / Cowles, J. / Winkel, M. / IEEE et al. | 1997
- 200
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Real/Complex Reconfigurable Arithmetic Using Redundant Complex Number SystemsAoki, T. / Amada, H. / Higuchi, T. / IEEE et al. | 1997
- 208
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Algorithms for Multi-Exponentiation Based on Complex ArithmeticDimitrov, V. / Jullien, G. / Miller, W. / IEEE et al. | 1997
- 218
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Fraction-Free RNS Algorithms for Solving Linear SystemsTurner, P. / IEEE et al. | 1997
- 225
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Fast Software Exponentiation in GF(2^K)Koc, C. / Acar, T. / IEEE et al. | 1997
- 234
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An RNS Montgomery Modular Multiplication AlgorithmBajard, J.-C. / Didier, L.-S. / Kornerup, P. / IEEE et al. | 1997
- 240
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Design and Implementation of an RNS Division AlgorithmHiasat, A. / Abdel-Aty-Zohdy, H. / IEEE et al. | 1997
- 250
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Scaled and Unscaled Residue Number System to Binary Conversion Techniques Using the Core FunctionBurgess, N. / IEEE et al. | 1997
- 260
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On-the-Fly Algorithms and Sequential MachinesFrougny, C. / IEEE et al. | 1997
- 266
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The Half-Adder Form and Early Branch Condition ResolutionLutz, D. / Jayasimha, D. / IEEE et al. | 1997
- 274
-
Synchronous Up/Down Counter with Clock Period Independent of Counter SizeStan, M. / IEEE et al. | 1997
- 282
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A Q-Coder Algorithm With Carry Free AdditionCena, G. / Montuschi, P. / Ciminiera, L. / Sarma, A. / IEEE et al. | 1997
- 722
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Long and Fast Up/Down CountersStan, M. R. / Tenca, A. F. / Ercegovac, M. D. / IEEE et al. | 1997
- iii
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Proceedings 13th IEEE Sympsoium on Computer Arithmetic| 1997