The K^*BMD: A Verification Data Structure (English)
- New search for: Drechsler, R.
- New search for: Becker, B.
- New search for: Ruppertz, S.
- New search for: Drechsler, R.
- New search for: Becker, B.
- New search for: Ruppertz, S.
In:
IEEE DESIGN AND TEST OF COMPUTERS
;
14
, 2
;
51-59
;
1997
-
ISSN:
- Article (Journal) / Print
-
Title:The K^*BMD: A Verification Data Structure
-
Contributors:
-
Published in:IEEE DESIGN AND TEST OF COMPUTERS ; 14, 2 ; 51-59
-
Publisher:
- New search for: IEEE INSTITUTE OF ELECTRICAL AND ELECTRONICS
-
Publication date:1997-01-01
-
Size:9 pages
-
ISSN:
-
Type of media:Article (Journal)
-
Type of material:Print
-
Language:English
- New search for: 621.395
- Further information on Dewey Decimal Classification
-
Classification:
DDC: 621.395 -
Source:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Table of contents – Volume 14, Issue 2
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 2
-
Letters -- VHDL fault injection| 1997
- 3
-
News -- 1149.5 update| 1997
- 4
-
Editorial Calendar| 1997
- 4
-
Panel Summaries -- IP conficts| 1997
- 5
-
Adventures in the Mainframe TradeWagner, K. et al. | 1997
- 5
-
A D&T Profile: Adventures in the Mainframe TradeWagner, Ken et al. | 1997
- 5
-
Adventures in the mainframe trade [Interview with Gene Amdahl]Wagner, K. et al. | 1997
- 14
-
Design, Design Automation, And Test In EuropeMarwedel, P. / Lopez-Barrio, C.A. et al. | 1997
- 14
-
Guest Editors Introduction: Design, Design Automation and Test in EuropeMarwedel, Peter et al. | 1997
- 16
-
System-on-a-chip cosimulation and compilationLiem, C. / Nacabal, F. / Valderrama, C. / Paulin, P. / Jerraya, A. et al. | 1997
- 25
-
Call for Articles| 1997
- 26
-
Open defects in CMOS RAM address decodersSachdev, M. et al. | 1997
- 34
-
CAD tools for bridging microsystems and foundriesKaram, J.M. / Courtois, B. / Boutamine, H. et al. | 1997
- 34
-
CAD Tools for Bringing Microsystems and FoundriesKaram, J. M. / Courtois, B. / Boutamine, H. et al. | 1997
- 40
-
Observable time windows: verifying high-level synthesis resultsBergamaschi, R.A. / Raje, S. et al. | 1997
- 51
-
The K*BMD: A verification data structureDrechsler, R. / Becker, B. / Ruppertz, S. et al. | 1997
- 60
-
Fault-secure parity prediction arithmetic operatorsNicolaidis, M. / Duarte, R.O. / Manich, S. / Figueras, J. et al. | 1997
- 72
-
Using a programming language for digital system designGupta, R.K. / Liao, S.Y. et al. | 1997
- 81
-
Testing Embedded CoresAnderson, T.L. / Chandramouli, R. / Dey, S. / Hemmady, S. / Mallipeddi, C. / Rajsuman, R. / Walther, R. / Zorian, Y. et al. | 1997
- 81
-
Testing Embedded Cores: How can we satisfy time-to-market demands for chips with high levels of integration and density| 1997
- 81
-
A D&T Roundtable: Testing Embedded Cores| 1997
- 90
-
Author Guidelines| 1997
- 93
-
DATC Newsletter| 1997
- 94
-
TTTC Newsletter| 1997
- 96
-
The Last Byte -- Is your project late?| 1997
-
CS Info Page| 1997