iCFP: Tolerating All-Level Cache Misses in In-Order Processors (English)
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- New search for: Hilton, A.
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In:
IEEE MICRO
;
30
, 1
;
12-19
;
2010
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ISSN:
- Article (Journal) / Print
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Title:iCFP: Tolerating All-Level Cache Misses in In-Order Processors
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Contributors:
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Published in:IEEE MICRO ; 30, 1 ; 12-19
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Publisher:
- New search for: IEEE INSTITUTE OF ELECTRICAL AND ELECTRONICS
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Publication date:2010-01-01
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Size:8 pages
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ISSN:
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Type of media:Article (Journal)
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Type of material:Print
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Language:English
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Table of contents – Volume 30, Issue 1
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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Contents| 2010
- 2
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Computer Society InformationHardavellas, Nikos et al. | 2010
- 3
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Call for Applications for Editor in Chief| 2010
- 4
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The Next Chapter at Google [Micro Economics]Greenstein, Shane et al. | 2010
- 4
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The Next Chapter at GoogleGreenstein, S. et al. | 2010
- 4
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Micro Economics - The Next Chapter at GoogleKelm, John H et al. | 2010
- 8
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Guest Editor's Introduction: Top Picks from the Computer Architecture Conferences of 2009Mudge, Trevor et al. | 2010
- 11
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Advertising/Product IndexWenisch, Thomas F et al. | 2010
- 12
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iCFP: Tolerating All-Level Cache Misses in In-Order ProcessorsHilton, A. / Nagarakatte, S. / Roth, A. et al. | 2010
- 29
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Near-Optimal Cache Block Placement with Reactive Nonuniform Cache ArchitecturesHardavellas, N. / Ferdman, M. / Falsafi, B. / Ailamaki, A. et al. | 2010
- 29
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A Task-Centric Memory Model for Scalable Accelerator ArchitecturesKelm, J.H. / Johnson, D.R. / Lumetta, S.S. / Patel, S.J. / Frank, M.I. et al. | 2010
- 40
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DMP: Deterministic Shared-Memory MultiprocessingDevietti, J. / Lucia, B. / Ceze, L. / Oskin, M. et al. | 2010
- 50
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Making Address-Correlated Prefetching PracticalWenisch, T.F. / Ferdman, M. / Ailamaki, A. / Falsafi, B. / Moshovos, A. et al. | 2010
- 60
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Accelerating Critical Section Execution with Asymmetric Multicore ArchitecturesAater Suleman, M. / Mutlu, O. / Qureshi, M.K. / Patt, Y.N. et al. | 2010
- 71
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Per-Thread Cycle AccountingEyerman, S. / Eeckhout, L. et al. | 2010
- 81
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AnySP: Anytime Anywhere Anyway Signal ProcessingWoh, M. / Sangwon Seo, / Mahlke, S. / Mudge, T. / Chakrabarti, C. / Flautner, K. et al. | 2010
- 92
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Gate-Level Information-Flow Tracking for Secure ArchitecturesTiwari, M. / Xun Li, / Wassel, H.M.G. / Mazloom, B. / Mysore, S. / Chong, F.T. / Sherwood, T. et al. | 2010
- 110
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Predicting Voltage Droops Using Recurring Program and Microarchitectural Event ActivityReddi, V.J. / Gupta, M. / Holloway, G. / Smith, M.D. / Gu-Yeon Wei, / Brooks, D. et al. | 2010
- 110
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Architectural Implications of Nanoscale-Integrated Sensing and ComputingPistol, C. / Chongchitmate, W. / Dwyer, C. / Lebeck, A.R. et al. | 2010
- 121
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Gordon: An Improved Architecture for Data-Intensive ApplicationsCaulfield, A.M. / Grupp, L.M. / Swanson, S. et al. | 2010
- 143
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Phase-Change Technology and the Future of Main MemoryLee, B.C. / Ping Zhou, / Jun Yang, / Youtao Zhang, / Bo Zhao, / Ipek, E. / Mutlu, O. / Burger, D. et al. | 2010
- 144
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Technical Writing [review of Managing Writers: A Real World Guide to Managing Technical Documentation (Hamilton, R.; 2009)]Mateosian, Richard et al. | 2010
- 144
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Micro Review - Technical Writing| 2010
- c1
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[Front cover]| 2010
- c3
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[Advertisement - Back cover]| 2010