2005 IEEE International Test Conference (ITC) : 8 - 10 November 2005, Austin, TX ; Vol. 2 (English)
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2005
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Title:2005 IEEE International Test Conference (ITC) : 8 - 10 November 2005, Austin, TX ; Vol. 2
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Conference:IEEE International Test Conference ; 2005 ; Austin, Tex.
ITC ; 2005 ; Austin, Tex. -
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Place of publication:Piscataway, NJ
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Publication date:2005
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Size:VIII S., S. 661-1323, 3 S
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Type of media:Conference Proceedings
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Type of material:Print
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Language:English
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Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 8 pp.
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A structured approach for the systematic test of embedded automotive communication systemsArmengaud, E. / Rothensteiner, F. / Steininger, A. / Pallierer, R. / Horauer, M. / Zauner, M. et al. | 2005
- 1 pp.
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Off-shore outsource DFT vs. build off-shore branch officesYu Huang, et al. | 2005
- 1 pp.
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How are we going to test SoCs on a board?: the users viewpointCarisson, G. et al. | 2005
- 1 pp.
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Reducing high-speed/RF test cost - guaranteed by design or guaranteed to fail?Slamani, M. et al. | 2005
- 1 pp.
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Business constraints drive test decisionsMuradali, F. et al. | 2005
- 1 pp.
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How are we going to test SoC's on a PCB?Webster, J. et al. | 2005
- 1 pp.
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How are we going to test SOC's on a board?Smith, M.J. et al. | 2005
- 1 pp.
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Achieving higher yield through diagnosisTamarapalli, N. et al. | 2005
- 1 pp.
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Business constraints drive test decisions - not vice versaSanjiv Taneja, et al. | 2005
- 1 pp.
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Panel synopsis: reducing high-speed/RF test cost: guaranteed by design or guaranteed to fail?Haggag, H. / Chatterjee, A. et al. | 2005
- 1 pp.
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The ITC test compression shootoutDavidson, S. et al. | 2005
- 1 pp.
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Correct by construction is guaranteed to failSunter, S. et al. | 2005
- 1 pp.
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Partnering with customer to achieve high yieldWang, J. et al. | 2005
- 1 pp.
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The final D-frontier: should DFT be outsourced?Basto, L. et al. | 2005
- 1 pp.
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Needs fabless yield ramp foundry partnership to be most successfulCory, B. et al. | 2005
- 1 pp.
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Test the test experts: do we know what we are doing?Kapur, R. et al. | 2005
- 1 pp.
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Position statement: "have we overcome the challenges associated with SoC and multi-core testing?"Wood, T. et al. | 2005
- 1 pp.
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Guaranteed by design or guaranteed to fail or guaranteed by test? or ... neither?Soma, M. et al. | 2005
- 1 pp.
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The case for outsourcing DFTRoehr, J.L. et al. | 2005
- 1 pp.
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Is the concern for soft-error overblown?Kundu, et al. | 2005
- 2 pp.
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Achieving higher yield through diagnosis-the ASIC perspectiveSchuermyer, C. et al. | 2005
- 2 pp.
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Board and system test with SoC DFTRobinson, G.D. et al. | 2005
- 2 pp.
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Panel: business constraints drive test decisionsSchneider, J. et al. | 2005
- 2 pp.
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Test compression - real issues and matching solutionsRajski, J. et al. | 2005
- 2 pp.
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Panel discussion for "have we overcome the challenges associated with SoC and multi-core testing?"Chelstrom, N. et al. | 2005
- 2 pp.
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Methods for improving test compressionTouba, N.A. et al. | 2005
- 2 pp.
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The concern for soft errors is not overblownSanda, P.N. et al. | 2005
- 2 pp.
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Business constraints drive test decisions planning, partnerships and successCampbell, M. et al. | 2005
- 2 pp.
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Today's SOC test challengesZorian, Y. et al. | 2005
- 2 pp.
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Outsourcing DFT: it can be done but it isn't easyWinemberg, L. et al. | 2005
- 2 pp.
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Encounter test OPMISR/sup +/ on-chip compressionKeller, B. et al. | 2005
- 2 pp.
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Test compression and logic BIST at your fingertipsShianling Wu, / Laung-Terng Wang, / Jin Woo Cho, / Zhigang Jiang, / Boryau Sheu, et al. | 2005
- 2 pp.
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Soft errors: is the concern for soft-errors overblown?Vijaykrishnan, N. et al. | 2005
- 2 pp.
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Darwin, thy name is systemForce, C. et al. | 2005
- 2 pp.
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Outsourcing DFT: the right mixHolzwarth, C. et al. | 2005
- 2 pp.
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XMAX: a practical and efficient compression architectureKee Sup Kim, et al. | 2005
- 2 pp.
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Have we overcome the challenges associated with SoC and multi-core testing?Menon, S. et al. | 2005
- 6 pp.
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STIL persistence [data reduction]Maston, G. / Villar, J. et al. | 2005
- 6 pp.
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Noncontact wafer probe using wireless probe cardsSellathamby, C.V. / Reja, M.M. / Lin Fu, / Bai, B. / Reid, E. / Slupsky, S.H. / Filanovsky, I.M. / Iniewski, K. et al. | 2005
- 6 pp.
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Lowering the cost of test with a scalable ATE custom processor and timing IC containing 400 high-linearity timing verniersArkin, B. et al. | 2005
- 7 pp.
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An update on IEEE 1149.6 - successes and issuesEklow, B. et al. | 2005
- 7 pp.
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Optimized reasoning-based diagnosis for non-random, board-level, production defectsO'Farrill, C. / Moakil-Chbany, M. / Eklow, B. et al. | 2005
- 7 pp.
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A practical perspective on reducing ASIC NTFsConroy, Z. / Richmond, G. / Xinli Gu, / Eklow, B. et al. | 2005
- 7 pp.
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The PXI carrier: a novel approach to ATE instrument developmentKushnick, E.B. et al. | 2005
- 7 pp.
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Case study: effectiveness of high-speed scan based feed forward voltage testing in reducing DPPM on a high volume ASICLurkins, J. / Hill, D. / Benware, B. et al. | 2005
- 7 pp.
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Safely backdriving low voltage devices at in-circuit testJacobsen, C. / Saye, T. / Trader, T. et al. | 2005
- 7 pp.
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Analyzing second-order effects between optimizations for system-level test-based model generationMargaria, T. / Raffelt, H. / Steffen, B. et al. | 2005
- 7 pp.
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A self-timed structural test methodology for timing anomalies due to defects and process variationsSingh, A.D. et al. | 2005
- 7 pp.
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Effect of lead free solders on in-circuit test processReinosa, R.D. et al. | 2005
- 7 pp.
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Gate exhaustive testingKyoung Youn Cho, / Mitra, S. / McCluskey, E.J. et al. | 2005
- 7 pp.
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Technique to improve the performance of time-interleaved A-D convertersAsami, K. et al. | 2005
- 7 pp.
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Diagnosis and analysis of an analog circuit failure using time resolved emission microscopySyed, A. / Herlein, R. / Cain, B. / Sauk, F. et al. | 2005
- 7 pp.
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Low cost multisite testing of quadruple band GSM transceiversZhang, L. / Heaton, D. / Largey, H. et al. | 2005
- 8 pp.
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Calibrating clock stretch during AC scan testingRearick, J. / Rodgers, R. et al. | 2005
- 8 pp.
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A transparent solution for providing remote wired or wireless communication to board and system level boundary-scan architecturesCollins, P. / Reis, I. / Simonen, M. / van Houcke, M. et al. | 2005
- 8 pp.
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IJTAG (internal JTAG): a step toward a DFT standardRearick, J. / Eklow, B. / Posse, K. / Crouch, A. / Bennetts, B. et al. | 2005
- 8 pp.
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"Driver on a floppy" delivery of ATE instrumentation softwareProskauer, D. et al. | 2005
- 8 pp.
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Test implications of lead-free implementation in a high-volume manufacturing environmentShu Peng, / Sam Wong, et al. | 2005
- 8 pp.
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Towards achieving relentless reliability gains in a server marketplace of teraflops, laptops, kilowatts, and "cost, cost, cost"...: making peace between a black art and the bottom lineVan Horn, J. et al. | 2005
- 8 pp.
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UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reductionLaung-Terng Wang, / Abdel-Hafez, K.S. / Xiaoqing Wen, / Sheu, B. / Shianling Wu, / Shyh-Horng Lin, / Ming-Tung Chang, et al. | 2005
- 8 pp.
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Power-scan chain: design for analog testabilityZjajo, A. / Bergveld, H.J. / Schuttert, R. / de Gyvez, J.P. et al. | 2005
- 8 pp.
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The effects of defects on high-speed boardsParker, K.P. et al. | 2005
- 8 pp.
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A novel process and hardware architecture to reduce burn-in costSchroeder, C. / Jin Pan, / Albertson, T. et al. | 2005
- 8 pp.
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A comprehensive production test solution for 1.5Gb/s and 3Gb/s serial-ATA - based on AWG and undersampling techniquesCai, Y. / Bhattacharyya, A. / Martone, J. / Verma, A. / Burchanowski, W. et al. | 2005
- 8 pp.
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Compressed pattern diagnosis for scan chain failuresYu Huang, / Wu-Tung Cheng, / Rajski, J. et al. | 2005
- 8 pp.
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A concurrent BIST scheme for on-line/off-line testing based on a pre-computed test setVoyiatzis, I. / Gizopoulos, D. / Paschalis, A. / Halatsis, C. et al. | 2005
- 8 pp.
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Drive only at speed functional testing; one of the techniques Intel is using to control test costsTripp, M. / Picano, S. / Schnarch, B. et al. | 2005
- 8 pp.
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Cost-effective designs of field service for electronic systemsYu-Ting Lin, / Williams, D. / Ambler, T. et al. | 2005
- 8 pp.
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Testing priority address encoder faults of content addressable memoriesJin-Fu Li, et al. | 2005
- 8 pp.
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Test time reduction of successive approximation register A/D converter by selective code measurementGoyal, S. / Chatterjee, A. / Atia, M. / Iglehart, H. / Chung Yu Chen, / Shenouda, B. / Khouzam, N. / Haggag, H. et al. | 2005
- 8 pp.
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Layering of the STIL extensionsMaston, G. / Taylor, T. et al. | 2005
- 8 pp.
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March AB, March AB1: new March tests for unlinked dynamic memory faultsBenso, A. / Bosio, A. / Di Carlo, S. / Di Natale, G. / Prinetto, P. et al. | 2005
- 8 pp.
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Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systemsRobertson, I. / Hetherington, G. / Leslie, T. / Parulkar, I. / Lesnikoski, R. et al. | 2005
- 8 pp.
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Test connections - tying application to processCarulli, J.M. / Anderson, T.J. et al. | 2005
- 8 pp.
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Synthesis of nonintrusive concurrent error detection using an even error detecting functionDutta, A. / Touba, N.A. et al. | 2005
- 8 pp.
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Analysis of pseudo-interleaving AWGOkawara, H. et al. | 2005
- 8 pp.
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Verifying flying prober performance - fitness is survivalRussell, B. et al. | 2005
- 8 pp.
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Diagnosis framework for locating failed segments of path delay faultsYing-Yen Chen, / Min-Pin Kuo, / Jing-Jia Liou, et al. | 2005
- 8 pp.
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Development of a software framework for open architecture ATEFritzsche, W.A. et al. | 2005
- 9 pp.
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Defect-based RF testing using a new catastrophic fault modelAcar, E. / Ozev, S. et al. | 2005
- 9 pp.
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Parallel, multi-DUT testing in an open architecture test systemAdachi, T. / Pramanick, A. / Elston, M. et al. | 2005
- 9 pp.
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Hierarchical DFT with enhancements for AC scan, test scheduling and on-chip compression - a case studyRemmers, J. / Lee, D. / Fisette, R. et al. | 2005
- 9 pp.
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High speed differential pin electronics over 6.4 GbpsOhshima, A. / Nomura, T. et al. | 2005
- 9 pp.
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Identification of systematic yield limiters in complex ASICS through volume structural test fail data visualization and analysisSchuermyer, C. / Cota, K. / Madge, R. / Benware, B. et al. | 2005
- 9 pp.
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A novel stuck-at based method for transistor stuck-open fault diagnosisXinyue Fan, / Moore, W. / Hora, C. / Gronthoud, G. et al. | 2005
- 9 pp.
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A scalable test strategy for network-on-chip routersAmory, A.M. / Briao, E. / Cota, E. / Lubaszewski, M. / Moraes, F.G. et al. | 2005
- 9 pp.
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Enabling yield analysis with X-compactStanojevic, Z. / Ruifeng Guo, / Mitra, S. / Venkataraman, S. et al. | 2005
- 9 pp.
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Use of MISRs for compression and diagnosticsKeller, B. / Bartenstein, T. et al. | 2005
- 9 pp.
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An optimal test pattern selection method to improve the defect coverageYuxin Tian, / Grimaila, M.R. / Weiping Shi, / Mercer, M.R. et al. | 2005
- 9 pp.
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A novel test methodology based on error-rate to support error-toleranceKuen-Jong Lee, / Tong-Yu Hsieh, / Breuer, M.A. et al. | 2005
- 9 pp.
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Evaluating ATE-equipment for volume diagnosisArnold, R. / Leininger, A. et al. | 2005
- 9 pp.
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Full-speed field-programmable memory BIST architectureXiaogang Du, / Mukherjee, N. / Wu-Tung Cheng, / Reddy, S.M. et al. | 2005
- 9 pp.
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Column parity and row selection (CPRS): a BIST diagnosis technique for multiple errors in multiple scan chainsHung-Mao Lin, / Li, J.C.-M. et al. | 2005
- 9 pp.
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Invisible delay quality - SDQM model lights up what could not be seenSato, Y. / Hamada, S. / Maeda, T. / Takatori, A. / Nozuyama, Y. / Kajihara, S. et al. | 2005
- 9 pp.
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CMOS high-speed, high-precision timing generator for 4.266-Gbps memory test systemSuda, M. / Yamamoto, K. / Okayasu, T. / Kantake, S. / Sudou, S. / Watanabe, D. et al. | 2005
- 9 pp.
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X-filter: filtering unknowns from compacted test responsesManish Sharma, / Wu-Tung Cheng, et al. | 2005
- 9 pp.
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Reducing test cost through the use of digital testers for analog testsSweeney, J. / Tsefrekas, A. et al. | 2005
- 9 pp.
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Node sensitivity analysis for soft errors in CMOS logicGill, B.S. / Papachristou, C. / Wolff, F.G. / Seifert, N. et al. | 2005
- 9 pp.
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Variance reduction and outliers: statistical analysis of semiconductor test dataDaasch, W.R. / Madge, R. et al. | 2005
- 9 pp.
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Forming N-detection test sets from one-detection test sets without test generationPomeranz, I. / Reddy, S.M. et al. | 2005
- 9 pp.
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Testing throughput computing interconnect topologies with Tbits/sec bandwidth in manufacturing and in fieldParulkar, I. / Huang, D. / Chua, L. / Doblar, D. et al. | 2005
- 9 pp.
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Multiple tests for each gate delay fault: higher coverage and lower test application costIrajpour, S. / Gupta, S.K. / Breuer, M.A. et al. | 2005
- 9 pp.
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An advanced optical diagnostic technique of IBM z990 eServer microprocessorSong, P. / Stellari, F. / Huott, B. / Wagner, O. / Srinivasan, U. / Yuen Chan, / Rizzolo, R. / Nam, H.J. / Eckhardt, J. / McNamara, T. et al. | 2005
- 9 pp.
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Test methodology for Freescale's high performance e600 core based on PowerPC/spl reg/ instruction set architectureTendolkar, N. / Belete, D. / Razdan, A. / Reyes, H. / Schwarz, B. / Sullivan, M. et al. | 2005
- 9 pp.
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A random access scans architecture to reduce hardware overheadMudlapur, A.S. / Agrawal, V.D. / Singh, A.D. et al. | 2005
- 9 pp.
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Functional vs. multi-VDD testing of RF circuitsSilva, E. / Pineda de Gyvez, J. / Gronthoud, G. et al. | 2005
- 9 pp.
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A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquerArasu, S.T. / Ravikumar, C.P. / Nandy, S.K. et al. | 2005
- 9 pp.
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Reconfigurable systems self-healing using mobile hardware agentsBenso, A. / Cilardo, A. / Mazzocca, N. / Miclea, L. / Prinetto, P. / Szilard, E. et al. | 2005
- 9 pp.
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Chasing subtle embedded RAM defects for nanometer technologiesPowell, T. / Kumar, A. / Rayhawk, J. / Mukherjee, N. et al. | 2005
- 9 pp.
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Simulation of transients caused by single-event upsets in combinational logicMohanram, K. et al. | 2005
- 9 pp.
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Impact of back side circuit edit on active device performance in bulk silicon ICsKerst, U. / Schlangen, R. / Kabakow, A. / Le Roy, E. / Lundquist, T.R. / Pauthner, S. et al. | 2005
- 9 pp.
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Testability features of the first-generation CELL processorRiley, M. / Bushard, L. / Chelstrom, N. / Kiryu, N. / Ferguson, S. et al. | 2005
- 9 pp.
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Bead probes in practiceParker, K.P. et al. | 2005
- 9 pp.
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A test case for 3Gbps serial attached SCSI (SAS)Cai, Y. / Fang, L. / Ratemo, R. / Liu, J. / Gross, K. / Kozma, M. et al. | 2005
- 10 pp.
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Methods for improving transition delay fault coverage using broadside testsDevtaprasanna, N. / Gunda, A. / Krishnamurthy, P. / Reddy, S.M. / Pomeranz, I. et al. | 2005
- 10 pp.
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The value of statistical testing for quality, yield and test cost improvementMadge, R. / Benware, B. / Ward, M. / Daasch, R. et al. | 2005
- 10 pp.
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Data-driven models for statistical testing: measurements, estimates and residualsDaasch, W.R. / Madge, R. et al. | 2005
- 10 pp.
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IEEE 1500 utilization in SOC design and testZorian, Y. / Yessayan, A. et al. | 2005
- 10 pp.
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JTAG-based vector and chain management for system testVan Treuren, B.G. / Peterson, B.E. / Miranda, J.M. et al. | 2005
- 10 pp.
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Test generation for ultra-high-speed asynchronous pipelinesFeng Shi, / Yiorgos Makris, / Nowick, S.M. / Singh, M. et al. | 2005
- 10 pp.
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A static noise impact analysis methodology for evaluating transient error effects in digital VLSI circuitsChong Zhao, / Xiaoliang Bai, / Sujit Dey, et al. | 2005
- 10 pp.
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A new probing technique for high-speed/high-density printed circuit boardsParker, K.P. et al. | 2005
- 10 pp.
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Burn-in reduction using principal component analysisNahar, A. / Daasch, R. / Subramaniam, S. et al. | 2005
- 10 pp.
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Structural tests for jitter tolerance in SerDes receiversSunter, S. / Roy, A. et al. | 2005
- 10 pp.
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Automated mapping of pre-computed module-level test sequences to processor instructionsGuramurthy, S. / Vasudevan, S. / Abraham, J.A. et al. | 2005
- 10 pp.
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Production-oriented interface testing for PCI-Express by enhanced loop-back techniqueLin, M. / Kwang-Ting Cheng, / Hsu, J. / Sun, M.C. / Chen, J. / Lu, S. et al. | 2005
- 10 pp.
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Remote boundary-scan system test control for the ATCA standardBackstrom, D. / Carlsson, G. / Larsson, E. et al. | 2005
- 10 pp.
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Jitter transformations in measurement instruments and discrepancies between measurement resultsZamek, I. / Zamek, S. et al. | 2005
- 10 pp.
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Hazard-aware statistical timing simulation and its applications in screening frequency-dependent defectsLee, B. / Hui Li, / Wang, L.-C. / Abadir, M.S. et al. | 2005
- 10 pp.
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A new approach for massive parallel scan designWoo Cheol Chung, / Ha, D.S. et al. | 2005
- 10 pp.
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Test data compression for IP embedded cores using selective encoding of scan slicesZhanglei Wang, / Chakrabarty, K. et al. | 2005
- 10 pp.
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I/sub DDQ/ test using built-in current sensing of supply line voltage dropBin Xue, / Walker, D.M.H. et al. | 2005
- 10 pp.
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A test point selection method for data converters using Rademacher functions and wavelet transformsCarter, C. / Ang, S. et al. | 2005
- 10 pp.
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Defect-oriented testing and diagnosis of digital microfluidics-based biochipsFei Su, / Hwang, W. / Mukherjee, A. / Chakrabarty, K. et al. | 2005
- 10 pp.
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Simulation-based target test generation techniques for improving the robustness of a software-based-self-test methodologyWen, C.H.-P. / Wang, L.-C. / Kwang-Ting Cheng, / Wei-Ting Liu, / Ji-Jan Chen, et al. | 2005
- 10 pp.
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Diagnosis with convolutional compactors in presence of unknown statesMrugalski, G. / Pogiel, A. / Rajski, J. / Tyszer, J. et al. | 2005
- 10 pp.
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Analysis of error-masking and X-masking probabilities for convolutional compactorsArai, M. / Fukumoto, S. / Iwasaki, K. et al. | 2005
- 10 pp.
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Comparative study of CA with phase shifters and GLFSRsChidambaram, S. / Kagaris, D. / Pradhan, D.K. et al. | 2005
- 10 pp.
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A leakage control system for thermal stability during burn-in testMeterelliyoz, M. / Mahmoodi, H. / Roy, K. et al. | 2005
- 10 pp.
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Low-capture-power test generation for scan-based at-speed testingXiaoqing Wen, / Yamashita, Y. / Morishima, S. / Kajihara, S. / Laung-Terng Wang, / Saluja, K.K. / Kinoshita, K. et al. | 2005
- 10 pp.
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Power-supply noise in SoCs: ATPG, estimation and controlNourani, M. / Radhakrishnan, A. et al. | 2005
- 10 pp.
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A vector-based approach for power supply noise analysis in test compactionJing Wang, / Ziding Yue, / Xiang Lu, / Wangqi Qiu, / Weiping Shi, / Walker, D.M.H. et al. | 2005
- 10 pp.
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A strategy for board level in-system programmable built-in assisted test and built-in self testFerry, J. / Scesnak, J. / Shaikh, S. et al. | 2005
- 10 pp.
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Word line pulsing technique for stability fault detection in SRAM cellsPavlov, A. / Azimane, M. / de Gyvez, J.P. / Sachdev, M. et al. | 2005
- 10 pp.
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Definitions of jitter measurement terms and relationshipsZamek, I. / Zamek, S. et al. | 2005
- 10 pp.
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A 16-bit resistor string DAC with full-calibration at final testParthasarathy, K. / Kuyel, T. / Zhongjun Yu, / Degang Chen, / Geiger, R. et al. | 2005
- 10 pp.
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Production test enhancement techniques for MB-OFDM ultra-wide band (UWB) devices: EVM and CCDFBhattacharya, S. / Senguttuvan, R. / Chatterjee, A. et al. | 2005
- 10 pp.
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A methodology for testing one-hot transmission gate multiplexersMcLaurin, T.L. / Frederick, F. / Slobodnik, R. et al. | 2005
- 10 pp.
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Efficient SAT-based combinational ATPG using multi-level don't-caresSaluja, N.S. / Khatri, S.P. et al. | 2005
- 10 pp.
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Design and analysis of multiple weight linear compactors of responses containing unknown valuesClouqueur, T. / Kamran Zarrineh, / Saluja, K.K. / Fujiwara, H. et al. | 2005
- 10 pp.
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High-performance ADC linearity test using low-precision signals in non-stationary environmentsLe Jin, / Parthasarathy, K. / Kuyel, T. / Geiger, R. / Degang Chen, et al. | 2005
- 10 pp.
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Microprocessor silicon debug based on failure propagation tracingCaty, O. / Dahlgren, P. / Bayraktaroglu, I. et al. | 2005
- 10 pp.
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XWRC: externally-loaded weighted random pattern testing for input test data compressionSeongmoon Wang, / Balakrishnan, K.J. / Chakradhar, S.T. et al. | 2005
- 10 pp.
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Definition of a robust modular SOC test architecture; resurrection of the single TAM daisy-chainWaayers, T. / Morren, R. / Grandi, R. et al. | 2005
- 10 pp.
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Logic soft errors: a major barrier to robust platform designMitra, S. / Ming Zhang, / Mak, T.M. / Seifert, N. / Zia, V. / Kee Sup Kim, et al. | 2005
- 10 pp.
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Built-in constraint resolutionGiles, G. / Irby, J. / Toneva, D. / Kun-Han Tsai, et al. | 2005
- 10 pp.
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Transient fault characterization in dynamic noisy environmentsPolian, I. / Hayes, J.P. / Kundu, S. / Becker, B. et al. | 2005
- 10 pp.
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Test and debug features of the RTO7 chipvan Kaam, K. / Vermeulen, B. / Bergveld, H.J. et al. | 2005
- 10 pp.
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Computational intelligence based testing for semiconductor measurement systemsLiau, E. / Schmitt-Landsiedel, D. et al. | 2005
- 10 pp.
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Compression mode diagnosis enables high volume monitoring diagnosis flowLeininger, A. / Muhmenthaler, P. / Wu-Tung Cheng, / Tamarapalli, N. / Wu Yang, / Hans Tsai, et al. | 2005
- 10 pp.
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Understanding NTF components from the fieldDavidson, S. et al. | 2005
- 10 pp.
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Progressive random access scan: a simultaneous solution to test power, test data volume and test timeDong Hyun Baik, / Saluja, K.K. et al. | 2005
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On concurrent test of wrapped cores and unwrapped logic blocks in SOCsQiang Xu, / Nicolici, N. et al. | 2005
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Logic proximity bridgesTran, E.N. / Krishna, V. / Zachariah, S. / Chakravarty, S. et al. | 2005
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Jitter spectrum analysis using continuous time interval analyzer (CTIA)Tabatabaei, S. / Ben-Zeev, F. / Farahmand, T. et al. | 2005
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A DDJ calibration methodology for high-speed test and measurement equipmentsFarahmand, T. / Tabatabaei, S. / Ben-Zeev, F. / IvanoV, A. et al. | 2005
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Enhanced launch-off-capture transition fault testingAhmed, N. / Tehranipoor, M. / Ravikumar, C.P. et al. | 2005
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Using built-in self-test and adaptive recovery for defect tolerance in molecular electronics-based nanofabricsZhanglei Wang, / Chakrabarty, K. et al. | 2005
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Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoringSaibal Mukhopadhyay, / Kunhyuk Kang, / Hamid Mahmoodi, / Kaushik Roy, et al. | 2005
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Programmable memory BISTBoutobza, S. / Nicolaidis, M. / Lamara, K.M. / Costa, A. et al. | 2005
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Testing and debugging delay faults in dynamic circuitsDatta, R. / Nassif, S. / Montoye, R. / Abraham, J.A. et al. | 2005
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A wideband low-noise ATE-based method for measuring jitter in GHz signalsYamaguchi, T.J. / Ishida, M. / Soma, M. et al. | 2005
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Efficient compression of deterministic patterns into multiple PRPG seedsWohl, P. / Waicukauski, J.A. / Patel, S. / DaSilva, F. / Williams, T.W. / Kapur, R. et al. | 2005
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External memory BIST for system-in-packageYamasaki, K. / Suzuki, I. / Kobayashi, A. / Horie, K. / Kobayashi, Y. / Aoki, H. / Hayashi, H. / Tada, K. / Tsutsumida, K. / Higeta, K. et al. | 2005
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Statistical and System Approaches For Jitter, Noise, And Bit Error Rate (BER) Tests For High Speed Serial Links And DevicesLi, M. P. / Institute of Electrical and Electronics Engineers et al. | 2005
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A New Measurement and Analysis Method for A Third Order Phase Locked Loop (PLL) Transfer FunctionMa, J. / Li, M. / Marlett, M. / Institute of Electrical and Electronics Engineers et al. | 2005
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Third-Order Phase Lock Loop Measurement and CharacterizationMa, J. / Li, M. / Marlett, M. et al. | 2005
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Test Methodology for Freescale's High Performance e600 Core Based on PowerPC® Instruction Set ArchitectureTendolkar, N. / Belete, D. / Razdan, A. / Reyes, H. / Schwarz, B. / Sullivan, M. / Institute of Electrical and Electronics Engineers et al. | 2005
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A Random Access Scan Architecture to Reduce Hardware OverheadMudlapur, A. S. / Agrawal, V. D. / Singh, A. D. / Institute of Electrical and Electronics Engineers et al. | 2005
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Towards Achieving Relentless Reliability Gains in a Server Marketplace of Teraflops, Laptops, Kilowatts, & "cost, Cost, COST".... (Making Peace between a Black Art and the Bottom Line)Van Horn, J. / Institute of Electrical and Electronics Engineers et al. | 2005
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IDDQ Test Using Built-In Current Sensing of Supply Line Voltage DropXue, B. / Walker, D. M. H. / Institute of Electrical and Electronics Engineers et al. | 2005
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Node Sensitivity Analysis for Soft Errors in CMOS Logic BalkaranGill, S. / Papachristou, C. / Wolff, F. G. / Seifert, N. / Institute of Electrical and Electronics Engineers et al. | 2005
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Stil PersistenceMaston, G. / Villar, J. / Institute of Electrical and Electronics Engineers et al. | 2005
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A Test Point Selection Method For Data Cconverters Using Rademacher Functions And Wavelet TransformsCarter, C. / Ang, S. / Institute of Electrical and Electronics Engineers et al. | 2005
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Encounter Test OPMISR + On-Chip CompressionKeller, B. / Institute of Electrical and Electronics Engineers et al. | 2005