Proceedings of the 2005 IEEEACM International conference on Computer-aided design (English)
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2005
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Title:Proceedings of the 2005 IEEEACM International conference on Computer-aided design
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Additional title:ICCAD '05
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- New search for: IEEE Computer Society
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Place of publication:Washington, DC
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Publication date:2005
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Size:Online-Ressource (1 online resource.)
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Remarks:Campusweiter Zugriff (Universität Hannover) - Vervielfältigungen (z.B. Kopien, Downloads) sind nur von einzelnen Kapiteln oder Seiten und nur zum eigenen wissenschaftlichen Gebrauch erlaubt. Keine Weitergabe an Dritte. Kein systematisches Downloaden durch Robots.
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Type of media:Conference Proceedings
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Type of material:Electronic Resource
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Language:English
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Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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Session 1A - Memory and arithmetic optimizations| 2005
- 3
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1A.1 Storage Assignment During High-Level Synthesis for Configurable AchitecturesGong, W. / Wang, G. / Kastner, R. / IEEE / Association for Computing Machinery et al. | 2005
- 3
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Storage assignment during high-level synthesis for configurable architecturesWenrui Gong, / Gang Wang, / Kastner, R. et al. | 2005
- 7
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1A.2 Performance-Driven Read-After-Write Dependencies Softening in High-Level SynthesisSautua, R. R. / Molina, M. C. / Mendias, J. M. / Hermida, R. / IEEE / Association for Computing Machinery et al. | 2005
- 7
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Performance-driven read-after-write dependencies softening in high-level synthesisRuiz-Sautua, R. / Molina, M.C. / Mendias, J.M. / Hermida, R. et al. | 2005
- 13
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1A.3 An Exact Algorithm for the Maximal Sharing of Partial Terms in Multiple Constant MultiplicationsFlores, P. F. / Monteiro, J. C. / Costa, E. C. / IEEE / Association for Computing Machinery et al. | 2005
- 13
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An exact algorithm for the maximal sharing of partial terms in multiple constant multiplicationsFlores, P. / Monteiro, J. / Costa, E. et al. | 2005
- 17
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Session 1B - Design manufacturing interaction| 2005
- 19
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1B.1 FPGA Device and Architecture Evaluation Considering Process VariationsWong, H. Y. P. / Cheng, L. / Lin, Y. / He, L. / IEEE / Association for Computing Machinery et al. | 2005
- 19
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FPGA device and architecture evaluation considering process variationsHo-Yan Wong, / Lerong Cheng, / Yan Lin, / Lei He, et al. | 2005
- 25
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1B.2 Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular FabricsRan, Y. / Sadowska, M. M. / IEEE / Association for Computing Machinery et al. | 2005
- 25
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Via-configurable routing architectures and fast design mappability estimation for regular fabricsRan, Y. / Marek-Sadowska, M. et al. | 2005
- 33
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1B.3 SPIDER: Simultaneous Post-Layout IR-Drop and Metal Density Enhancement with Redundant FillLeung, K. S. / IEEE / Association for Computing Machinery et al. | 2005
- 33
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SPIDER: simultaneous post-layout IR-drop and metal density enhancement with redundant fillKwok-Shing Leung, et al. | 2005
- 39
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Session 1C - Detailed placement| 2005
- 41
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1C.1 Computational Geometry Based Placement MigrationLuo, T. / Ren, H. / Alpert, C. J. / Pan, D. Z. / IEEE / Association for Computing Machinery et al. | 2005
- 41
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Computational geometry based placement migrationLuo, T. / Ren, H. / Alpert, C.J. / Pan, D.Z. et al. | 2005
- 48
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1C.2 An Efficient and Effective Detailed Placement AlgorithmPan, M. / Viswanathan, N. / Chu, C. / IEEE / Association for Computing Machinery et al. | 2005
- 48
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An efficient and effective detailed placement algorithmMin Pan, / Viswanathan, N. / Chu, C. et al. | 2005
- 56
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1C.3 Post-Placement Rewiring and Rebuffering by Exhaustive Search for Functional SymmetriesChang, K. / Markov, I. L. / Bertacco, V. / IEEE / Association for Computing Machinery et al. | 2005
- 56
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Post-placement rewiring and rebuffering by exhaustive search for functional symmetriesKai-hui Chang, / Markov, I.L. / Bertacco, V. et al. | 2005
- 64
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Wirelength optimization by optimal block orientationXin Hao, / Brewer, F. et al. | 2005
- 64
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1C.4 Wirelength Optimization by Optimal Block OrientationHao, X. / Brewer, F. / IEEE / Association for Computing Machinery et al. | 2005
- 71
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Session 1D - Digital, analog and RF test| 2005
- 73
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Parametric test development for RF circuits targeting physical fault locations and using specification-based fault definitionsAcar, E. / Ozev, S. et al. | 2005
- 73
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1D.1 Parametric Test Development for RF Circuits Targeting Physical Fault Locations and Using Specification-Based Fault DefinitionsAcar, E. / Ozev, S. / IEEE / Association for Computing Machinery et al. | 2005
- 80
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1D.2 Response Shaper: A Novel Technique To Enhance Unknown Tolerance for Output Response CompactionChao, M. / Wang, S. / Chakradhar, S. T. / Cheng, K.-T. / IEEE / Association for Computing Machinery et al. | 2005
- 80
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Response shaper: a novel technique to enhance unknown tolerance for output response compactionChao, M.C.-T. / Seongmoon Wang, / Chakradhar, S.T. / Kwang-Ting Cheng, et al. | 2005
- 88
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Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCsSehgal, A. / Chakrabarty, K. et al. | 2005
- 88
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1D.3 Test Planning for the Effective Utilization of Port-Scalable Testers for Heterogeneous Core-Based SOCsSehgal, A. / Chakrabarty, K. / IEEE / Association for Computing Machinery et al. | 2005
- 94
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A cocktail approach on random access scan toward low power and high efficiency testShih Ping Lin, / Chung Len Lee, / Chen, J.E. et al. | 2005
- 94
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1D.4S Cocktail Scan Based on Random Access Scan Toward Low Power and High Efficiency TestLin, S. P. / Lee, C. L. / Chen, J. E. / IEEE / Association for Computing Machinery et al. | 2005
- 100
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A statistical study of the effectiveness of BIST jitter measurement techniquesBordoley, D. / Nguyen, H. / Soma, M. et al. | 2005
- 100
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1D.5S A Statistical Study of the Effectiveness of BIST Jitter Measurement TechniquesBordoley, D. A. / Nguyen, H. / Soma, M. / IEEE / Association for Computing Machinery et al. | 2005
- 109
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Session 2A - Embedded turorial: design trends| 2005
- 111
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The circuit design of the synergistic processor element of a CELL processorTakahashi, O. / Cook, R. / Cottier, S. / Dhong, S.H. / Flachs, B. / Hirairi, K. / Kawasumi, A. / Murakami, H. / Noro, H. / Oh, H. et al. | 2005
- 111
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2A.1 The Circuit Design of the Synergistic Processor Element of a Cell ProcessorTakahashi, O. / Cook, R. / Cottier, S. / Dhong, S. H. / Flachs, B. / Hirairi, K. / Kawasumi, A. / Murakami, H. / Noro, N. / Oh, H. et al. | 2005
- 118
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2A.2 Adaptive Designs for Power and Thermal OptimizationMcGowen, R. / IEEE / Association for Computing Machinery et al. | 2005
- 118
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Adaptive designs for power and thermal optimizationMcGowen, R. et al. | 2005
- 122
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2A.3 Digital RF Processor (DRP) for Cellular PhonesStaszewski, R. B. / Muhammed, K. / Leipold, D. / IEEE / Association for Computing Machinery et al. | 2005
- 122
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Digital RF processor (DRP/spl trade/) for cellular phonesStaszewski, R.B. / Muhammad, K. / Leipold, D. et al. | 2005
- 131
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Session 2B - Physical design for manufacturing| 2005
- 133
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2B.1 A Layout Dependent Full-Chip Copper Electroplating (ECP) Topography ModelLuo, J. / Su, Q. / Chiang, C. / Kawa, J. / IEEE / Association for Computing Machinery et al. | 2005
- 133
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A layout dependent full-chip copper electroplating topography modelJianfeng Luo, / Qing Su, / Chiang, C. / Kawa, J. et al. | 2005
- 141
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Interval-valued statistical modeling of oxide chemical-mechanical polishingMa, J.D. / Fang, C.F. / Rutenbar, R.A. / Xiaolin Xie, / Boning, D.S. et al. | 2005
- 141
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2B.2 Interval-Valued Statistical Modeling of Oxide Chemical-Mechanical PolishingMa, J. / Fang, C. / Rutenbar, R. A. / Xie, X. / Boning, D. S. / IEEE / Association for Computing Machinery et al. | 2005
- 149
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2B.3 Fast and Efficient Phase Conflict Detection and Correction in Standard-Cell LayoutsChiang, C. / Kahng, A. B. / Sinha, S. / Xu, X. / IEEE / Association for Computing Machinery et al. | 2005
- 149
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Fast and efficient phase conflict detection and correction in standard-cell layoutsChiang, C. / Kahng, A.B. / Sinha, S. / Xu, X. et al. | 2005
- 157
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Session 2C - Large-scale layout techniques| 2005
- 159
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IMF: interconnect-driven multilevel floorplanning for large-scale building-module designsTung-Chieh Chen, / Yao-Wen Chang, / Shyh-Chang Lin, et al. | 2005
- 159
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2C.1 IMF: Interconnect-Driven Multilevel Floorplanning for Large-Scale Building-Module DesignsChen, T. / Chang, Y.-W. / Lin, S.-C. / IEEE / Association for Computing Machinery et al. | 2005
- 165
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Robust mixed-size placement under tight white-space constraintsCong, J. / Romesis, M. / Shinnerl, J.R. et al. | 2005
- 165
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2C.2 Robust Mixed-Size Placement Under Tight White-Space ConstraintsCong, J. / Romesis, M. / Shinnerl, J. / IEEE / Association for Computing Machinery et al. | 2005
- 173
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2C.3 Intrinsic Shortest Path Length: A New, Accurate A Priori Wirelength EstimatorReda, S. / Kahng, A. B. / IEEE / Association for Computing Machinery et al. | 2005
- 173
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Intrinsic shortest path length: a new, accurate a priori wirelength estimatorKahng, A.B. / Reda, S. et al. | 2005
- 181
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Session 2D - Novel ideas and logic synthesis| 2005
- 183
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Synthesis methodology for built-in at-speed testingYinghua Li, / Kondratyev, A. / Brayton, R. et al. | 2005
- 183
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2D.1 Synthesis Methodology for Built-In At-Speed TestingLi, Y. / Kondratyev, A. / Brayton, R. K. / IEEE / Association for Computing Machinery et al. | 2005
- 189
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Clustering for processing rate optimizationChuan Lin, / Jia Wang, / Hai Zhou, et al. | 2005
- 189
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2D.2 Clustering for Processing Rate OptimizationLin, C. / Zhou, H. / Wang, J. / IEEE / Association for Computing Machinery et al. | 2005
- 196
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2D.3 ConvexFit: An Optimal Minimum-Error Convex Fitting and Smoothing Algorithm with Application to Gate-SizingRoy, S. C. / Chen, W. / Chen, C. / IEEE / Association for Computing Machinery et al. | 2005
- 196
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ConvexFit: an optimal minimum-error convex fitting and smoothing algorithm with application to gate-sizingSanghamitra Roy, / Weijen Chen, / Charlie Chung-Ping Chen, et al. | 2005
- 205
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Session 3A - Embedded tutorial: opportunities and challenges with double-gated devices| 2005
- 207
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FinFETs for nanoscale CMOS digital integrated circuitsTsu-Jae King, et al. | 2005
- 207
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3A.1 FinFETs for Nanoscale CMOS Digital Integrated CircuitsKing, T.-J. / IEEE / Association for Computing Machinery et al. | 2005
- 211
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Physics-based compact modeling for nonclassical CMOSTrivedi, V.P. / Fossum, G. / Mathew, L. / Chowdhury, M.M. / Zhang, W. / Workman, G.O. / Nguyen, B.-Y. et al. | 2005
- 211
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3A.2 Physics-Based Compact Modeling for Nonclassical CMOSTrivedi, V. P. / Fossum, J. G. / Mathew, L. / Chowdhury, M. M. / Zhang, W. / Workman, G. O. / Nguyen, B. Y. / IEEE / Association for Computing Machinery et al. | 2005
- 217
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3A.3 Double-Gate SOI Devices for Low-Power and High-Performance ApplicationsRoy, K. / Mahmoodi, H. / Mukhopadhyay, S. / Ananthan, H. / Bansal, A. / Cakici, T. / IEEE / Association for Computing Machinery et al. | 2005
- 217
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Double-gate SOI devices for low-power and high-performance applicationsRoy, K. / Mahmoodi, H. / Mukhopadhyay, S. / Ananthan, H. / Bansal, A. / Cakici, T. et al. | 2005
- 225
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Thermal simulation techniques for nanoscale transistorsRowlette, J. / Pop, E. / Sinha, S. / Panzer, M. / Goodson, K. et al. | 2005
- 225
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3A.4 Thermal Simulation Techniques for Nano TransistorsRowlette, J. / Pop, E. / Sinha, S. / Panzer, M. / Goodson, K. E. / IEEE / Association for Computing Machinery et al. | 2005
- 229
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Session 3B - Routing and application specific NoC architectures| 2005
- 231
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3B.1 An Automated Technique for Topology and Route Generation of Application Specific On-Chip Interconnection NetworksSrinivasan, K. / Chatha, K. S. / Konjevod, G. / IEEE / Association for Computing Machinery et al. | 2005
- 231
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An automated technique for topology and route generation of application specific on-chip interconnection networksSrinivasan, K. / Chatha, K.S. / Konjevod, G. et al. | 2005
- 238
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Deadlock-free routing and component placement for irregular mesh-based networks-on-chipSchafer, M.K.F. / Hollstein, T. / Zimmer, H. / Glesner, M. et al. | 2005
- 238
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3B.2 Deadlock-Free Routing and Component Placement for Irregular Mesh-based Networks-on-ChipSchafer, M. / Hollstein, T. / Zimmer, H. / Glesner, M. / IEEE / Association for Computing Machinery et al. | 2005
- 246
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Application-specific network-on-chip architecture customization via long-range link insertionOgras, U.Y. / Marculescu, R. et al. | 2005
- 246
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3B.3 Application-Specific Network-on-Chip Architecture Customization via Long-Range Link InsertionOgras, U. Y. / Marculescu, R. / IEEE / Association for Computing Machinery et al. | 2005
- 254
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NoCEE: energy macro-model extraction methodology for network on chip routersChan, J. / Parameswaran, S. et al. | 2005
- 254
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3B.4 NoCEE: Energy Macro-Model Extraction Methodology for Network on Chip RoutersChan, J. / Parameswaran, S. / IEEE / Association for Computing Machinery et al. | 2005
- 261
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Session 3C - Memory driven code and architecture optimizations| 2005
- 263
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3C.1 Architecture and Compilation for Data Bandwidth Improvement in Configurable Embedded ProcessorsCong, J. / Han, G. / Zhang, Z. / IEEE / Association for Computing Machinery et al. | 2005
- 263
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Architecture and compilation for data bandwidth improvement in configurable embedded processorsCong, J. / Guoling Han, / Zhiru Zhang, et al. | 2005
- 271
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Code restructuring for improving cache performance of MPSoCsChen, G. / Kandemir, M. et al. | 2005
- 271
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3C.2 Code Restructuring for Improving Cache Performance of MPSoCsChen, G. / Kandemir, M. / IEEE / Association for Computing Machinery et al. | 2005
- 275
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3C.3 Two-Dimensional Data Locality: Definition, Abstraction, and ApplicationKandemir, M. / IEEE / Association for Computing Machinery et al. | 2005
- 275
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2D data locality: definition, abstraction, and applicationKandemir, M. et al. | 2005
- 279
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3C.4 Integrating Loop and Data Optimizations for Locality within a Constraint Network Based FrameworkChen, G. / Ozturk, O. / Kandemir, M. / Kolcu, I. / IEEE / Association for Computing Machinery et al. | 2005
- 279
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Integrating loop and data optimizations for locality within a constraint network based frameworkGuilin Chen, / Ozturk, O. / Kandemir, M. / Kolcu, I. et al. | 2005
- 283
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Session 3D - Exploiting arithmetic constructs in verification| 2005
- 285
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System level verification of digital signal processing applications based on the polynomial abstraction techniqueRaudvere, T. / Singh, A.K. / Sander, I. / Jantsch, A. et al. | 2005
- 285
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3D.1 System Level Verification of Digital Signal Processing Applications Based on the Polynomial Abstraction TechniqueRaudvere, T. / Singh, A. K. / Sander, I. / Jantsch, A. / IEEE / Association for Computing Machinery et al. | 2005
- 291
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Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebraShekhar, N. / Kalla, P. / Enescu, F. / Gopalakrishnan, S. et al. | 2005
- 291
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3D.2 Equivalence Verification of Polynomial Datapaths with Fixed-Size Bit-Vectors using Finite Ring AlgebraShekhar, N. / Kalla, P. / Enescu, F. / Gopalakrishnan, S. / IEEE / Association for Computing Machinery et al. | 2005
- 297
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3D.3 RTL SAT Simplification by Interval Arithmetic ReasoningParthasarathy, G. / Iyer, M. K. / Cheng, K. T. / Brewer, F. / IEEE / Association for Computing Machinery et al. | 2005
- 297
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RTL SAT simplification by Boolean and interval arithmetic reasoningParthasarathy, G. / Iyer, M.K. / Cheng, K.-T. / Brewer, F. et al. | 2005
- 303
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3D.4 Runtime Integrity Checking for Inter-Object ConnectionsChen, G. / Kandemir, M. / IEEE / Association for Computing Machinery et al. | 2005
- 303
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Runtime integrity checking for inter-object connectionsGuilin Chen, / Mahmut Kandemir, et al. | 2005
- 307
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Session 4A - Buffers and voltage islands| 2005
- 309
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4A.1 Optimal Post-Placement Voltage Island Generation Under Performance RequirementWu, H. / Liu, I. / Wang, Y. / Wong, M. / IEEE / Association for Computing Machinery et al. | 2005
- 309
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Post-placement voltage island generation under performance requirementHuaizhi Wu, / I-Min Liu, / Wong, M.D.F. / Yusu Wang, et al. | 2005
- 317
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4A.2 Buffer Insertion Under Process Variations for Delay MinimizationDeng, L. / Wong, M. / IEEE / Association for Computing Machinery et al. | 2005
- 317
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Buffer insertion under process variations for delay minimizationLiang Deng, / Wong, M.D.F. et al. | 2005
- 322
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4A.3 Efficient Algorithms for Buffer Insertion in General Circuits Based on Network FlowChen, R. / Zhou, H. / IEEE / Association for Computing Machinery et al. | 2005
- 322
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Efficient algorithms for buffer insertion in general circuits based on network flowRuiming Chen, / Hai Zhou, et al. | 2005
- 327
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Session 4B - Sequential circuit optimization| 2005
- 329
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Trade-off between latch and flop for min-period sequential circuit designs with crosstalkChuan Lin, / Hai Zhou, et al. | 2005
- 329
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4B.1 Trade-off between Latch and Flop for Min-Period Sequential Circuit Designs with CrosstalkLin, C. / Zhou, H. / IEEE / Association for Computing Machinery et al. | 2005
- 335
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4B.2 Flip-Flop Insertion With Shifted-Phase Clocks For FPGA Power ReductionLim, H. / Lee, K. / Cho, Y. / Chang, N. / IEEE / Association for Computing Machinery et al. | 2005
- 335
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Flip-flop insertion with shifted-phase clocks for FPGA power reductionHyeonmin Lim, / Kyungsoo Lee, / Youngjin Cho, / Naehyuck Chang, et al. | 2005
- 343
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4B.3 Acyclic Modeling of Combinational LoopsGupta, A. / Selvidge, C. / IEEE / Association for Computing Machinery et al. | 2005
- 343
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Acyclic modeling of combinational loopsGupta, A. / Selvidge, C. et al. | 2005
- 349
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Session 4C - Power grid verification| 2005
- 351
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Fast algorithms for IR drop analysis in large power gridYu Zhong, / Wong, M.D.F. et al. | 2005
- 351
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4C.1 Fast Algorithms for IR Drop Analysis in Large Power GridZhong, Y. / Wong, M. D. F. / IEEE / Association for Computing Machinery et al. | 2005
- 358
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4C.2 Incremental Partitioning-Based Vectorless Power Grid VerificationKouroussis, D. / Ferzli, I. A. / Najm, F. N. / IEEE / Association for Computing Machinery et al. | 2005
- 358
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Incremental partitioning-based vectorless power grid verificationKouroussis, D. / Ferzli, I.A. / Najm, F.N. et al. | 2005
- 365
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Static timing analysis considering power supply variationsSanjay Pant, / Blaauw, D. et al. | 2005
- 365
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4C.3 Static Timing Analysis Considering Power Supply VariationsPant, S. / Blaauw, D. / IEEE / Association for Computing Machinery et al. | 2005
- 373
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Session 4D - Nanoelectronics| 2005
- 375
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4D.1 Hybrid Semiconductor/Nanoelectronic Circuits: Devices, Architectures, and Design AutomationDeHon, A. / Likharev, K. K. / IEEE / Association for Computing Machinery et al. | 2005
- 375
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Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automationDeHon, A. / Likharev, K.K. et al. | 2005
- 383
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4D.2 Performance Analysis of Carbon Nanotube Interconnects for VLSI ApplicationsSrivastava, N. / Banerjee, K. / IEEE / Association for Computing Machinery et al. | 2005
- 383
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Performance analysis of carbon nanotube interconnects for VLSI applicationsSrivastava, N. / Banerjee, K. et al. | 2005
- 391
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Session 5A - Variability in design| 2005
- 393
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5A.1 DiCER: Distributed and Cost-Effective Redundancy for Variation ToleranceWu, D. / Venkataraman, G. / Li, Q. / Hu, J. / Mahapatra, R. N. / IEEE / Association for Computing Machinery et al. | 2005
- 393
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DiCER: distributed and cost-effective redundancy for variation toleranceDi Wu, / Venkataraman, G. / Jiang Hu, / Quiyang Li, / Mahapatra, R. et al. | 2005
- 398
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Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variabilityTsukamoto, Y. / Nii, K. / Imaoka, S. / Oda, Y. / Ohbayashi, S. / Yoshizawa, T. / Makino, H. / Ishibashi, K. / Shinohara, H. et al. | 2005
- 398
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5A.2 Worst-Case Analysis to Obtain Stable Read/Write DC Margin of High Density 6T-SRAM-Array with Local Vth VariabilityTsukamoto, Y. / Koji, N. / Imaoka, S. / Oda, Y. / Ohbayashi, S. / Yoshizawa, T. / Makino, H. / Ishibashi, K. / Shinohara, H. / IEEE et al. | 2005
- 406
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5A.3 Noise Margin Analysis for Dynamic Logic CircuitsYang, S. / Greenstreet, M. R. / IEEE / Association for Computing Machinery et al. | 2005
- 406
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Noise margin analysis for dynamic logic circuitsSuwen Yang, / Greenstreet, M. et al. | 2005
- 413
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Session 5B - Efficient analog design space exploration techniques| 2005
- 415
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Efficient analog platform characterization through analog constraint graphsDe Bernardinis, F. / Sangiovanni Vincentelli, A. et al. | 2005
- 415
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5B.1 Efficient Analog Platform Characterization Through Analog Constraint GraphsDe Bernardinis, F. / Vincentelli, A. S. / IEEE / Association for Computing Machinery et al. | 2005
- 422
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Performance-centering optimization for system-level analog design explorationXin Li, / Jian Wang, / Pileggi, L.T. / Tun-Shih Chen, / Wanju Chiang, et al. | 2005
- 422
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5B.2 Performance-Centering Optimization for System-Level Analog Design ExplorationLi, X. / Wang, J. / Pileggi, L. T. / Chiang, W. / Chen, T.-S. / IEEE / Association for Computing Machinery et al. | 2005
- 430
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Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuitsAgarwal, A. / Vemuri, R. et al. | 2005
- 430
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5B.3 Hierarchical Performance Macromodels of Feasible Regions for Synthesis of Analog and RF CircuitsAgarwal, A. / Vemuri, R. / IEEE / Association for Computing Machinery et al. | 2005
- 437
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Session 5C - Dynamic voltage scaling| 2005
- 439
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Battery optimization vs energy optimization: which to choose and when?Rao, R. / Vrudhula, S. et al. | 2005
- 439
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5C.1 Battery Optimization vs. Energy Optimization: Which to Choose and When?Rao, R. / Vrudhula, S. / Chang, N. / IEEE / Association for Computing Machinery et al. | 2005
- 446
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Dynamic voltage scaling for the schedulability of jitter-constrained real-time embedded systemsMochocki, B. / Xiaobo Sharon Hu, / Racu, R. / Ernst, R. et al. | 2005
- 446
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5C.2 Dynamic Voltage Scaling for the Schedulability of Jitter-Constrained Real-Time Embedded SystemsMochocki, B. C. / Hu, X. S. / Racu, R. / Ernst, R. / IEEE / Association for Computing Machinery et al. | 2005
- 450
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5C.3 Optimal Integration of Inter-Task and Intra-Task Dynamic Voltage Scaling Techniques for Hard Real-Time ApplicationsSeo, J. / Dutt, N. D. / Kim, T. / IEEE / Association for Computing Machinery et al. | 2005
- 450
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Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applicationsJaewon Seo, / Taewhan Kim, / Dutt, N.D. et al. | 2005
- 456
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5C.4 Compiler-Directed Voltage Scaling on Communication Links for Reducing Power ConsumptionLi, F. / Chen, G. / Kandemir, M. / IEEE / Association for Computing Machinery et al. | 2005
- 456
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Compiler-directed voltage scaling on communication links for reducing power consumptionLi, F. / Chen, G. / Kandemir, M. et al. | 2005
- 461
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Session 5D - Biochips and DNA-Based nanofabrication| 2005
- 463
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5D.1 Design Automation Issues for Biofluidic MicrochipsMukherjee, T. / IEEE / Association for Computing Machinery et al. | 2005
- 463
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Design automation issues for biofluidic microchipsMukherjee, T. et al. | 2005
- 471
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5D.2 Design of DNA OrigamiRothemund, P. W. K. / IEEE / Association for Computing Machinery et al. | 2005
- 471
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Design of DNA origamiRothemund, P.W.K. et al. | 2005
- 479
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Kauffman networks: analysis and applicationsDubrova, E. / Teslenko, M. / Martinelli, A. et al. | 2005
- 479
-
5D.3 Kauffman Networks: Analysis and ApplicationsDubrova, E. V. / Teslenko, M. / Martinelli, A. / IEEE / Association for Computing Machinery et al. | 2005
- 485
-
Session 6A - Efficient simulation and synthesis methodologies for analog circuits| 2005
- 487
-
6A.1 Parameterized Model Order Reduction For Nonlinear Dynamical SystemsBond, B. / Daniel, L. / IEEE / Association for Computing Machinery et al. | 2005
- 487
-
Parameterized model order reduction of nonlinear dynamical systemsBond, B. / Daniel, L. et al. | 2005
- 495
-
Fast-yet-accurate PVT simulation by combined direct and iterative methodsBo Hu, / Shi, C.-J.R. et al. | 2005
- 495
-
6A.2 Fast-Yet-Accurate PVT Simulation by Combined Direct and Iterative MethodsShi, C. J. R. / Hu, B. / IEEE / Association for Computing Machinery et al. | 2005
- 502
-
6A.3 Robust Automated Synthesis Methodology for Integrated Spiral Inductors with VariabilityNieuwoudt, A. B. / Massoud, Y. / IEEE / Association for Computing Machinery et al. | 2005
- 502
-
Expression of Concern: Robust automated synthesis methodology for integrated spiral inductors with variabilityNieuwoudt, A. / Massoud, Y. et al. | 2005
- 509
-
Session 6B - Technology mapping and timing analysis| 2005
- 511
-
6B.1 Statistical Technology Mapping for Parametric YieldSingh, A. K. / Mani, M. / Orshansky, M. / IEEE / Association for Computing Machinery et al. | 2005
- 511
-
Statistical technology mapping for parametric yieldSingh, A.K. / Mani, M. / Orshansky, M. et al. | 2005
- 519
-
Reducing structural bias in technology mappingChatterjee, S. / Mishchenko, A. / Brayton, R. / Wang, X. / Kam, T. et al. | 2005
- 519
-
6B.2 Reducing Structural Bias in Technology MappingChatterjee, S. / Mishchenko, A. / Brayton, R. / Wang, X. / Kam, T. / IEEE / Association for Computing Machinery et al. | 2005
- 527
-
Improving the efficiency of static timing analysis with false pathsShuo Zhou, / Bo Yao, / Hongyu Chen, / Yi Zhu, / Chung-Kuan Cheng, / Hutton, M. / Collins, T. / Srinivasan, S. / Chou, N. / Suaris, P. et al. | 2005
- 527
-
6B.3 Improving the Efficiency of Static Timing Analysis with False PathsZhou, S. / Yao, B. / Chen, H. / Cheng, C. / Hutton, M. / Collins, T. / Srinivasan, S. / Chou, N. / Suaris, P. / IEEE et al. | 2005
- 533
-
Session 6C - Power aware system architecture and software optimizations| 2005
- 535
-
Total power-optimal pipelining and parallel processing under process variations in nanometer technologyNam Sung Kim, / Taeho Kgil, / Bowman, K. / De, V. / Mudge, T. et al. | 2005
- 535
-
6C.1 Total Power-Optimal Pipelining and Parallel Processing Process Variations in Nanometer TechnologyKim, N. S. / Kgil, T. / Bowman, K. / De, V. / Mudge, T. / IEEE / Association for Computing Machinery et al. | 2005
- 541
-
6C.2 Serial-Link Bus: A Low-Power On-Chip Bus ArchitectureGhoneima, M. M. / Khellah, M. / Tschanz, J. / Ismail, Y. / De, V. / IEEE / Association for Computing Machinery et al. | 2005
- 541
-
Serial-link bus: a low-power on-chip bus architectureGhoneima, M. / Ismail, Y. / Khellah, M. / Tschanz, J. / De, V. et al. | 2005
- 547
-
6C.3 New Decompilation Techniques for Binary-level Co-processor GenerationStitt, G. / Vahid, F. / IEEE / Association for Computing Machinery et al. | 2005
- 547
-
New decompilation techniques for binary-level co-processor generationStiff, G. / Vahid, F. et al. | 2005
- 555
-
Session 6D - Cellular array architectures| 2005
- 557
-
6D.1 Cellular Wave Computers and CNN Technology - An SoC architecture with xK Processors and SensorsRoska, T. / IEEE / Association for Computing Machinery et al. | 2005
- 557
-
Cellular wave computers and CNN technology - a SoC architecture with xK processors and sensor arraysRoska, T. et al. | 2005
- 565
-
Eliminating wire crossings for molecular quantum-dot cellular automata implementationChaudhary, A. / Chen, D.Z. / Xiaobo Sharon Hu, / Whitton, K. / Niemier, M. / Ravichandran, R. et al. | 2005
- 565
-
6D.2 Eliminating Wire Crossings for Molecular Quantum-dot Cellular Automata ImplementationChaudhary, A. / Chen, D. / Hu, X. S. / Niemier, M. T. / Ravichandran, R. / Whitton, K. / IEEE / Association for Computing Machinery et al. | 2005
- 573
-
Session 7A - Variability aware clocking| 2005
- 575
-
Statistical timing analysis driven post-silicon-tunable clock-tree synthesisJeng-Liang Tsai, / Lizheng Zhang, / Charlie Chung-Ping Chen, et al. | 2005
- 575
-
7A.1 Statistical Timing Analysis Driven Post-Silicon-Tunable Clock-Tree SynthesisTsai, J. / Zhang, L. / Chen, C. / IEEE / Association for Computing Machinery et al. | 2005
- 582
-
TACO: temperature aware clock-tree optimizationMinsik Cho, / Ahmedtt, S. / Pan, D.Z. et al. | 2005
- 582
-
7A.2 TACO: Temperature Aware Clock Tree OptimizationCho, M. / Ahmed, S. / Pan, D. Z. / IEEE / Association for Computing Machinery et al. | 2005
- 588
-
Statistical based link insertion for robust clock network designLam, W.-C.D. / Jam, J. / Koh, C.-K. / Balakrishnan, V. / Chen, Y. et al. | 2005
- 588
-
7A.3 Statistical Based Link Insertion for Robust Clock Network DesignLam, D. / Koh, C. K. / Chen, Y. / Jain, J. / Balakrishnan, V. / IEEE / Association for Computing Machinery et al. | 2005
- 592
-
7A.4 Practical Techniques for Minimizing Skew and Its Variation in Buffered Clock NetworksVenkataraman, G. / Jayakumar, N. / Hu, J. / Li, P. / khatri, S. / Rajaram, A. / Alpert, C. / McGuinness, P. / IEEE / Association for Computing Machinery et al. | 2005
- 592
-
Practical techniques to reduce skew and its variations in buffered clock networksVenkataraman, G. / Jayakumar, N. / Hu, J. / Li, P. / Sunil Khatri, / Anand Rajaram, / McGuinness, P. / Alpert, C. et al. | 2005
- 597
-
Session 7B - Oscillator analysis| 2005
- 599
-
An efficient and robust technique for tracking amplitude and frequency envelopes in oscillatorsTing Mei, / Roychowdhury, J. et al. | 2005
- 599
-
7B.1 An Efficient and Robust Technique for Tracking Amplitude and Frequency Envelopes in OscillatorsMei, T. / Roychowdhury, J. / IEEE / Association for Computing Machinery et al. | 2005
- 604
-
Oscillator-AC: restoring rigour to linearized small-signal analysis of oscillatorsTing Mei, / Roychowdhury, J. et al. | 2005
- 604
-
7B.2 Oscillator-AC: Restoring Rigour to Linearized Small-Signal Analysis of OscillatorsMei, T. / Roychowdhury, J. / IEEE / Association for Computing Machinery et al. | 2005
- 610
-
7B.3 A Multi-Harmonic Probe Technique for Computing Oscillator Steady StatesBoianapally, K. D. / Roychowdhury, J. / Mei, T. / IEEE / Association for Computing Machinery et al. | 2005
- 610
-
A multi-harmonic probe technique for computing oscillator steady statesBoianapally, K.D. / Ting Mei, / Roychowdhury, J. et al. | 2005
- 614
-
An efficient and accurate algorithm for autonomous envelope following with applications| 2005
- 614
-
7B.4S An Efficient and Accurate Algorithm for Autonomous Envelope Following with ApplicationsZhang, T. / Feng, D. / IEEE / Association for Computing Machinery et al. | 2005
- 618
-
7B.5S Steady-State Analysis of Voltage and Current Controlled OscillatorsMehrotra, A. / Lu, S. / Lee, D. C. / Narayan, A. / IEEE / Association for Computing Machinery et al. | 2005
- 618
-
Steady-state analysis of voltage and current controlled oscillatorsMehrotra, A. / Suihua Lu, / Lee, D.C. / Narayan, A. et al. | 2005
- 625
-
Session 7C - Power noise and thermal issues| 2005
- 627
-
7C.1 Timing-Aware Power Noise Reduction in LayoutYeh, C. Y. / Sadowska, M. M. / IEEE / Association for Computing Machinery et al. | 2005
- 627
-
Timing-aware power noise reduction in layoutChao-Yang Yeh, / Marek-Sadowska, M. et al. | 2005
- 635
-
A high efficiency full-chip thermal simulation algorithmYong Zhan, / Sapatnekar, S.S. et al. | 2005
- 635
-
7C.2 High Efficiency Full-Chip Thermal Simulation AlgorithmZhan, Y. / Sapatnekar, S. S. / IEEE / Association for Computing Machinery et al. | 2005
- 639
-
7C.3 Fast Thermal Simulation for Architecture Level Dynamic Thermal ManagementLiu, P. / Li, H. / Jin, L. / Wu, W. / Tan, S. / Yang, J. / Qi, Z. / IEEE / Association for Computing Machinery et al. | 2005
- 639
-
Fast thermal simulation for architecture level dynamic thermal managementPu Liu, / Zhenyu Qi, / Hang Li, / Lingling Jin, / Wei Wu, / Tan, S.X.-D. / Jun Yang, et al. | 2005
- 645
-
7C.4 Variational Analysis of Large Power Grids by Exploring Statistical Sampling Sharing and Spatial LocalityLi, P. / IEEE / Association for Computing Machinery et al. | 2005
- 645
-
Variational analysis of large power grids by exploring statistical sampling sharing and spatial localityPeng Li, et al. | 2005
- 653
-
Session 7D - Nanocomputing| 2005
- 655
-
The impact of the nanoscale on computing systemsGoldstein, S.C. et al. | 2005
- 655
-
7D.1 The Impact of the Nanoscale on Computing SystemsGoldstein, S. / IEEE / Association for Computing Machinery et al. | 2005
- 662
-
Computer-aided design for DNA self-assembly: process and applicationsDwyer, C. et al. | 2005
- 662
-
7D.2 Computer-Aided Design for DNA Self-Assembly: Process and ApplicationsDwyer, C. / IEEE / Association for Computing Machinery et al. | 2005
- 668
-
A mapping algorithm for defect-tolerance of reconfigurable nano-architecturesTahoori, M.B. et al. | 2005
- 668
-
7D.3 A Mapping Algorithm for Defect-Tolerance of Reconfigurable Nano-ArchitecturesTahoori, M. B. / IEEE / Association for Computing Machinery et al. | 2005
- 673
-
Session 8A - Extraction and modeling for interconnect structures| 2005
- 675
-
8A.1 FastSies: A Fast Stochastic Integral Equation Solver for Modeling the Rough Surface EffectZhu, Z. / White, J. K. / IEEE / Association for Computing Machinery et al. | 2005
- 675
-
FastSies: a fast stochastic integral equation solver for modeling the rough surface effectZhenhai Zhu, / White, J. et al. | 2005
- 683
-
8A.2 Efficient Statistical Capacitance Variability Modeling with Orthogonal Principle Factor AnalysisJiang, R. / Fu, W. / Chen, C. C. P. / Lin, V. / Wang, J. / IEEE / Association for Computing Machinery et al. | 2005
- 683
-
Efficient statistical capacitance variability modeling with orthogonal principle factor analysisRong Jiang, / Wenyin Fu, / Wang, J.M. / Lin, V. / Chen, C.C.-P. et al. | 2005
- 691
-
Expression of Concern: Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductanceMondal, M. / Massoud, Y. et al. | 2005
- 691
-
8A.3 Reducing Pessimism in RLC Delay Estimation Using an Accurate Analytical Frequency Dependent Model for InductanceMondal, M. / Massoud, Y. / IEEE / Association for Computing Machinery et al. | 2005
- 697
-
Session 8B - Timing and power optimization| 2005
- 699
-
8B.1 Statistical Critical Path Analysis Considering CorrelationsZhan, Y. / Strojwas, A. J. / Sharma, M. / Newmark, D. / IEEE / Association for Computing Machinery et al. | 2005
- 699
-
Statistical critical path analysis considering correlationsYaping Zhan, / Strojwas, A.J. / Sharma, M. / Newmark, D. et al. | 2005
- 705
-
8B.2 Discrete Vt Assignment and Gate Sizing Using a Self-Snapping Continuous FormulationShah, S. / Srivastava, A. / Sharma, D. / Zolotov, V. / Sylvester, D. / Blaauw, D. / IEEE / Association for Computing Machinery et al. | 2005
- 705
-
Discrete Vt assignment and gate sizing using a self-snapping continuous formulationShah, S. / Srivastava, A. / Sharma, D. / Sylvester, D. / Blaauw, D. / Zolotov, V. et al. | 2005
- 713
-
8B.3 Formalizing Designer's Preferences for Multiattribute Optimization with Application to Leakage-Delay TradeoffsBhardwaj, S. / Vrudhula, S. / IEEE / Association for Computing Machinery et al. | 2005
- 713
-
Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffsSarvesh Bhardwaj, / Sarma Vrudhula, et al. | 2005
- 719
-
Session 8C - System-level variability modeling| 2005
- 721
-
Projection-based performance modeling for inter/intra-die variationsXin Li, / Jiayong Le, / Pileggi, L.T. / Strojwas, A. et al. | 2005
- 721
-
8C.1 Projection-Based Performance Modeling for Inter/Intra-Die VariationsLi, X. / Le, J. / Pileggi, L. T. / Strojwas, A. / IEEE / Association for Computing Machinery et al. | 2005
- 728
-
System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS)Wang, J.M. / Srinivas, B. / Dongsheng Ma, / Chen, C.C.-P. / Jun Li, et al. | 2005
- 728
-
8C.2 System-Level Power and Thermal Modeling by Orthogonal Polynomial based Response Surface Approach (OPRS)Wang, J. M. / Srinivas, B. / Ma, D. / Chen, C. C.-P. / Li, J. / IEEE / Association for Computing Machinery et al. | 2005
- 736
-
8C.3 Accurate Estimation and Modeling of Total Chip Leakage Considering Inter- and Intra-Die Process VariationsAgarwal, A. / Kang, K. / Roy, K. / IEEE / Association for Computing Machinery et al. | 2005
- 736
-
Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variationsAgarwal, A. / Kunhyuk Kang, / Roy, K. et al. | 2005
- 743
-
Session 8D - Routing [breaker page]| 2005
- 745
-
8D.1 Thermal Via Planning for 3-D ICsCong, J. / Zhang, Y. / IEEE / Association for Computing Machinery et al. | 2005
- 745
-
Thermal via planning for 3-D ICsCong, J. / Yan Zhang, et al. | 2005
- 753
-
A routing algorithm for flip-chip designJia-Wei Fang, / I-Jye Lin, / Ping-Hung Yuh, / Yao-Wen Chang, / Jyh-Herng Wang, et al. | 2005
- 753
-
8D.2 A Routing Algorithm for Flip-Chip DesignFang, J.-W. / Lin, I.-J. / Yuh, P.-H. / Chang, Y.-W. / Wang, J.-H. / IEEE / Association for Computing Machinery et al. | 2005
- 759
-
An escape routing framework for dense boards with high-speed design constraintsOzdal, M.M. / Wong, M.D.F. / Honsinger, P.S. et al. | 2005
- 759
-
8D.3S An Escape Routing Framework for Dense Boards with High-Speed Design ConstraintsOzdal, M. M. / Wong, M. D. F. / Honsinger, P. / IEEE / Association for Computing Machinery et al. | 2005
- 767
-
Optimal routing algorithms for pin clusters in high-density multichip modulesOzdal, M.M. / Wong, M.D.F. / Honsinger, P.S. et al. | 2005
- 767
-
8D.4S Optimal Routing Algorithms for Pin Clusters in High-Density Multichip ModulesOzdal, M. M. / Wong, M. D. F. / Honsinger, P. / IEEE / Association for Computing Machinery et al. | 2005
- 775
-
Session 9A - New frontiers in high-level synthesis| 2005
- 777
-
9A.1 Weighted Control SchedulingVijayakumar, A. / Brewer, F. D. / IEEE / Association for Computing Machinery et al. | 2005
- 777
-
Weighted control schedulingAravind Vijayakumar, / Brewer, F. et al. | 2005
- 784
-
9A.2 Hardware Synthesis from Guarded Atomic Actions with Performance SpecificationsRosenband, D. L. / Arvind / IEEE / Association for Computing Machinery et al. | 2005
- 784
-
Hardware synthesis from guarded atomic actions with performance specificationsRosenband, D.L. / Arvind, et al. | 2005
- 792
-
9A.3S Fast Timing Closure by Interconnect Criticality Driven Delay RelaxationSinghal, L. / Bozorgzadeh, E. / IEEE / Association for Computing Machinery et al. | 2005
- 792
-
Fast timing closure by interconnect criticality driven delay relaxationSinghal, L. / Bozorgzadeh, E. et al. | 2005
- 799
-
Sesison 9B - Advances in model order reduction approaches| 2005
- 801
-
9B.1 Fast Balanced Stochastic Truncation Via A Quadratic Extension of the Alternating Direction Implicit IterationWong, N. / Balakrishnan, V. / IEEE / Association for Computing Machinery et al. | 2005
- 801
-
Fast balanced stochastic truncation via a quadratic extension of the alternating direction implicit iterationNgai Wong, / Balakrishnan, V. et al. | 2005
- 806
-
9B.2 Parameterized Interconnect Order Reduction with Explicit-and-Implicit Multi-Parameter Moment Matching for Inter/Intra-Die VariationsLi, X. / Li, P. / Pileggi, L. T. / IEEE / Association for Computing Machinery et al. | 2005
- 806
-
Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variationsXin Li, / Peng Li, / Pileggi, L.T. et al. | 2005
- 813
-
9B.3 A More Reliable Reduction Algorithm for Behavioral Model ExtractionVasilyev, D. G. / White, J. K. / IEEE / Association for Computing Machinery et al. | 2005
- 813
-
A more reliable reduction algorithm for behavioral model extractionVasilyev, D. / White, J. et al. | 2005
- 821
-
9B.4 An Efficient Method for Terminal Reduction of Interconnect Circuits Considering Delay VariationsLiu, P. / Sheldon, T. / Li, H. / Qi, Z. / Kong, J. / McGaughy, B. / He, L. / IEEE / Association for Computing Machinery et al. | 2005
- 821
-
An efficient method for terminal reduction of interconnect circuits considering delay variationsPu Liu, / Tan, S.X.-D. / Hang Li, / Zhenyu Qi, / Jun Kong, / McGaughy, B. / Lei He, et al. | 2005
- 827
-
Session 9C - Statistical timing analysis| 2005
- 829
-
Statistical timing analysis with two-sided constraintsHeloue, K.R. / Najm, F.N. et al. | 2005
- 829
-
9C.1 Statistical Timing Analysis With Two-sided ConstraintsHeloue, K. R. / Najm, F. N. / IEEE / Association for Computing Machinery et al. | 2005
- 837
-
A unified framework for statistical timing analysis with coupling and multiple input switchingSinha, D. / Hai Zhou, et al. | 2005
- 837
-
9C.2 An Unified Framework for Statistical Timing Analysis With Coupling and Multiple Input SwitchingSinha, D. / Zhou, H. / IEEE / Association for Computing Machinery et al. | 2005
- 844
-
9C.3 Defining Statistical Sensitivity for Timing Optimization of Logic Circuits With Large-Scale Process and Environmental VariationsLi, X. / Le, J. / Celik, M. / Pileggi, L. T. / IEEE / Association for Computing Machinery et al. | 2005
- 844
-
Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variationsXin Li, / Jiayong Le, / Mustafa Celik, / Pileggi, L.T. et al. | 2005
- 853
-
Session 9D - Problem structure in formal verification| 2005
- 855
-
Verification of executable pipelined machines with bit-level interfacesManolios, P. / Srinivasan, S.K. et al. | 2005
- 855
-
9D.1 Verification of Executable Pipelined Machines with Bit-Level InterfacesManolios, P. / Srinivasan, S. K. / IEEE / Association for Computing Machinery et al. | 2005
- 863
-
A complete compositional reasoning framework for the efficient verification of pipelined machinesManolios, P. / Srinivasan, S.K. et al. | 2005
- 863
-
9D.2 A Complete Compositional Reasoning Framework for the Efficient Verification of Pipelined MachinesManolios, P. / Srinivasan, S. K. / IEEE / Association for Computing Machinery et al. | 2005
- 871
-
Post-verification debugging of hierarchical designsAli, M.F. / Safarpour, S. / Veneris, A. / Abadir, M.S. / Drechsler, R. et al. | 2005
- 871
-
9D.3 Post-Verification Debugging of Hierarchical DesignsAli, M. F. / Safarpour, S. / Veneris, A. / Abadir, M. S. / Drechsler, R. / IEEE / Association for Computing Machinery et al. | 2005
- 877
-
Efficient LTL compilation for SAT-based model checkingArmoni, R. / Egorov, S. / Fraer, R. / Korchemny, D. / Vardi, M.Y. et al. | 2005
- 877
-
9D.4 Efficient LTL Compilation for SAT-based Model CheckingArmoni, R. / Egorov, S. V. / Fraer, R. / Korchemny, D. / Vardi, M. Y. / IEEE / Association for Computing Machinery et al. | 2005
- 885
-
9D.5 SAT based solutions for Consistency Problems in Formal Property Specifications for Open SystemsRoy, S. / Das, S. / Basu, P. / Dasgupta, P. / Chakrabarti, P. P. / IEEE / Association for Computing Machinery et al. | 2005
- 885
-
SAT based solutions for consistency problems in formal property specifications for open systemsSuchismita Roy, / Sayantan Das, / Prasenjit Basu, / Pallab Dasgupta, / Chakrabarti, P.P. et al. | 2005
- 889
-
Session 10A - Analytical placement| 2005
- 891
-
10A.1 Architecture and Details of a High Quality, Large-Scale Analytical PlacerKahng, A. B. / Reda, S. / Wang, Q. / IEEE / Association for Computing Machinery et al. | 2005
- 891
-
Architecture and details of a high quality, large-scale analytical placerKahng, A.B. / Reda, S. / Qinke Wang, et al. | 2005
- 899
-
10A.2 Mixed-Size Placement via Line SearchVorwerk, K. / Kennings, A. / IEEE / Association for Computing Machinery et al. | 2005
- 899
-
Mixed-size placement via line searchVorwerk, K. / Kennings, A. et al. | 2005
- 905
-
10A.3 A Hybrid Linear Equation Solver and its Application in Quadratic PlacementQian, H. / Sapatnekar, S. S. / IEEE / Association for Computing Machinery et al. | 2005
- 905
-
A hybrid linear equation solver and its application in quadratic placementHaifeng Qian, / Sapatnekar, S.S. et al. | 2005
- 911
-
Session 10B - Embedded tutorial: hardware and software design of energy efficient sensor platforms| 2005
- 913
-
10B.1 Energy-Efficient Platform Designs for Real-World Wireless Sensing ApplicationsChou, P. H. / Park, C. / IEEE / Association for Computing Machinery et al. | 2005
- 913
-
Energy-efficient platform designs for real-world wireless sensing applicationsChou, P.H. / Chulsung Park, et al. | 2005
- 921
-
10B.2 Power-Aware Microsensor DesignSchott, B. / Bajura, M. / IEEE / Association for Computing Machinery et al. | 2005
- 921
-
Power-aware microsensor designSchott, B. / Bajura, M. et al. | 2005
- 925
-
10B.3 System Software Techniques for Low-Power Operation in Wireless Sensor NetworksCuller, D. E. / Dutta, P. K. / IEEE / Association for Computing Machinery et al. | 2005
- 925
-
System software techniques for low-power operation in wireless sensor networksDutta, P.K. / Culler, D.E. et al. | 2005
- 933
-
Session 10C - Improving the accuracy of static timing analysis| 2005
- 935
-
10C.1S Expanding the Frequency Range of AWE via Time ShiftingShebaita, A. M. / Amin, C. S. / Dartu, F. / Ismail, Y. / IEEE / Association for Computing Machinery et al. | 2005
- 935
-
Expanding the frequency range of AWE via time shiftingShebaita, A. / Amin, C. / Dartu, F. / Ismail, Y. et al. | 2005
- 939
-
A sliding window scheme for accurate clock mesh analysisChen, H. / Yeh, C. / Wilke, G. / Reddy, S. / Nguyen, H. / Walker, W. / Murgai, R. et al. | 2005
- 939
-
10C.2S A Sliding Window Scheme for Accurate Clock Mesh AnalysisChen, H. / Yeh, C. Y. / Reddy, S. M. / Wilke, G. / Van Nguyen, H. / Walker, W. W. / Murgai, R. / IEEE / Association for Computing Machinery et al. | 2005
- 947
-
Accurate delay computation for noisy waveform shapesJain, A. / Blaauw, D. / Zolotov, V. et al. | 2005
- 947
-
10C.3 Accurate Delay Computation for Noisy Waveform ShapesJain, A. / Zolotov, V. / Blaauw, D. / IEEE / Association for Computing Machinery et al. | 2005
- 954
-
10C.4 Pessimism Reduction in Crosstalk Noise Aware STABecer, M. R. / Zolotov, V. / Panda, R. / Grinshpon, A. / Algor, I. / Levy, R. / Oh, C. / IEEE / Association for Computing Machinery et al. | 2005
- 954
-
Pessimism reduction in crosstalk noise aware STABecer, M. / Zolotov, V. / Panda, R. / Grinshpon, A. / Algol, I. / Levy, R. / Oh, C. et al. | 2005
- 963
-
Session 10D - Embedded tutorial : formal eguivalence checking between system-level models and RTL| 2005
- 965
-
Embedded tutorial: formal equivalence checking between system-level models and RTLKoelbl, A. / Yuan Lu, / Mathur, A. et al. | 2005
- 965
-
10D.1 Formal equivalence checking between system-level models and RTLKoebel, A. / Lu, Y. / Mathur, A. / IEEE / Association for Computing Machinery et al. | 2005
- 973
-
Session 11A - Embedded tutorial: emergent communication| 2005
- 975
-
CDMA/FDMA-interconnects for future ULSI communicationsChang, M.F. et al. | 2005
- 975
-
11A.1 CDMA/FDMA-Interconnects for Future ULSI CommunicationsChang, F. / IEEE / Association for Computing Machinery et al. | 2005
- 979
-
11A.2 The Feasibility of On-Chip Interconnection Using AntennasKen, O. / Kim, K. / Floyd, B. / Mehta, J. / Yoon, H. / Hung, C. M. / Bravo, D. / Dickson, T. / Guo, X. / Li, R. et al. | 2005
- 985
-
Global signaling over lossy transmission linesFlynn, M.P. / Kang, J.J. et al. | 2005
- 985
-
11A.3 Global Signaling Over Lossy Transmission LinesFlynn, M. P. / Kang, J. J. / IEEE / Association for Computing Machinery et al. | 2005
- 993
-
Session 11B - Addressing emerging challenges for SoCs| 2005
- 995
-
11B.1 A Cache-Defect-Aware Code Placement Algorithm for Improving the Performance of ProcessorsIshihara, T. / Fallah, F. / IEEE / Association for Computing Machinery et al. | 2005
- 995
-
A cache-defect-aware code placement algorithm for improving the performance of processorsIshihara, T. / Fallah, F. et al. | 2005
- 1002
-
11B.2 Improving Scratch-Pad Memory Reliability Through Compiler-Guided Data Block DuplicationLi, F. / Chen, G. / Kandemir, M. / Kolcu, I. / IEEE / Association for Computing Machinery et al. | 2005
- 1002
-
Improving scratch-pad memory reliability through compiler-guided data block duplicationLi, F. / Chen, G. / Kandemir, M. / Kolcu, I. et al. | 2005
- 1006
-
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systemsAgiwal, A. / Singh, M. et al. | 2005
- 1006
-
11B.3 Multi-Clock Latency-Insensitive Architecture and Wrapper SynthesisAgiwal, A. / Singh, M. / IEEE / Association for Computing Machinery et al. | 2005
- 1014
-
11B.4 Memory Access Optimization of Dynamic Binary Translation for Reconfigurable ArchitecturesOh, S. / Kim, T. G. / IEEE / Association for Computing Machinery et al. | 2005
- 1014
-
Memory access optimization of dynamic binary translation for reconfigurable architecturesSe Jong Oh, / Tag Gon Kim, et al. | 2005
- 1021
-
Session 11C - Statistical optimization| 2005
- 1023
-
11C.1 Parametric Yield Maximization using Gate Sizing based on Efficient Statistical Power and Delay Gradient ComputationChopra, K. / Shah, S. / Srivastav, A. / Sylvester, D. / Blaauw, D. / IEEE / Association for Computing Machinery et al. | 2005
- 1023
-
Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computationChopra, K. / Shah, S. / Srivastava, A. / Blaauw, D. / Sylvester, D. et al. | 2005
- 1029
-
Gate sizing using incremental parameterized statistical timing analysisGuthaus, M.R. / Venkateswarant, N. / Visweswariaht, C. / Zolotov, V. et al. | 2005
- 1029
-
11C.2 Gate Sizing using Incremental Parameterized Statistical Timing AnalysisGuthaus, M. R. / Venkateswaran, N. / Visweswariah, C. / Zolotov, V. / IEEE / Association for Computing Machinery et al. | 2005
- 1037
-
11C.3 Timing Yield Driven Statistical Gate Sizing OptimizationSinha, D. / Shenoy, N. V. / Zhou, H. / IEEE / Association for Computing Machinery et al. | 2005
- 1037
-
Statistical gate sizing for timing yield optimizationSinha, D. / Shenoy, N.V. / Hai Zhou, et al. | 2005
- 1043
-
Session 11D - Making model checking practical| 2005
- 1045
-
Simulation-based bug trace minimization with BMC-based refinementKai-hui Chang, / Bertacco, V. / Markov, I.L. et al. | 2005
- 1045
-
11D.1 Simulation-based Bug Trace Minimization with BMC-based RefinementChang, K. / Bertacco, V. / Markov, I. L. / IEEE / Association for Computing Machinery et al. | 2005
- 1052
-
11D.2 Complementary Use of Runtime Validation and Model CheckingBayazit, A. A. / Malik, S. / IEEE / Association for Computing Machinery et al. | 2005
- 1052
-
Complementary use of runtime validation and model checkingBayazit, A.A. / Malik, S. et al. | 2005
- 1060
-
11D.3 Scalable Compositional Minimization via Static AnalysisZaraket, F. A. / Baumgartner, J. / Aziz, A. / IEEE / Association for Computing Machinery et al. | 2005
- 1060
-
Scalable compositional minimization via static analysisZaraket, F. / Baumgartner, J. / Aziz, A. et al. | 2005
- 1068
-
11D.4 Transition-by-Transition FSM Traversal for Reachability Analysis in Bounded Model CheckingNguyen, M. D. / Stoffel, D. A. / Kunz, W. / Wedler, M. / IEEE / Association for Computing Machinery et al. | 2005
- 1068
-
Transition-by-transition FSM traversal for reachability analysis in bounded model checkingNguyen, M.D. / Stoffel, D. / Wedler, M. / Kunz, W. et al. | 2005
- 1076
-
Automatic generalized phase abstraction for formal verificationBjesse, P. / Kukula, J. et al. | 2005
- 1076
-
11D.5 Automatic Phase Abstraction for Formal VerificationBjesse, P. / Kukula, J. / IEEE / Association for Computing Machinery et al. | 2005
- 1083
-
Author index| 2005
- xix
-
Table of contents| 2005
-
ICCAD-2005 International Conference on Computer Aided Design (IEEE Cat. No. 05CH37700)| 2005