2015 International Conference on Reconfigurable Computing and FPGAs (ReConFig15) : Cancun, Mexico, December 8-10, 2014 (English)
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2015
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ISBN:
- Conference Proceedings / Electronic Resource
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Title:2015 International Conference on Reconfigurable Computing and FPGAs (ReConFig15) : Cancun, Mexico, December 8-10, 2014
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Contributors:Hübner, Michael ( editor ) / Gokhale, Maya ( editor ) / Cumplido, René ( editor ) / International Conference on ReConFigurable Computing and FPGAs ( author ) / Instituto Nacional de Astrofísica, Optica y Electrónica, Mexiko ( organizer ) / Lawrence Livermore National Laboratory ( organizer ) / Ruhr-Universität Bochum ( organizer )
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Conference:International Conference on Reconfigurable Computing and FPGAs ; 2015 ; Cancun
ReConFig ; 2015 ; Cancun -
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Place of publication:Piscataway, NJ
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Publication date:2015
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Size:1 Online-Ressource
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Remarks:Illustrationen
"During December 7th, 8th and 9th, 2015" - Vorwort. - Datum der Konferenz im Titelzusatz fälschlich als "December 8-10, 2014" angegeben
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ISBN:
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Type of media:Conference Proceedings
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Type of material:Electronic Resource
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Language:English
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Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
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Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAsRodrıguez, Alfonso / Valverde, Juan / de la Torre, Eduardo et al. | 2015
- 1
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Design and synthesis of reconfigurable control-flow structures for CGRARakossy, Zoltan Endre / Acosta-Aponte, Axel / Noll, Tobias G. / Ascheid, Gerd / Leupers, Rainer / Chattopadhyay, Anupam et al. | 2015
- 1
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Improving FPGA NoC performance using virtual cut-through switching techniqueMaidee, Pongstorn / Kaviani, Alireza et al. | 2015
- 1
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Keynote 1 - From data to information to flowMencer, Oskar et al. | 2015
- 1
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Organizing committee| 2015
- 1
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Technical demonstrations session| 2015
- 1
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Towards a reconfigurable distributed testbed to enable advanced research and development of timing and synchronization in cyber-physical systemsAndrade, Hugo A. / Derler, Patricia / Eidson, John C. / Li-Baboud, Ya-Shian / Shrivastava, Aviral / Stanton, Kevin / Weiss, Marc et al. | 2015
- 1
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Resource-saving compile flow for coarse-grained reconfigurable architecturesZhao, Zhongyuan / Sheng, Weiguang / Jing, Naifeng / He, Weifeng / Mao, Zhigang et al. | 2015
- 1
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Explicitly isolating data and computation in high level synthesis: the role of polyhedral frameworkCattaneo, Riccardo / Pallotta, Gabriele / Sciuto, Donatella / Santambrogio, Marco D. et al. | 2015
- 1
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Exploiting the brownian bridge technique to improve longstaff-schwartz american option pricing on FPGA systemsVarela, Javier Alejandro / Brugger, Christian / Schryver, Christian De / Wehn, Norbert / Tang, Songyin / Omland, Steffen et al. | 2015
- 1
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Feasibility of high level compiler optimizations in online synthesisJung, Lukas Johannes / Hochberger, Christian et al. | 2015
- 1
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Large-scale high-dimensional nearest neighbor search using flash memory with in-store processingJun, Sang-Woo / Chung, Chanwoo / Arvind, et al. | 2015
- 1
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Multiple contexts in a multi-ported VLIW register file implementationHoozemans, Joost / Johansen, Jens / Straten, Jeroen Van / Brandon, Anthony / Wong, Stephan et al. | 2015
- 1
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Optimizing memory performance for FPGA implementation of pagerankZhou, Shijie / Chelmis, Charalampos / Prasanna, Viktor K. et al. | 2015
- 1
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Accelerating the construction of BRIEF descriptors using an FPGA-based architecturede Lima, Roberto / Martinez-Carranza, Jose / Morales-Reyes, Alicia / Cumplido, Rene et al. | 2015
- 1
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A universal hardware API for authenticated ciphersHomsirikamol, Ekawat / Diehl, William / Ferozpuri, Ahmed / Farahmand, Farnoud / Sharif, Malik Umar / Gaj, Kris et al. | 2015
- 1
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Designing customized ISA processors using high level synthesisSkalicky, Sam / Ananthanarayana, Tejaswini / Lopez, Sonia / Lukowiak, Marcin et al. | 2015
- 1
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Efficient and flexible NoC-based group communication for secure MPSoCsSepúlveda, Johanna / Flórez, Daniel / Gogniat, Guy et al. | 2015
- 1
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Floating point CORDIC-based architecture for powering computationMack, Joshua / Bellestri, Sam / Llamocca, Daniel et al. | 2015
- 1
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Power modelling for saving strategies in coarse grained reconfigurable systemsFanni, Tiziana / Sau, Carlo / Meloni, Paolo / Raffo, Luigi / Palumbo, Francesca et al. | 2015
- 1
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Additional reviewers| 2015
- 1
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Real-time pedestrian detection on a xilinx zynq using the HOG algorithmRettkowski, Jens / Boutros, Andrew / Göhringer, Diana et al. | 2015
- 1
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UT-OCL: an OpenCL framework for embedded systems using xilinx FPGAsMirian, Vincent / Chow, Paul et al. | 2015
- 1
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Archborn: an open source tool for automated generation of chip heterogeneous multiprocessor architecturesMa, Sen / Ding, Hongyuan / Huang, Miaoqing / Andrews, David et al. | 2015
- 1
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Design and exploration of routing methods for NoC-based multicore systemsBahrebar, Poona / Stroobandt, Dirk et al. | 2015
- 1
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Evaluating shared virtual memory in an OpenCL framework for embedded systems on FPGAsMirian, Vincent / Chow, Paul et al. | 2015
- 1
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FPGA-based visual control of robot manipulators using dynamic perceptibilityPérez, J. / Alabdo, A. / Garcia, G.J. / Pomares, J. / Torres, F. et al. | 2015
- 1
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Private circuits II versus fault injection attacksRakotomalala, Henitsoa / Ngo, Xuan Thuy / Najm, Zakaria / Danger, Jean-Luc / Guilley, Sylvain et al. | 2015
- 1
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Statistical performance of the ARM cortex A9 accelerator coherency port in the xilinx zynq SoC for real-time applicationsPowell, Andrew / Silage, Dennis et al. | 2015
- 1
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Using type transformations to generate program variants for FPGA design space explorationNabi, Syed Waqar / Vanderbauwhede, Wim et al. | 2015
- 1
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A real-time reconfigurable architecture for face detectionSuse, Viorel / Ionescu, Dan et al. | 2015
- 1
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An improved hardware design for matrix inverse based on systolic array QR decomposition and piecewise polynomial approximationSantos, L. Canche / Atoche, A. Castillo / Castilloy, J. Vazquez / Gandaraz, O. Longoria / Alvarez, R. Carrasco / Aguilar, J. Ortegon et al. | 2015
- 1
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An architectural template for composing application specific datapaths at runtimeBackasch, Rico / Hempel, Gerald / Blochwitz, Christopher / Werner, Stefan / Groppe, Sven / Pionteck, Thilo et al. | 2015
- 1
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G-DMA: improving memory access performance for hardware accelerated sparse graph computationBean, Andrew / Kapre, Nachiket / Cheung, Peter et al. | 2015
- 1
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High throughput sketch based online heavy change detection on FPGATong, Da / Prasanna, Viktor et al. | 2015
- 1
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A highly parallel AES-GCM core for authenticated encryption of 400 Gb/s network protocolsBuhrow, Benjamin / Fritz, Karl / Gilbert, Barry / Daniel, Erik et al. | 2015
- 1
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A hybrid design for high performance large-scale sorting on FPGASrivastava, Ajitesh / Chen, Ren / Prasanna, Viktor K. / Chelmis, Charalampos et al. | 2015
- 1
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MiCAP: a custom reconfiguration controller for dynamic circuit specializationKulkarni, Amit / Kizheppatt, Vipin / Stroobandt, Dirk et al. | 2015
- 1
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A run-length encoding co-processor for retinal image texture analysisBendaoudi, Hamza / Gan, Qifeng / Cheriet, Farida / Tahar, Houssem Ben / Langlois, J.M. Pierre et al. | 2015
- 1
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Shape exploration for modules in rapid assembly workflowsLee, Kevin / Athanas, Peter et al. | 2015
- 1
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Thoroughly analyzing the use of ring oscillators for on-chip hardware trojan detectionLecomte, Maxime / Fournier, Jacques J.A. / Maurine, Philippe et al. | 2015
- 1
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A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2Masuyama, Koichiro / Fujita, Yu / Okuhara, Hayate / Amano, Hideharu et al. | 2015
- 1
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Accurate in-situ runtime measurement of energy per operation of system-on-chip on FPGABhargav, Siddharth S. / Prabakar, Rishvanth K. / Cho, Young H. et al. | 2015
- 1
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An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databasesBlochwitz, Christopher / Joseph, Jan Moritz / Backasch, Rico / Pionteck, Thilo / Werner, Stefan / Heinrich, Dennis / Groppe, Sven et al. | 2015
- 1
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FPGA-based circular hough transform with graph clustering for vision-based multi-robot trackingIrwansyah, Arif / Ibraheem, Omar W. / Hagemeyer, Jens / Porrmann, Mario / Rueckert, Ulrich et al. | 2015
- 1
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A multiobjective reconfiguration-aware scheduler for FPGA-based heterogeneous architecturesDeiana, Enrico A. / Rabozzi, Marco / Cattaneo, Riccardo / Santambrogio, Marco D. et al. | 2015
- 1
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On how to efficiently accelerate brain network analysis on FPGA-based computing systemGnemmi, Giulia / Crippa, Mattia / Durelli, Gianluca / Cattaneo, Riccardo / Pallotta, Gabriele / Santambrogio, Marco D. et al. | 2015
- 1
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Keynote 2 – Towards datacenter computing with FPGAsGhiu, Gordon et al. | 2015
- 1
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Analysis of FPGA and software approaches to simulate unconventional computer architecturesGhasempour, Mohsen / Heathcote, Jonathan / Navaridas, Javier / Plana, Luis A. / Garside, Jim / Lujan, Mikel et al. | 2015
- 1
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FAUPU - A design framework for the development of programmable image processing architecturesReichenbach, Marc / Lieske, Tobias / Vaas, Steffen / Haublein, Konrad / Fey, Dietmar et al. | 2015
- 1
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A PCIe DMA engine to support the virtualization of 40 Gbps FPGA-accelerated network appliancesZazo, Jose Fernando / Lopez-Buedo, Sergio / Audzevich, Yury / Moore, Andrew W. et al. | 2015
- 1
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Polynomial multipliers for fully homomorphic encryption on FPGAJayet-Griffon, C. / Cornelie, M.-A. / Maistri, P. / Elbaz-Vincent, Ph. / Leveugle, R. et al. | 2015
- 1
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Adaptive controller using runtime partial hardware reconfiguration for unmanned aerial vehicles (UAVs)Thomas, Nikhil / Felder, Andrew / Bobda, Christophe et al. | 2015
- 1
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An efficient structure for run-time configuration of synthesis and channelizer filter banksKoehn, Thaddeus / Carrick, Matthew / Athanas, Peter et al. | 2015
- 1
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Exploring the energy consumption of lightweight blockciphers in FPGABanik, Subhadeep / Bogdanov, Andrey / Regazzoni, Francesco et al. | 2015
- 1
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FPGA-based acceleration of high density myoelectric signal processingBoschmann, Alexander / Agne, Andreas / Witschen, Linus / Thombansen, Georg / Kraus, Florian / Platzner, Marco et al. | 2015
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FPGA implementation of the EKF algorithm for localization in mobile robotics using a unified hardware module approachContreras, Luis / Cruz, Sergio / Motta, J.M.S.T. / Llanos, Carlos H. et al. | 2015
- 1
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FPGA based nodes for sub-microsecond synchronization of cyber-physical production systems on high availability ring networksAstarloa, Armando / Moreira, Naiara / Bidarte, Unai / Urbina, Marcelo / Modrono, David et al. | 2015
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openHMC - a configurable open-source hybrid memory cube controllerSchmidt, Juri / Bruning, Ulrich et al. | 2015
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The ReConFig 2015 Program Committee is proud to honor Alexander Boschmann, Andreas Agne, Linus Witschen, Georg Thombansen, Florian Kraus and Marco Platzner from University of Paderborn, Germany with the ReConFig 2015 Best New Applied Domain Paper Award| 2015
- 1
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Side channel attack on multiprecision multiplier used in protected ECDSA implementationVarchola, Michal / Drutarovsky, Milos / Repka, Marek / Zajac, Pavol et al. | 2015
- 1
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Achieving energy-efficiency on MPSoCs: performance and power optimizationsDing, Hongyuan / Huang, Miaoqing et al. | 2015
- 1
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Aging effects on ring-oscillator-based physical unclonable functions on FPGAsGehrer, Stefan / Leger, Sebastien / Sigl, Georg et al. | 2015
- 1
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Deeply hardware-entangled reconfigurable logic and interconnectErbagci, Burak / Bhargava, Mudit / Dondero, Rachel / Ma, Ken et al. | 2015
- 1
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Low latency solver for linear equation systems in floating point arithmeticDavid, Jean Pierre et al. | 2015
- 1
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Partial reconfiguration and specialized circuitry for flexible FPGA-based packet processingHager, Sven / Bendyk, Daniel / Scheuermann, Bjorn et al. | 2015
- 1
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Buffering strategies for ultra high-throughput stream processingKoehn, Thaddeus / Athanas, Peter et al. | 2015
- 1
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Exploiting hardware abstraction for hybrid parallel computing frameworkDing, Hongyuan / Huang, Miaoqing et al. | 2015
- 1
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Hardware isolation technique for IRC-based botnets detectionHategekimana, Festus / Tbatou, Adil / Bobda, Christophe / Kamhoua, Charles / Kwiat, Kevin et al. | 2015
- 1
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Technical program committees| 2015
- 1
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Scalable analytic placement for FPGA on GPGPUPattison, Ryan / Fobel, Christian / Grewal, Gary / Areibi, Shawki et al. | 2015
- 1
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Scalable modular hardware platform for FPGA based industrial radar flowmetersJaeschke, Timo / Imberg, Patrick / Zapke, Michael / Hubner, Michael / Pohl, Nils et al. | 2015
- 1
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A software configurable and parallelized coprocessor architecture for LQR controlZhang, Pei / Mills, Aaron / Zambreno, Joseph / Jones, Phillip H. et al. | 2015
- 1
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Using shadow pointers to trace C pointer values in FPGA circuitsMonson, Joshua S. / Hutchings, Brad et al. | 2015
- 1
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Accelerating all-pairs shortest path using a message-passing reconfigurable architectureAttia, Osama G. / Grieve, Alex / Townsend, Kevin R. / Jones, Phillip / Zambreno, Joseph et al. | 2015
- 1
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A resource-efficient multi-camera GigE vision IP core for embedded vision processing platformsIbraheem, Omar W. / Irwansyah, Arif / Hagemeyer, Jens / Porrmann, Mario / Rueckert, Ulrich et al. | 2015
- 1
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GIMME2 - an embedded system for stereo vision and processing of megapixel images with FPGA-accelerationAhlberg, Carl / Ekstrand, Fredrik / Ekstrom, Mikael / Spampinato, Giacomo / Asplund, Lars et al. | 2015
- 1
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Power measurements and analysis for dynamic circuit specializationKulkarni, Amit / Bonamy, Robin / Stroobandt, Dirk et al. | 2015
- 1
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Message from chairsGokhale, Maya / Huebner, Michael / Cumplido, René et al. | 2015
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Papers by track| 2015
- 1
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Runtime mapping and scheduling for energy efficiency in heterogeneous multi-core systemsSilva, Bruno / Delbem, Alexandre / Bonato, Vanderlei / Diniz, Pedro C. et al. | 2015
- 1
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Exploration of polynomial multiplication algorithms for homomorphic encryption schemesMigliore, Vincent / Real, Maria Mendez / Lapotre, Vianney / Tisserand, Arnaud / Fontaine, Caroline / Gogniat, Guy et al. | 2015
- 1
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Leveraging open source platforms and high-level synthesis for the design of FPGA-based 10 GbE active network probesRuizy, M. / Suttery, G. / Lopez-Buedo, S. / Ramosy, J. / Lopez de Vergara, J. E. / Aracil, J. et al. | 2015
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Reconfigurable coprocessors synthesis in the MPEG-RVC domainSau, Carlo / Fanni, Luca / Meloni, Paolo / Raffo, Luigi / Palumbo, Francesca et al. | 2015
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A sparse VLIW instruction encoding scheme compatible with generic binariesBrandon, Anthony / Hoozemans, Joost / van Straten, Jeroen / Lorenzon, Arthur / Sartor, Anderson / Schneider Beck, Antonio Carlos / Wong, Stephan et al. | 2015
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[Front cover]| 2015
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Copyright notice| 2015