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This paper describes a 16-bit x 16-bit multiplier for 2 two's complement binary numbers based on a new algorithm. This multiplier has been fabricated on an LSI chip using a standard n-E/D MOS process technology with a 2.7-micrometer design rule. This multiplier is characterized by use of a binary tree of redundant binary adders. In the new algorithm, n-bit multiplication is performed in a time proportional to log2n and the physical design of the multiplier is constructed of a regular cellular array. This new algorithm has been proposed by Takagi et al. The 16-bit x 16-bit multiplier chip size is 5.8 x 6.3 mm2 using the new layout for a binary adder tree. The chip contains about 10600 transistors, and the longest logic path includes 46 gates. The multiplication time was measured as 120 ns. We estimate that a 32-bit x 32-bit multiplication time is about 140 ns.