Defect analysis of patterned SOI material (English)
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In:
IEEE International SOI Conference, 1999
;
121-122
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1999
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ISBN:
- Conference paper / Print
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Title:Defect analysis of patterned SOI material
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Contributors:Bagchi, S. ( author ) / Yu, Y. ( author ) / Mendicino, M. ( author ) / Conner, J. ( author ) / Anderson, A. ( author ) / Prabhu, L. ( author ) / Tiner, M. ( author ) / Alles, M. ( author )
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Published in:IEEE International SOI Conference, 1999 ; 121-122
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Publisher:
- New search for: IEEE Operations Center
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Place of publication:Piscataway
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Publication date:1999
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Size:2 Seiten, 2 Quellen
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ISBN:
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DOI:
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Type of media:Conference paper
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Type of material:Print
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Language:English
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Keywords:Kristallfehler , Kristallmikrostruktur , Layout integrierter Schaltungen , integrierte Schaltung , integrierte Schaltungstechnologie , SIMOX-Technik , Transmissionselektronenmikroskopie , Schadenanalyse , SOI-Technik , Leckstrom , Wärmeleitfähigkeit , Schraubenversetzung , Silicium , Siliciumdioxid , Multichip-Modul , Transmissionselektronenmikroskop
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
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1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)| 1999
- 1
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Mainstreaming SOI TechnologyShahidi, G. / Ajmera, A. / Assaderaghi, F. / Bolam, R. / Bryant, A. / Coffey, M. / Hovel, H. / Lasky, J. / Leobandung, E. / Maloney, M. et al. | 1999
- 5
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Advanced Microelectronics - The Role of SOIRadack, D. / IEEE et al. | 1999
- 8
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Single Chip Wireless Systems Using SOIReedy, R. / Cable, J. / Kelly, D. / IEEE et al. | 1999
- 12
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A 1.8V 2.5GHz PLL using 0.18mum SOI/CMOS TechnologyYoshimura, T. / Ueda, K. / Nakura, T. / Kubo, K. / Mashiko, K. / Maeda, S. / Maegawa, S. / Yamaguchi, Y. / Matsuda, Y. / IEEE et al. | 1999
- 14
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A Low Power Sigmadelta Analog-to-Digital Modulator with 50MHz Sampling Rate in a 0.25mum SOI CMOS TechnologySwaminathan, A. / Fong, N. / Lauzon, P. / Yang, H. K. / Maliepaard, M. / Plett, C. / Snelgrove, M. / IEEE et al. | 1999
- 16
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1.5-V 1.8-GHz SOI Low Noise Amplifiers for PCS ReceiversJin, W. / Chan, P. C. / Hai, C. / IEEE et al. | 1999
- 18
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A SOI Current Memory for Analog Signal Processing at High TemperaturePortmann, L. / Declercq, M. / IEEE et al. | 1999
- 20
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A bandgap circuit operating up to 300^o C using lateral bipolar transistors in thin-film CMOS-SOI technologyAdriaensen, S. / Dessard, V. / Flandre, D. / IEEE et al. | 1999
- 22
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Comparison between Fully- and Partially-Depleted SOI MOSFETs for Low-Power Radio-Frequency ApplicationsRozeau, O. / Jomaah, J. / Boussey, J. / Raynaud, C. / Pelloie, J. L. / Balestra, F. / IEEE et al. | 1999
- 24
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High Frequency Characterization of SOI Dynamic Threshold Voltage MOS (DTMOS) TransistorsFerlet-Cavrois, V. / Bracale, A. / Fel, N. / Musseau, O. / Raynaud, C. / Faynot, O. / Pelloie, J. L. / IEEE et al. | 1999
- 26
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Temperature Dependence of AC Floating Body Effects in PD SOI nMOSTseng, Y. C. / Huang, W. M. / Hwang, C. / Welch, P. / Woo, J. C. / IEEE et al. | 1999
- 28
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Thermal Modeling of Thin-Film SOI TransistorsAsheghi, M. / Sverdrup, P. / Goodson, K. E. / IEEE et al. | 1999
- 30
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High Frequency Losses in Transmission Lines made on SIMOX, Bulk Silicon and Depleted Silicon/Silicon Structures Formed by Wafer BondingJohansson, M. / Bergh, M. / Bengtsson, S. / IEEE et al. | 1999
- 32
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Threshold Voltage Design Incompatibility between Partially-Depleted SOI and Bulk CMOS transistorsvan Meer, H. / Lyu, J. H. / Kubicek, S. / Geenen, L. / De Meyer, K. / IEEE et al. | 1999
- 34
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The OFF Leakage in SOI-MOS Transistors and the Impact on the Standby Current of ULSI'sAdan, A. O. / Higashi, K. / Niimi, K. / Ashida, T. / IEEE et al. | 1999
- 36
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`Self-Body-Biased' SOI MOSFET through `Depletion Isolation Effect'Terauchi, M. / Terada, K. / IEEE et al. | 1999
- 38
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Buried Oxide Fringing Capacitance: A New Physical Model and its Implication on SOI Device Scaling and ArchitectureErnst, T. / Cristoloveanu, S. / IEEE et al. | 1999
- 40
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Detailed Analysis of the Gate Delay Variability in Partially Depleted SOI CMOS CircuitsAller, I. / Kroell, K. E. / IEEE et al. | 1999
- 42
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SOI MOSFET Fluctuation Limits on Gigascale Integration (GSI)Tang, X. / De, V. K. / Wang, L. / Meindl, J. D. / IEEE et al. | 1999
- 44
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Architecture and Performance of 3-Dimensional SOI CircuitsZhang, R. / Roy, K. / Janes, D. B. / IEEE et al. | 1999
- 46
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An SOI Single-Electron TransistorTang, X. / Baie, X. / Bayot, V. / Van de Wiele, F. / Colinge, J. P. / IEEE et al. | 1999
- 48
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Evidence of Energetically-Localized Trap-States at SOI-BOX Interface in High-Dose SIMOX WafersUshiki, T. / Kotani, K. / Funaki, T. / Kawai, K. / Ohmi, T. / IEEE et al. | 1999
- 50
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A Body-Contact SOI MOSFET Model for Circuit SimulationSu, P. / Fung, S. K. / Assaderaghi, F. / Hu, C. / IEEE et al. | 1999
- 52
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'Gated-diode' in SOI MOSFETs: a sensitive tool for characterizing the buried Si-SiO2 interfaceZhao, Xuejun / Ioannou, D.E. et al. | 1999
- 52
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"Grated-Diode" in SOI MOSFET's: a sensitive tool for characterizing the buried Si/SiO2 intrfaceZhao, X. / Ioannou, D. / IEEE et al. | 1999
- 54
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Novel 3D StructuresSarawat, K. C. / Souri, S. J. / Subramanian, V. / Joshi, A. R. / Wang, A. W. / IEEE et al. | 1999
- 56
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Advances in Silicon-on-Insulator Photonic Integrated Circuit (SOIPIC) TechnologyJalali, B. / Naydenkov, M. / IEEE et al. | 1999
- 67
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MEMS using SOI SubstrateTang, T. / IEEE et al. | 1999
- 67
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MEMS for space applicationsTang, T.K. et al. | 1999
- 68
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Electrostatic Discharge Protection in Silicon-on-Insulator TechnologyVoldman, S. / Hui, D. / Warriner, L. / Young, D. / Williams, R. / Howard, J. / Gross, V. / Rausch, W. / Leobangdung, E. / Sherony, M. et al. | 1999
- 72
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A 0.5-V, 3-m W, 54 X 54-b Multiplier with a Triple-Vth CMOS/SIMOX Circuit SchemeFujii, K. / Douseki, T. / IEEE et al. | 1999
- 75
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A Novel 0.7V Two-Port 6T SRAM Memory Cell Structure with Single-Bit-Line Simultaneous Read-and-Write Access (SBLSRWA) Capability using Partially-Depleted SOI CMOS Dynamic-Threshold TechniqueLiu, S. C. / Kuo, J. B. / IEEE et al. | 1999
- 77
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A Dynamic Body Discharge Technique for SOI Circuit ApplicationsKuang, J. B. / Saccamango, M. J. / Lu, P. F. / Chuang, C. T. / Assaderaghi, F. / IEEE et al. | 1999
- 79
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Frequency Dependent Behavior of a High Performance Dynamic Register File in 1.8V, 0.25mum SOI TechnologyJoshi, R. V. / Hwang, W. / Wilson, S. C. / Shahidi, G. / Chuang, C. T. / IEEE et al. | 1999
- 82
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Temperature Dependent Hysteretic Propagation Delay in FB SOI Inverter ChainChang, D. / Min, B. / Veeraraghavan, S. / Mendicino, M. / Cooper, T. / Egley, S. / Cox, K. / IEEE et al. | 1999
- 84
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Mechanisms of dynamic pass leakage current in partially depleted SOI MOSFETsSaraya, T. / Hiramoto, T. / IEEE et al. | 1999
- 86
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Scalability of fully-depleted SOI technology into 0.13 mu m 1.2 V-1 V CMOS generationRaynaud, C. / Faynot, O. / Pelloie, J.L. / Martin, F. / Tedesco, S. / Cluzel, J. / Grouillet, A. / Dal'Zotto, B. / Vanhoenacker, D. et al. | 1999
- 86
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Scability of Fully-depleted SOI Technology into 0.13mum 1.2V-1V CMOS GenerationRaynaud, C. / Faynot, O. / Pelloie, J. L. / Martin, F. / Tedesco, S. / Cluzel, J. / Grouillet, A. / Dal'zotto, B. / Vanhoenacker, D. / IEEE et al. | 1999
- 88
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Advanced silicide for sub-0.18 mu m CMOS on ultra-thin (35 mu m) SOIRen, L.P. / Cheng, Baohong / Woo, J.C.S. et al. | 1999
- 88
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Advanced Silicide for Sub-0.18mum CMOS on Ultra-thin (35nm) SOIRen, L. P. / Cheng, B. / Woo, J. C. / IEEE et al. | 1999
- 90
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Performance Trade-offs of Argon Implanted SOI MOSFETs With In and Sb Retrograde Channel DopingXu, X. L. / Widenhofer, R. / Yu, Y. / Zia, O. / Pozder, S. / Hall, D. / Rashed, M. / Chang, D. / Jallepalli, S. / Connelly, D. et al. | 1999
- 92
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Ultimately Thin SOI MOSFETs: Special Characteristics and MechanismsErnst, T. / Munteanu, D. / Cristoloveanu, S. / Ouisse, T. / Hefyene, N. / Horiguchi, S. / Ono, Y. / Takahashi, Y. / Murase, K. / IEEE et al. | 1999
- 94
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High Performance Sub-0.1mum SOI Polysilicon Spacer Gate MOSFETs Using Large Angle Tilted Implant for Drain EngineeringTo, K. H. / Woo, J. C. / IEEE et al. | 1999
- 96
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A RF Power LDMOS Device on SOIFiorenza, J. G. / del Alamo, J. A. / Antoniadis, D. A. / IEEE et al. | 1999
- 98
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Optimal Double-Gate MOSFETs: Symmetrical or Asymmetrical Gates?Kim, K. / Fossum, J. G. / IEEE et al. | 1999
- 100
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An SOI Nano Flash Memory DeviceTang, X. / Baie, X. / Bayot, V. / Van de Wiele, F. / Colinge, J. P. / IEEE et al. | 1999
- 102
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Building Hybrid Active Pixels for CMOS Imager on SOI SubstrateZhang, W. / Chan, M. / Wang, H. / Ko, P. K. / IEEE et al. | 1999
- 104
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IOS-a new type of materials combination for system-on-a chip preparationTong, Q. Y. / Huang, L. J. / Chao, Y. L. / Gang, Q. / Goesele, U. / IEEE et al. | 1999
- 106
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Thin-Layer SIMOX For Future ApplicationsAnc, M. J. / Dolan, R. P. / Jiao, J. / Nakai, T. / IEEE et al. | 1999
- 108
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Multi-Layer SOI Island Technology by Selective Epitaxial Growth for Single-Gate and Double-Gate MOSFETsPae, S. / Denton, J. P. / Neudeck, G. W. / IEEE et al. | 1999
- 110
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ELTRAN(R) by water-jet splitting in stress-controlled porous SiSakaguchi, K. / Yanagita, K. / Kurisu, H. / Suzuki, H. / Ohmi, K. / Yonehara, T. et al. | 1999
- 110
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ELTRAN® by Water-Jet Splitting in Stress-Controlled Porous SiSakaguchi, K. / Yanagita, K. / Kurisu, H. / Suzuki, H. / Ohmi, K. / Yonehara, T. / IEEE et al. | 1999
- 112
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SOI Formation From Amorphous Silicon by Metal-Induced-Lateral-Crystallization (MILC) and Subsequent High Temperature AnnealingJagar, S. / Chan, M. / Poon, M. C. / Wang, H. / Qin, M. / Shivani, S. / Ko, P. K. / Wang, Y. / IEEE et al. | 1999
- 114
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Thinning of Si in SOI wafers by the SC1 Standard CleanCeller, G. K. / Barr, D. L. / Rosamilia, J. M. / IEEE et al. | 1999
- 116
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SIMOX SOI Surface Smoothing for Gate Oxide Integrity and ReliabilityAllen, L. P. / Fenner, D. B. / Skinner, W. J. / Chandonnet, R. / Deziel, S. E. / Torti, R. P. / Toyoda, N. / IEEE et al. | 1999
- 119
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Integrity of the Gate Oxide on the Thin Top Si Layer in ITOX-SIMOX WafersNakashima, S. / Kodate, J. / IEEE et al. | 1999
- 121
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Defect Analysis of Patterned SOI MaterialBagchi, S. / Yu, Y. / Mendicino, M. / Conner, J. / Anderson, A. / Prabhu, L. / Tiner, M. / Alles, M. / IEEE et al. | 1999
- 123
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Effect of Single-Step, High-Oxygen-Concentration Annealing on Buried Oxide Layer Microstructure in Post-Implant-Amorphized, Low-Dose SIMOX MaterialChen, L. / Bagchi, S. / Krause, S. J. / Roitman, P. R. / IEEE et al. | 1999
- 125
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Study of Cu Diffusion in Ultra Thin Bonded SOI Wafers Evaluated by Using Radioactive Isotope TracersFurihata, J. I. / Nakano, M. / Mitani, K. / IEEE et al. | 1999
- 127
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The Effects of Preparation Conditions of SIMOX Samples on the Photoluminescence Spectra of their Buried Oxide LayerSkorupa, W. / Rebohle, L. / Revesz, A. G. / Hughes, H. L. / IEEE et al. | 1999
- 129
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Fractional Implantation Area Effects on Patterned Ion-Cut Silicon Layer TransferYun, C. H. / Cheung, N. W. / IEEE et al. | 1999
- 131
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Bulk-Layout-Compatible 0.18mum SOI-CMOS Technology Using Body-Fixed Partial Trench Isolation (PTI)Hirano, Y. / Maeda, S. / Matsumoto, T. / Nii, K. / Iwamatsu, T. / Yamaguchi, Y. / Ipposhi, T. / Kawashima, H. / Maegawa, S. / Inuishi, M. et al. | 1999
- 133
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Power Amplifiers on Thin-Film-Silicon-on-Insulator (TFSOI) TechnologyNgo, D. / Huang, W. M. / Ford, J. M. / IEEE et al. | 1999
- 135
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Circuit Simulator and Compact Model Requisites for Accurate Simulation of AC Floating Body Behavior in PD SOIBenson, J. / Redman-White, W. / Easson, C. A. / D'Halleweyn, N. V. / Uren, M. J. / IEEE et al. | 1999