Ziel dieser Dissertation war die Entwicklung eines Mehrkanal-Mischsignal-ASICs für die Auslese von Detektoren. Die vorliegende Arbeit beschreibt den gesamten Entwicklungsprozess, welcher mit der unspezifischen Aufgabenstellung des Entwurfs eines Auslesechips für einen der Teildetektoren von CBM/FAIR beginnt und der mit der neusten und tatsächlich realisierten system-on-a-chip Lösung mit dem Namen SPADIC endet, deren Haupteinsatzzweck die Auslese des zukünftigen CBM-TRD ist. Diese Arbeit umfasst den von Grunde auf begonnenen Entwicklungsprozess von insgesamt 6 ASIC Prototypen und 10 PCB Ausleseaufbauten sowie die Entwicklung diverser Software- und Firmwarekomponenten, die Charakterisierung der entworfenen ASICs, die Entwicklung des SPADIC-Konzeptes, den Entwurf der SPADIC Webseite und nicht zuletzt die Zusammenarbeit mit den TRD-Physikern, mit dem erreichten Ziel mithilfe verschiedener SPADICs Kammer-Prototypen während CERN-Testbeams oder im Labor auszulesen. Neben den Beschreibungen der wichtigsten Chipdetails und den dazugehörigen theoretischen Analysen, enthält diese Abhandlung auch eine allgemeine, auf einem Niveau für Ingenieure gehaltene, Einführung in die Varianten von Detektoren und in die Detektorphysik, mit dem Ziel diese technische Arbeit in ihren physikalischen Kontext einzubetten. Das effektive Resultat dieser Dissertation ist der selbstgetriggerte 32-Kanal-Ladungspuls-Verstärker und Digitalisierungs-Chip SPADIC 1.0.
This work comprises the whole journey from the initial and vague requirement of a dedicated readout chip for some CBM sub-detector(s) to a comprehensive and flexible readout system for the TRD sub-detector. The obtained result consists of the full development of the SPADIC readout concept with all its theoretical and technical details and of the realization of 6 SPADIC versions and 10 system prototypes that, moreover, have eventually all successfully been operated and characterized. The numberless technical and practical steps that had to be taken for that purpose and the countless lines of code of software, firmware, and hardware that had to be written are not further summarized here. Instead it shall be emphasized, that the resulting chip design is not simply an arbitrarily chosen solution, but effectively the result of a close and long lasting collaboration with the detector physicists on the one hand and the DAQ engineers on the other hand. In fact, all crucial design decisions that have been made during the years and that have finally led to the present SPADIC design concept, were all based either on intense and perpetual discussions or on well-founded experience, which has been gathered basically from simulations, observations, and measurements. A basic principle of this work has always been to take nothing for granted and to leave nothing to chance. Being the central result, the whole SPADIC 1.0 prototype does not only prove the overall system concept to be suitable for the CBM-TRD application, but has also shown all used chip components as well as the whole mixed-signal architecture to work properly. Due to the very flexible and versatile architecture, the SPADIC chip can be directly used or at least easily adapted for other applications as well. That is especially true, since all functionalities have been clearly separated and all building blocks have been modularly designed - on all levels of hierarchy. SPADIC 1.0 is a free-running multi-channel mixed-signal readout system on a chip. It combines high sensitivity amplification with flexible data handling and processing on one single die. It is easily accessible and flexibly adjustable. The oscilloscope-like behavior offers various new opportunities and allows comfortably monitoring and analyzing all kinds of short detector charge pulses. Whereas most of the characteristic numbers rather lie in a moderate range (e.g. the time and amplitude resolution or the power consumption), the main qualities of the SPADIC system are its compactness, its flexibility, and its convenience. Nevertheless, SPADIC 1.0 is still not the end of the line. As mentioned in the respective chapters before, some uncritical but necessary bugs have to be fixed and some few but important tasks still have to be addressed. Especially an improved single event effect (SEE) tolerance of the digital part and a final analog adjustment of the front-end to the final TRD detector requirements are probably important steps that will have to be taken. And, moreover, already a new list with additional beneficial ideas exists. For all that reasons, at least one iteration after SPADIC 1.0 will have to be designed and tested. Furthermore, one must not forget that even though all crucial parts of SPADIC 1.0 have been successfully operated, the analog part has not been fully characterized yet. The results that are shown in this paper are mostly preliminary and especially the analog details of the CSA and the ADC still have to be extracted more carefully. Another future issue concerning SPADIC 1.0 is the readout setup. Whereas, as mentioned earlier in this document, first real chamber signals could be read out with the latest available setup, many open questions still remain and a lot of effort will have to be taken to find proper answers. A very crucial task for instance will be to make the setup more reliable and stable. That includes the search for proper power-on cycles, stable grounding schemes, reliable reset strategies, et cetera. Moreover, another important task will probably be to build and operate a PCB that carries several SPADIC 1.0 dies close to each other (pitch 2 cm).