International Test Conference 1988 Proceedings - New Frontiers in Testing, 12-14 Sept. 1988, Washington, DC, USA (English)
1988
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ISBN:
- Conference Proceedings / Print
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Title:International Test Conference 1988 Proceedings - New Frontiers in Testing, 12-14 Sept. 1988, Washington, DC, USA
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Additional title:Internationale Pruefkonferenz 1988. Berichte - Neue Pruefgrenzen, 12.-14. Sept. 1988, Washington, DC, USA
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Publisher:
- New search for: IEEE Comput. Soc. Press
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Place of publication:Washington
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Publication date:1988
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Size:1005 Seiten
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ISBN:
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Type of media:Conference Proceedings
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Type of material:Print
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Language:English
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Keywords:CAD/CAM , LEITERPLATTENPRUEFUNG , VLSI-SCHALTUNG , WORKSTATION , FEHLERSIMULATION , PRUEFAUTOMAT , AUTOMATISCHE PRUEFUNG , WIRTSCHAFT (OEKONOMIE) , FEHLERORTUNG , RAM (DIREKTZUGRIFFSSPEICHER) , SIGNATURANALYSE , WIRTSCHAFTLICHKEIT , PRUEFVERFAHREN , PRUEFUNG INTEGRIERTER SCHALTUNGEN , LOGIKPRUEFUNG , MESSNORM , OPTISCHE PRUEFUNG , SRAM (STATIC RAM) , PRUEFBARKEIT , SYSTEMS TEST
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
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International Test Conference 1988 Proceedings - New Frontiers in Testing (Cat. No.88CH2610-4)| 1988
- 4
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Optimal logic synthesis and testability: two faces of the same coinDevadas, S. / Ma, H.K.T. / Newton, A.R. / Sangiovanni-Vincentelli, A. et al. | 1988
- 13
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GaAs driver and sensor for a high speed systemTsai, S.J. / Hechtman, C.D. et al. | 1988
- 23
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Integrated pin electronics for a VLSI test systemBranson, C. / Murray, D. / Sullivan, S. et al. | 1988
- 28
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Characteristic impedance and coupling coefficients for multilayer PC boardsBirchak, J.R. / Haill, H.K. et al. | 1988
- 39
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Practical production testing of ISDN circuit boardsMcAuliffe, R.E. et al. | 1988
- 47
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Board-level diagnosis by signature analysisKarpovsky, M.G. / Nagvajara, P. et al. | 1988
- 54
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Fault isolation in grey systemsSu, S.Y.H. / Ma, H. et al. | 1988
- 64
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Analysis of experimental results on functional testing and diagnosis of complex circuitsBellon, C. / Velazco, R. / Ziade, H. et al. | 1988
- 73
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Microprocessor testing by instruction sequences derived from random patternsKlug, H.P. et al. | 1988
- 81
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Detection of control flow errors using signature and checking instructionsSosnowski, J. et al. | 1988
- 89
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A parallel algorithm for fault simulation on the Connection MachineNarayanan, V. / Pitchumani, V. et al. | 1988
- 94
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Fault simulation and test pattern generation at the multiple-valued switch levelCaisso, J.P. / Courtois, B. et al. | 1988
- 102
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A method to generate tests for combinational logic circuits using an ultrahigh-speed logic simulatorHirose, F. / Takayama, K. / Kawato, N. et al. | 1988
- 108
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Key technologies for 500-MHz VLSI system ULTIMATETamama, T. / Narumi, N. / Otsuji, T.-i. / Suzuki, M. / Sudo, T. et al. | 1988
- 114
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Software environment for 500-MHz VLSI test system ULTIMATEAdachi, T. / Tanno, M. / Sudo, T. et al. | 1988
- 120
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Packaging technologies for 500-MHz VLSI test system ULTIMATESakagawa, Y. / Akazawa, Y. / Narumi, N. / Yoshii, A. / Sudo, T. et al. | 1988
- 126
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Testing and diagnosis of interconnects using boundary scan architectureHassan, A. / Rajski, J. / Agarwal, V.K. et al. | 1988
- 138
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Boundary scan with cellular-based built-in self-testGloster, C.S. jun. / Brglez, F. et al. | 1988
- 146
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Design for testability for wafer-scale integration interconnect systems design and test methodologyGruetzner, M. et al. | 1988
- 153
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Testability features in the TMS370 family of microcomputersPowell, T.J. / Hwang, F. / Johnson, B. et al. | 1988
- 161
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Testability features of a 32 kbps ADPCM transcoderBonet, L.A. et al. | 1988
- 172
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Design for testability of a 32-bit microprocessor-the TX1Nozuyama, Y. / Nishimura, A. / Iwamura, J. et al. | 1988
- 183
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What is the path to fast fault simulation?Abramovici, M. / Krishnamurthy, B. / Mathews, R. / Rogers, B. / Schulz, M. / Seth, S. / Waicukauski, J. et al. | 1988
- 193
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Standardization of ATE timing accuracy specificationsMydill, M. et al. | 1988
- 195
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Boundary scan-the ATE vendors' viewCollins, P. et al. | 1988
- 197
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Semiconductor perspective on test standardsFleming, P. et al. | 1988
- 199
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Impact of testability standards on university research and instructionKime, C.R. et al. | 1988
- 201
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Value of testability standards in testing commercial productsRichards, D.J. et al. | 1988
- 203
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Practice and theory (IC testing)McCluskey, E.J. et al. | 1988
- 205
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Digital testing theory and practiceMourad, S. et al. | 1988
- 207
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Do the designs work? (VLSI design education)Rose, K. et al. | 1988
- 209
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Expert system for the functional test program generation of digital electronic circuit boardsLea, S.M. / Brown, N. / Katz, T. / Collins, P. et al. | 1988
- 221
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Hierarchical test generation using precomputed testsd for modulesMurray, B.T. / Hayes, J.P. et al. | 1988
- 230
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The KARL/KARATE system-automatic test pattern generation based on RT level descriptionsAlfs, G. / Hartenstein, R.W. / Wodtko, A. et al. | 1988
- 236
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Multiple distributions for biased random test patternsWunderlich, H.J. et al. | 1988
- 245
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Fault detection effectiveness of weighted random patternsWaicukauski, J.A. / Lindbloom, E. et al. | 1988
- 256
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WTPGA: a novel weighted test-pattern generation approach for VLSI built-in self testSiavoshi, F. et al. | 1988
- 263
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RTRAM: reconfigurable and testable multi-bit RAM designPradhan, D.K. / Kamath, N.R. et al. | 1988
- 279
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An on-chip double-bit error-correcting code for three-dimensional dynamic random-access memoryMazumder, P. et al. | 1988
- 289
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Application of a commercial data base management system to memory device test program generation and debuggingGrennan, S. et al. | 1988
- 295
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IC qualityd and test transparencyMcCluskey, E.J. / Buelow, F. et al. | 1988
- 302
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Design for test and the cost of qualitySalzmann, C. / Funcell, M. / Taylor, R. et al. | 1988
- 308
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Elimination of incoming test based upon in-process failure and repair costsBallew, W.D. / Streb, L.M. et al. | 1988
- 314
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On multiple fault coverage and aliasing probability measuresCox, H. / Ivanov, A. / Agarwal, V.K. / Rajski, J. et al. | 1988
- 322
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Identification of failing tests with cycling registersSavir, J. / McAnney, W.H. et al. | 1988
- 329
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A new framework for designing and analyzing BIST techniques: computation of exact aliasing probabilityGupta, S.K. / Pradhan, D.K. et al. | 1988
- 343
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Fault modeling and test algorithm development for static random access memoriesDekker, R. / Beenker, F. / Thijssen, L. et al. | 1988
- 353
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A realistic self-test machine for static random access memoriesDekker, R. / Beenker, F. / Thijssen, L. et al. | 1988
- 362
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Dual port static RAM testingRaposa, M.J. et al. | 1988
- 369
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Reliability testing by precise electrical measurementDorey, A.P. / Jones, B.K. / Richardson, A.M. / Russell, P.C. / Xu, Y.Z. et al. | 1988
- 374
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Fault detection of combinational circuits based on supply currentHashizume, M. / Yamada, K. / Tamesada, T. / Kawakami, M. et al. | 1988
- 381
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An advanced data compaction approach for test-during burn-inSchneider, B. / Oestergaard, P. et al. | 1988
- 391
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In-circuit test fixtureHechtman, C.D. et al. | 1988
- 401
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New testing equipment for SMT PC boardsBalme, L. / Mignotte, A. / Monari, J.Y. / Pondaven, P. / Vaucher, C. et al. | 1988
- 411
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Evaluating the limitations of high-speed board testersArena, J. et al. | 1988
- 421
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Test scheduling for high performance VLSI system implementationsSayah, J. / Kime, C.R. et al. | 1988
- 431
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Concurrent control of multiple BIT structuresBreuer, M.A. / Gupta, R. / Lien, J.-C. et al. | 1988
- 443
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Optimal scheduling of signature analysis for VLSI testingLee, Y.H. / Krishna, C.M. et al. | 1988
- 452
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A high level approach to integrating design and testIvie, J. et al. | 1988
- 460
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Optimal use of timing resources: a crucial step in test program generationChang, J.M. / Krakow, W.T. et al. | 1988
- 466
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A strategy for generating functional tests from device simulationsMerritt, C. et al. | 1988
- 475
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Extraction and simulation of realistic CMOS faults using inductive fault analysisFerguson, F.J. / Shen, J.P. et al. | 1988
- 485
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Dynamic techniques for yield enhancement of field programmable logic arraysDemjanenko, M. / Upadhyaya, S.J. et al. | 1988
- 492
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Statistical delay fault coverage and defect level for delay faultsPark, E.S. / Mercer, M.R. / Williams, T.W. et al. | 1988
- 500
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Contactors for testing at high frequenciesRiechelmann, B. et al. | 1988
- 502
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A test and maintenance controller for a module containing testable chipsBreuer, M.A. / Lien, J.C. et al. | 1988
- 514
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A BIST design of structured arrays with fault-tolerant layoutKatoozi, M. / Soma, M. et al. | 1988
- 522
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Reconfigurable hardware for pseudoexhaustive testUdell, J.G. jun. et al. | 1988
- 531
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Evaluation of system BIST using computational performance measuresLandis, D.L. / Muha, D.C. et al. | 1988
- 537
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Some new techniques in waveshape capture and analysisDowney, A.E. / Matsuda, K. et al. | 1988
- 547
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A high-resolution waveform analysis toolPowers, P.M. et al. | 1988
- 551
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Functional test program generation through interactive graphicsTinaztepe, C. / Ozguc, B. et al. | 1988
- 559
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PGTOOL: an automatic interactive program generation tool for testing new-generation memory devicesKawabata, Y. / Maruyama, M. / Tejeda, A. et al. | 1988
- 569
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Fault bundling: reducing machine evaluation activity in hierarchical concurrent fault simulationNicholls, W.H. / Soma, M. et al. | 1988
- 574
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Switch-level concurrent fault simulation based on a general purpose list traversal mechanismMachlin, D. / Gross, D. / Kadkade, S. / Ulrich, E. et al. | 1988
- 582
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D3FS: a demand driven deductive fault simulatorSmith, S.P. / Mercer, M.R. / Underwood, B. et al. | 1988
- 593
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On behavior fault modeling for combinational digital designsChakraborty, T. / Ghosh, S. et al. | 1988
- 601
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Membrane probe card technology (the future for higher performance wafer test)Leslie, B. / Matta, F. et al. | 1988
- 608
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Very high density probingBarsotti, C. / Tremaine, S. / Bonham, M. et al. | 1988
- 615
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New automated prober support for high pincount test headsFredriksen, T.R. / Grano, D. et al. | 1988
- 621
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Synthesis and optimization procedures for fully and easily testable sequential machinesDevadas, S. / Ma, H.K.T. / Newton, A.R. / Sangiovanni-Vincentelli, A. et al. | 1988
- 631
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A knowledge representation scheme for DFTD'Souza, D.F. et al. | 1988
- 642
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Enhancing random-pattern coverage of programmable logic arrays via masking techniqueFujiwara, H. / Fujisawa, O. / Hikone, K. et al. | 1988
- 649
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Managing the ASIC design to test processCulbertson, G.D. et al. | 1988
- 657
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Built-in test compiler in an ASIC environmentArchambeau, E. / Van Egmond, K. et al. | 1988
- 665
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An expert test program generation system for per-pin testersWalter, A. / Kleinman, Y. / Edelshteyn, L. / Gartner, J. et al. | 1988
- 669
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On the testing of multiplexersMakar, S.R. / McCluskey, E.J. et al. | 1988
- 680
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Robust tests for parity treesKundu, S. / Reddy, S.M. et al. | 1988
- 688
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Stuck-open and transition fault testing in CMOS complex gatesCox, H. / Rajski, J. et al. | 1988
- 695
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Optical testing of printed circuit boardsTremblay, G. / Meyrueix, P. / Peuzin, J.C. et al. | 1988
- 700
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Test head design using electrooptic receivers and GaAs pin electronics for a gigahertz production test systemHenley, F.J. / Choi, H.J. et al. | 1988
- 710
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High-speed pattern generator and GaAs pin electronics for a gigahertz production test systemKratzer, D.J. / Barton, S. / Benley, F.J. / Plomgrem, D.A. et al. | 1988
- 719
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Circular BIST with partial scanPradhan, M.M. / O'Brien, E.J. / Lam, S.L. / Beausang, J. et al. | 1988
- 730
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An incomplete scan design approach to test generation for sequential machinesMa, H.K.T. / Devadas, S. / Newton, A.R. / Sangiovanni-Vincentelli, A. et al. | 1988
- 735
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Threading a multiple scan paths in a VLSI circuitBhawmick, S. / Khaira, M.S. / Mishra, P.P. / Das, A. / Dasgupta, A. / Palchaudhury, P. et al. | 1988
- 744
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Integrated test logic for video IC'sBeck, J. / Rose, R. / Pappas, J. / Seiler, L. et al. | 1988
- 752
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Flexible deep memory architecture aids program developmentRusso, J.L. et al. | 1988
- 755
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Timing generation for DSP testingRosenfeld, E. et al. | 1988
- 764
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G-RIDDLE: a formal analysis of logic designs conducive to the acceleration of backtracingSilberman, G.M. / Spillinger, I. et al. | 1988
- 773
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Detecting bridging faults with stuck-at test setsMillman, S.D. / McCluskey, E.J. et al. | 1988
- 784
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An algorithmic branch and bound method for PLA test pattern generationRobinson, M. / Rajski, J. et al. | 1988
- 796
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Trouble-shooting: a key to process improvementYau, C.W. / Chang, S.L. / Jordan, B.F. / Schwermann, J.J. / Wellman, J.A. et al. | 1988
- 804
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Predicting and obtaining high final test yieldsBalzer, R.J. / Larsen, G.A. et al. | 1988
- 816
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CIM, electronics manufacturing . . .and ATEHutchinson, N. et al. | 1988
- 823
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Design for testability of mixed signal integrated circuitsWagner, K.D. / Williams, T.W. et al. | 1988
- 829
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TASTE: a tool for analog system testability evaluationHemink, G.J. / Meijer, B.W. / Kerkhoff, H.G. et al. | 1988
- 839
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DCIATP-an iterative analog circuit test generation program for generating DC single pattern testsMarlett, M.J. / Abraham, J.A. et al. | 1988
- 845
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On the detection of delay faultsPramanick, A.K. / Reddy, S.M. et al. | 1988
- 857
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Delay test generation. I. Concepts and coverage metricsIyengar, V.S. / Rosen, B.K. / Spillinger, I. et al. | 1988
- 867
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Delay test generation. II. Algebra and algorithmsIyengar, V.S. / Rosen, B.K. / Spillinger, I. et al. | 1988
- 877
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Experiences with concurrent fault simulation of diagnostic programsDemba, S. / Ulrich, E. / Panetta, K. / Giramma, D. et al. | 1988
- 884
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System level fault dictionary generationTanaka, H. / Kawai, M. / Sugasaki, I. / Hakuba, T. et al. | 1988
- 888
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Designs for diagnosability and reliability in VLSI systemsSu, S.Y.H. / Ma, H. et al. | 1988
- 898
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Automatic location of IC design errors using an E-beam systemMelgara, M. / Battu, M. / Garino, P. / Dowe, J. / Vernay, Y.J. / Marzouki, M. / Boland, F. et al. | 1988
- 908
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Electron beam tester integrated into a VLSI testerNiijima, H. / Tokunaga, Y. / Koshizuka, S. / Yakuwa, K. / Fazekas, P. / Sturm, M. / Feuerbaum, H.P. et al. | 1988
- 914
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Continuous signature monitoring: efficient concurrent-detection of processor control errorsWilken, K. / Shen, J.P. et al. | 1988
- 926
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Error detection with latency in sequential circuitsHolmquist, L.P. / Kinney, L.L. et al. | 1988
- 934
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Concurrent off-phase built-in self-test of dormant logicSigal, L.J. / Kime, C.R. et al. | 1988
- 942
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Techniques for user testing of the 68882Marshall, M. et al. | 1988
- 948
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Simultaneous switching noise evaluation of advanced CMOS logic (ACL)Stuchlik, K.R. et al. | 1988
- 958
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Emulative testing at the bus speed limitArnett, D.B. / Bhaskar, K.S. et al. | 1988
- 969
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Built-in test strategy for next generation military avionic hardwareMerlino, D.H. / Hadjilogiou, J. et al. | 1988
- 976
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Using scan technology for debug and diagnostics in a workstation environmentDervisoglu, B.I. et al. | 1988
- 987
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Scan diagnostic strategy for the series 10000 PRISM workstationRicchetti, M. / Hoglund, J. et al. | 1988
- 993
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CAD tools for supporting system design for testabilityHallenbeck, J.J. / Kanopoulos, N. / Vasanthavada, N. / Watterson, J.W. et al. | 1988
- 994
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Testability using random access test registerBui, C. et al. | 1988
- 996
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Designing state machines for testabilityTreseler, M. et al. | 1988
- 997
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On benchmarking digital testing systemsMourad, S. / McCluskey, E.J. et al. | 1988
- 998
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The non-linear feedback shift-register as a built-in self-test (BIST) resourceMarinos, P.N. et al. | 1988
- 999
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Detection of hard faults in a combinational circuit using budget constraintsStannard, D. / Kaminska, B. et al. | 1988
- 1000
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Partial hardware partitioning: a new pseudo-exhaustive test implementationUdell, J.G. jun. / McCluskey, E.J. et al. | 1988
- 1001
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Defining a standard for fault simulator evaluationAl-Arian, S.A. / Kwiat, K.A. et al. | 1988
- 1002
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Determination of safe back-driving currents in bond wires and diceHill, G.J. / Roberts, B.C. / Strudwick, C.P. et al. | 1988