A noise-immune GHz-clock distribution scheme using synchronous distributed oscillators (English)
- New search for: Mizuno, H.
- New search for: Ishibashi, K.
- New search for: Mizuno, H.
- New search for: Ishibashi, K.
In:
ISSCC, IEEE International Solid-State Circuits Conference, 1998
;
404-405
;
1998
-
ISBN:
- Conference paper / Print
-
Title:A noise-immune GHz-clock distribution scheme using synchronous distributed oscillators
-
Contributors:Mizuno, H. ( author ) / Ishibashi, K. ( author )
-
Published in:
-
Publisher:
- New search for: Institute of Electrical and Electronics Engineers (IEEE)
-
Place of publication:New York
-
Publication date:1998
-
Size:2 Seiten, 2 Quellen
-
ISBN:
-
DOI:
-
Type of media:Conference paper
-
Type of material:Print
-
Language:English
-
Keywords:
-
Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
-
1998 ieee international solid-state circuits conference. digest of technical papers, isscc. first edition [front cover and table of contents]| 1998
- 16
-
Challenges in semiconductor technology for multi-megabit network servicesNakamura, M. et al. | 1998
- 22
-
GSM and beyond-the future of the access networkDanneels, J. et al. | 1998
- 26
-
The Global Positioning System: challenges in bringing GPS to mainstream consumersChadha, K. et al. | 1998
- 30
-
A 100mm^2 0.95W Single-Chip MPEG2 MP@ML Video Encoder with a 128GOPS Motion Estimator and a Multi-Tasking RISC-Type ControllerMiyagoshi, E. / Araki, T. / Sayama, T. / Ohtani, A. / IEEE et al. | 1998
- 30
-
A 100 mm/sup 2/ 0.95 W single-chip MPEG2 MP@ML video encoder with a 128GOPS motion estimator and a multi-tasking RISC-type controllerMiyagoshi, E. / Araki, T. / Sayama, T. / Ohtani, A. / Minemaru, T. / Okamoto, K. / Kodama, H. / Morishige, T. / Watabe, A. / Aoki, K. et al. | 1998
- 32
-
A 1.2 W single-chip MPEG2 MP@ML video encoder LSI including wide search range motion estimation and 81 MOPS controllerOgura, E. / Takashima, M. / Hiranaka, D. / Ishikawa, T. / Yanagita, Y. / Suzuki, S. / Fukuda, T. / Ishii, T. et al. | 1998
- 36
-
A 60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage schemeTakahashi, M. / Hamada, M. / Nishikawa, T. / Arakida, H. / Tsuboi, Y. / Fujita, T. / Hatori, F. / Mita, S. / Suzuki, K. / Chiba, A. et al. | 1998
- 38
-
0.5m CMOS Circuits performing OFDM Demodulation and Channel Estimation/Correction for Digital Terrestrial TV ApplicationsDel Toso, C. / Combelles, R. / Penard, P. / Senn, P. / IEEE et al. | 1998
- 38
-
0.5 /spl mu/m CMOS circuits performing OFDM demodulation and channel estimation/correction for digital terrestrial TV applicationsDel Toso, C. / Combelles, P. / Penard, P. / Senn, P. / Sicre, J.-L. / Lauer, L. / Soyer, L. / Galbrun, J. / Scalise, F. et al. | 1998
- 40
-
A power-efficient single-chip OFDM demodulator and channel decoder for multimedia broadcastingHuisken, J.A. / Bekooij, M.J.G. / Gielis, G.C.M. / Gruijters, P.W.F. / Welten, F.P.J. et al. | 1998
- 44
-
A 900 MHz transceiver chipset for two-way paging applicationsSanielevici, S.A. / Cioffi, K.R. / Ahrari, B. / Stephenson, P.S. / Skoglund, D.L. / Zargari, M. et al. | 1998
- 46
-
A CMOS IF Transceiver for Narrowband PCSPaulus, T. / Somayajula, S. / Kyong Choi, T. M. / Trotter, B. / IEEE et al. | 1998
- 46
-
CMOS IF transceiver for narrowband PCSPaulus, T. / Somayajula, S. / Miller, T. / Kyong Choi, / Trotter, B. / Kerth, D. et al. | 1998
- 48
-
A single-chip CMOS transceiver for DCS-1800 wireless communicationsSteyaert, M. / Borremans, M. / Janssens, J. / de Muer, B. / Itoh, I. / Craninckx, J. / Crols, J. / Morifuji, E. / Momose, S. / Sansen, W. et al. | 1998
- 50
-
A 3.6 V 4 W 0.2cc Si power-MOS-amplifier module for GSM handset phonesYoshida, S. / Katsueda, M. / Morikawa, M. / Matsunaga, Y. / Fujioka, T. / Hotta, M. / Nunogawa, Y. / Kobayashi, K. / Shimuzu, S. / Nagata, M. et al. | 1998
- 52
-
A 2.7-5.5 V 0.2-1 W BiCMOS RF driver amplifier IC with closed-loop power control and biasingWong, S. / Luo, S. / Hadley, L. et al. | 1998
- 54
-
An IC for linearizing RF power amplifiers using envelope elimination and restorationSu, D. / McFarland, W. et al. | 1998
- 58
-
An audio DAC with 90 dB linearity using MOS to metal-metal charge transferWilliams, L.A. et al. | 1998
- 60
-
A 1.5 V, 4.1 mW dual channel audio delta-sigma D/A converterFujimori, I. / Sugimoto, T. et al. | 1998
- 60
-
A 1.5V, 4,1mW Dual-Channel Audio Delta-Sigma D/A Converter SessionFujimori, I. / Sugimoto, T. / IEEE et al. | 1998
- 62
-
A 113 dB SNR oversampling DAC with segmented noise-shaped scramblingAdams, R. / Nguyen, K. / Sweetland, K. et al. | 1998
- 64
-
A 100kHz 9.6mW Multi-bit cap delta DAC and ADC using Noise Shaping Dynamic Elements Matching with Tree StructureYasuda, A. / Tanimoto, H. / Iida, T. / IEEE et al. | 1998
- 64
-
A 100 kHz 9.6 mW multi bit /spl Delta//spl Sigma/ DAC and ADC using noise shaping dynamic elements matching with tree structureYasuda, A. / Tanimoto, H. / Lida, T. et al. | 1998
- 66
-
An Eight-order Bandpass /spl delta/ /spl sigma/l Modulator For A/D Conversion In Digital RadioLouis, L. / Abcarius, J. / Roberts, G. et al. | 1998
- 68
-
A 900mV 40mW Switched Opamp cap delta Modulator with 77dB Dynamic RangePeluso, V. / Vancorenland, P. / Marques, A. / Steyaert, M. / IEEE et al. | 1998
- 68
-
A 900 mV 40 /spl mu/W switched opamp /spl Delta//spl Sigma/ modulator with 77 dB dynamic rangePeluso, V. / Vancorenland, P. / Marques, A. / Steyaert, M. / Sansen, W. et al. | 1998
- 68
-
A 900mV 40mW Switched Opamp Modulator with 77dB Dynamic RangePeluso, V. / Vancorenland, P. / Marques, A. / Steyaert, M. / IEEE et al. | 1998
- 72
-
A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generatorYabe, T. / Miyano, S. / Sato, K. / Wada, M. / Haga, R. / Wada, O. / Enkaku, M. / Hojyo, T. / Mimoto, K. / Tazawa, M. et al. | 1998
- 74
-
An ASIC library granular DRAM macro with built-in self testDreibelbis, J. / Barth, J. / Kho, R. / Kalter, T. et al. | 1998
- 76
-
500 Mb/s non-precharged data bus for high-speed DRAMSaito, M. / Ogawa, J. / Wakayama, S. / Tamura, H. / Araki, H. / Tsz-Shing Cheung, / Gotoh, K. / Nishi, T. / Aikawa, T. / Suzuki, T. et al. | 1998
- 78
-
A 220 mm/sup 2/ 4 and 8 bank 256 Mb SDRAM with single-sided stitched WL architectureKirihata, T. / Gall, M. / Hosokawa, K. / Dortu, J.-M. / Wong, H. / Pfefferl, K.-P. / Ji, B. / Weinfurtner, O. / DeBrosse, J. / Terletzki, H. et al. | 1998
- 78
-
A 220mm^2 4 and 8 Bank 256Mb SDRAM with Single-Sided Stitched WL ArchitectureKirihata, T. / Gall, M. / Hosokawa, K. / Dortu, J.-M. / IEEE et al. | 1998
- 80
-
A 256Mb SDRAM with Subthreshold Leakage Current SuppressionHasegawa, M. / Nakamura, U. / Narui, S. / Ohkuma, S. / IEEE et al. | 1998
- 80
-
A 255 Mb SDRAM with subthreshold leakage current suppressionHasegawa, M. / Nakamura, M. / Ohkuma, S. / Kawase, Y. / Endoh, H. / Miyatake, S. / Akiba, T. / Kawakita, K. / Yoshida, M. / Yamada, S. et al. | 1998
- 82
-
A 1 Gb SDRAM with ground level precharged bitline and non-boosted 2.1 V word lineEto, S. / Matsumiya, M. / Takita, M. / Ishii, Y. / Nakamura, T. / Kawabata, K. / Kano, H. / Kitamoto, A. / Ikeda, T. / Koga, T. et al. | 1998
- 86
-
Beyond superscalar RISC, what next? An almost unbiased viewLuick, D.A. et al. | 1998
- 86
-
A Sub-0.1?m Circuit Design with Substrate-over-BiasingOowaki, Y. / Noguchi, M. / Takagi, S. / Takashima, D. / IEEE et al. | 1998
- 88
-
A sub-0.1 /spl mu/m circuit design with substrate-over-biasing [CMOS logic]Oowaki, Y. / Noguchi, M. / Takagi, S. / Takashima, D. / Ono, M. / Matsunaga, Y. / Sunouchi, K. / Kawaguchiya, H. / Matsuda, S. / Kamoshida, M. et al. | 1998
- 90
-
Statistical circuit characterization for deep-submicron CMOS designsChen, J. / Orshansky, M. / Chenming Hu, / Wan, C.-P. et al. | 1998
- 92
-
Multi-chip module with optical interconnection for parallel processor systemKoyanagi, M. / Matsumoto, T. / Shimatani, T. / Hirano, K. / Kurino, H. / Aibara, R. / Kuwana, Y. / Kuroishi, N. / Kawata, T. / Miyakawa, N. et al. | 1998
- 94
-
A 1M synapse self-learning digital neural network chipSaito, O. / Aihara, K. / Fujita, O. / Uchimura, K. et al. | 1998
- 96
-
Bulk spin quantum computation: toward large-scale quantum computationChuang, I.L. / Vandersypen, L.M.K. / Harris, J.S. et al. | 1998
- 98
-
Three Decades of DRAM Development, Debates, and DistinctionIEEE et al. | 1998
- 100
-
How Much Analog is Going to Survive on Large Digital Chips?IEEE et al. | 1998
- 102
-
Deep Sub 1V, SOI or Bulk CMOS?IEEE et al. | 1998
- 104
-
Will Power Limit Microprocessor Performance?IEEE et al. | 1998
- 108
-
An 85W Asynchronous Filter-Bank for a Digital Hearing AidNielsen, L. / Sparsoe, J. / IEEE et al. | 1998
- 108
-
A 85 /spl mu/W asynchronous filter-bank for a digital hearing aidNielsen, F. / Sparso, J. et al. | 1998
- 110
-
A 1 Mbs energy/security scalable encryption processor using adaptive width and supplyChandrakasan, A.P. et al. | 1998
- 112
-
A 1V 350W Voice-Controlled H.263 Video Decoder for Portable ApplicationsBolcioni, L. / Borgatti, M. / Felici, M. / Rambaldi, R. / IEEE et al. | 1998
- 112
-
A 1 V 350 /spl mu/W voice-controlled H.263 video decoder for portable applicationsBorgatti, M. / Felici, M. / Rambaldi, R. / Guerrieri, R. et al. | 1998
- 114
-
A 0.4 W mixed-signal digital storage oscilloscope processor with Moire prevention, embedded 393 kb RAM and 50 M sample/s 8b ADCVertregt, M. / Rey, W. / Boonen, M. / Verhaegh, J. / Wiertsema, W. et al. | 1998
- 116
-
An 0.8m CMOS Mixed Analog-Digital Integrated Audiometric SystemBrigati, S. / Francesconi, F. / Grassi, G. / Lissoni, D. / IEEE et al. | 1998
- 116
-
An 0.8 mu m CMOS mixed analog-digital integrated audiometric systemBrigati, S. / Francesconi, F. / Grassi, G. / Lissoni, D. / Malcovati, P. / Nobile, A. / Poletti, M. / Maloberti, F. et al. | 1998
- 116
-
An 0.8 /spl mu/m CMOS mixed analog-digital integrated audiometric systemBrigati, S. / Grassi, G. / Lissoni, D. / Nobile, A. / Poletti, M. / Maloberti, F. et al. | 1998
- 118
-
A high precision 1024-point FFT processor for 2D convolutionWosnitza, M. / Cavadini, M. / Thaler, M. / Troster, G. et al. | 1998
- 122
-
A 115 mW CMOS GPS receiverShaeffer, D. / Shahani, A. / Mohan, S. / Samavati, H. / Rategh, H. / Hershenson, M. / Xu, M. / Yue, C. / Eddleman, D. / Lee, T. et al. | 1998
- 124
-
A 900 MHz/1.8 GHz CMOS receiver for dual band applicationsWu, S. / Razavi, B. et al. | 1998
- 126
-
A direct conversion L-band tuner for digital DBSBrett, S. / Stanton, G. et al. | 1998
- 128
-
A 2 V, 600 mA, 1 GHz, BiCMOS super-regenerative receiverFavre, P. / Joehl, N. / Declercq, M. / Dehollain, C. / Deval, P. et al. | 1998
- 130
-
A global car radio IC with inaudible signal quality checksKianush, K. / Vaucher, C. et al. | 1998
- 132
-
A fully integrated CMOS 900 MHz LNA utilizing monolithic transformersZhou, J.-J. / Allstot, D.J. et al. | 1998
- 134
-
4GHz and 13GHz Tuned Amplifiers Implemented in a 0.1m CMOS Technology on SOI and SOS SubstratesKim, K.-H. / Ho, Y.-C. / Floyd, B. / Wann, C. / IEEE et al. | 1998
- 134
-
4GHz and 13GHz Tuned Amplifiers Implemented in a 0.1m CMOS Technology on SOl and SOS SubstratesKim, K.-H. / Ho, Y.-C. / Floyd, B. / Wann, C. / IEEE et al. | 1998
- 134
-
4 GHz and 13 GHz tuned amplifiers implemented in a 0.1 mu m CMOS technology on SOI and SOS substratesKim, K.H. / Ho, Y.C. / Floyd, B. / Wann, C. / Taur, Y. / Lagnado, I. et al. | 1998
- 134
-
4 GHz and 13 GHz tuned amplifiers implemented in a 0.1 /spl mu/m CMOS technology on SOI and SOS substratesKim, K.-H. / Ho, Y.-C. / Floyd, B. / Wann, C. / Taur, Y. / Lagnado, I. et al. | 1998
- 138
-
A single-ended 12 b 20 M sample/s self-calibrating pipeline A/D converterOpris, I. / Lewicki, L. / Wong, B. et al. | 1998
- 140
-
Digital background calibration of a 10 b 40 M sample/s parallel pipelined ADCFu, D. / Dyer, K. / Lewis, S. / Hurst, P. et al. | 1998
- 142
-
Analog background calibration of a 10 b 40 Msample/s parallel pipelined ADCDyer, K. / Fu, D. / Lewis, S. / Hurst, P. et al. | 1998
- 144
-
A continuously-calibrated 10 M sample/s 12 b 3.3 V ADCIngino, J. / Wooley, B. et al. | 1998
- 146
-
8 b 75 M sample/s 70 mW parallel pipelined ADC incorporating double samplingBright, W. et al. | 1998
- 148
-
A 5.75 b 350 M sample/s or 6.75 b 150 M sample/s reconfigurable flash ADC for a PRML read channelSetty, P. / Barner, J. / Plany, J. / Burger, H. / Sonntag, J. et al. | 1998
- 150
-
A 400 M sample/s 6b CMOS folding and interpolating ADCFlynn, M. / Sheahan, B. et al. | 1998
- 152
-
FA 9.8: Data Conversion A CMOS 6b 400MSample/s ADC with Error CorrectionTsukamoto, S. / Endo, T. / Schofield, W. G. / IEEE et al. | 1998
- 152
-
A CMOS 6b 400 M sample/s ADC with error correctionTsukamoto, S. / Endo, T. / Schofield, W.G. et al. | 1998
- 152
-
Data Conversion A CMOS 6b 400MSample/s ADC with Error CorrectionTsukamoto, S. / Endo, T. / Schofield, W. G. / IEEE et al. | 1998
- 156
-
A process independent 800 MB/s DRAM bytewide interface featuring command interleaving and concurrent memory operationGriffin, M. / Zerbe, J. / Chan, A. / Jun, Y.-H. / Tanaka, Y. / Richardson, W. / Tsang, G. / Ching, M. / Portmann, C. / Li, Y.-X. et al. | 1998
- 158
-
A 640 MB/s bi-directional data strobed, double-data-rate SDRAM with a 40 mW DLL circuit for a 256 MB memory systemKim, C. / Lee, J. / Park, C. / Roh, J. / Nam, H. / Jung, T. / Cho, S. et al. | 1998
- 160
-
Source synchronization and timing Vernier techniques for 1.2 GB/s SLDRAM interfaceMorooka, Y. / Nakase, Y. / Choi, J.-M. / Shin, H.J. / Perlman, D.J. / Kolor, D.J. / Yoshimura, T. / Watanabe, N. / Matsuda, Y. / Kumanoya, M. et al. | 1998
- 160
-
Source Synchronization and Timing Vernier Techniques for 1.2GB/s SLBRAM InterfaceMorooka, Y. / Nakase, Y. / Choi, J.-M. / Shin, H. J. / IEEE et al. | 1998
- 162
-
A 2.6 GB/s multi-purpose chip-to-chip interfaceLau, B. / Chan, Y.-F. / Moncayo, A. / Ho, J. / Allen, M. / Salmon, J. / Liu, J. / Muthal, M. / Lee, C. / Nguyen, T. et al. | 1998
- 164
-
PRD-based global-mean-time signaling for high-speed chip-to-chip communicationsTamura, H. / Gotoh, K. / Araki, H. / Wakayama, S. / Cheung, T.S. / Saito, M. / Ogawa, J. / Kato, Y. / Nishi, T. / Kawano, M. et al. | 1998
- 168
-
A 200mW 3.3V CMOS Color Camera IC Producing 352x288 24b Video at 30Frames/sLoinaz, M. / Singh, K. / Blanksby, A. / Inglis, D. / IEEE et al. | 1998
- 168
-
A 200 mW 3.3 V CMOS color camera IC producing 352/spl times/288 24 b video at 30 frames/sLoinaz, M. / Singh, K. / Blanksby, A. / Inglis, D. / Azadet, K. / Ackland, B. et al. | 1998
- 170
-
A Single-Chip 306x244-Pixel CMOS NTSC Video CameraSmith, S. / Hurwitz, J. / Torrie, U. / Baxter, D. / IEEE et al. | 1998
- 170
-
A single-chip 306/spl times/244-pixel CMOS NTSC video cameraSmith, S. / Hurwitz, J. / Torrie, M. / Baxter, D. / Holmes, A. / Panaghiston, M. / Henderson, R. / Murray, A. / Anderson, S. / Denyer, P. et al. | 1998
- 172
-
A 37/spl times/28 mm/sup 2/ 600k-pixel CMOS APS dental X-ray camera-on-a-chip with self-triggered readoutFossum, E.R. / Nixon, R.H. / Schick, D. et al. | 1998
- 172
-
A 37x28mm^2 600k-Pixel CMOS APS Dental X-Ray Camera-on-a-Chip with Self-Triggered ReadoutFossum, E. R. / Nixon, R. H. / Schick, D. / IEEE et al. | 1998
- 174
-
A CMOS imager with on-chip variable resolution for light-adaptive imagingZhou, Z. / Pain, B. / Fossum, E. et al. | 1998
- 176
-
A 256/spl times/256 CMOS imaging array with wide dynamic range pixels and column-parallel digital outputDecker, S. / McGrath, R. / Brehmer, K. / Sodini, C. et al. | 1998
- 176
-
A 256x256 CMOS Imaging Array with Wide Dynamic Range Pixels and Column-Parallel Digital OutputDecker, S. / McGrath, R. / Brehmer, K. / Sodini, C. / IEEE et al. | 1998
- 178
-
A 1/2 inch 1.3 M-pixel progressive-scan IT-CCD for still and motion picture applicationsYamada, T. / Hatano, K. / Morimoto, M. / Nakashiba, Y. / Uchiya, S. / Tanabe, A. / Kawakami, Y. / Nakano, T. / Kawai, S. / Suwazono, S. et al. | 1998
- 180
-
A 1 mm 50 K-pixel IT CCD image sensor for miniature camera systemItakura, K. / Nobusada, T. / Kokusenya, N. / Nagayoshi, R. / Ozaki, M. et al. | 1998
- 182
-
A 3.7x3.7m^2 Square Pixel CMOS Image Sensor for Digital Still Camera ApplicationIhara, H. / Yamashita, H. / Inoue, I. / Yamaguchi, T. / IEEE et al. | 1998
- 182
-
A 3.7/spl times/3.7 /spl mu/m/sup 2/ square pixel CMOS image sensor for digital still camera applicationIhara, H. / Yamashita, H. / Inoue, I. / Yamaguchi, T. / Nozaki, H. et al. | 1998
- 186
-
Toward sub 1 V analog integrated circuits in submicron standard CMOS technologiesSansen, W. / Steyaert, M. / Peluso, V. / Peeters, E. et al. | 1998
- 186
-
Toward Sub IV Analog Integrated Circuits in Submicron Standard CMOS TechnologiesSansen, W. / Steyaert, M. / Peluso, V. / Peeters, E. / IEEE et al. | 1998
- 188
-
0.5 V 320 MHz 8 b multiplexer/demultiplexer chips based on a gate array with regular-structured DTMOS/SOIHirota, T. / Ueda, K. / Wada, Y. / Mashiko, K. / Hamano, H. et al. | 1998
- 190
-
A Sub-IV Triple-Threshold CMOS/SIMOX Circuit for Active Power ReductionFujii, K. / Douseki, T. / Harada, M. / IEEE et al. | 1998
- 190
-
FP 12.3: A Sub-1V Triple-Threshold CMOS/SIMOX Circuit for Active Power ReductionFujii, K. / Douseki, T. / Harada, M. / IEEE et al. | 1998
- 190
-
A sub-1 V triple-threshold CMOS/SIMOX circuit for active power reductionFujii, K. / Douseki, T. / Harada, M. et al. | 1998
- 192
-
A CMOS scheme for 0.5 V supply voltage with pico-ampere standby currentKawaguchi, H. / Nose, K.-I. / Sakurai, T. et al. | 1998
- 194
-
Multiple-valued logic-in-memory VLSI based on a floating-gate-MOS pass-transistor networkHanyu, T. / Teranishi, K. / Kameyama, M. et al. | 1998
- 196
-
1.5 TXPS convolver using 5b analog flash for real-time large-kernel image filteringKramer, A. / Fabbrizio, V. / Mariaud, X. / Raynal, F. et al. | 1998
- 200
-
A 70 Mb/s variable-rate 1024-QAM cable receiver IC with integrated 10 b ADC and FEC decoderTan, L. / Putnam, J. / Lu, F. / D'Luna, L. / Mueller, D. / Kindsfater, K. / Cameron, K. / Joshi, R. / Hawley, R. / Samueli, H. et al. | 1998
- 202
-
A 10 Gb/s SiGe bipolar framer/demultiplexer for SDH systemsShioiri, S. / Soda, M. / Morikawa, T. / Hashimoto, T. / Sato, F. / Emura, K. et al. | 1998
- 202
-
FP 13.2: A 10Gb/s SiGe Bipolar Framer/Demultiplexer for SDH SystemsShioiri, S. / Soda, M. / Morikawa, T. / Hashimoto, T. / IEEE et al. | 1998
- 204
-
A 2V 120mA 25Gb/s 2x2 Crosspoint Switch in InP-HBT TechnologyMokhtari, M. / Kerzar, B. / Juhola, T. / Schuppener, G. / IEEE et al. | 1998
- 204
-
A 2 V 120 mA 25 Gb/s 2/spl times/2 crosspoint switch in InP-HBT technologyMokhtari, M. / Kerzar, B. / Juhola, T. / Schuppener, G. / Tenhunen, H. / Swahn, T. / Walden, R. et al. | 1998
- 206
-
A 3.3V 20-Channel 500Mb/s/ch Optical Receiver with Integrated Optical Detectors in 1.2m GaAsYang, J. / Choi, J.-H. / Kuchta, D. / Stawiasz, K. / IEEE et al. | 1998
- 206
-
A 3.3 V 20-channel 500 Mb/s/ch optical receiver with integrated optical detectors in 1.2 mm GaAsYang, J. / Choi, J.-H. / Kuchta, D. / Stawiasz, K. / Pepeljugoski, P. / Ainspan, H. et al. | 1998
- 208
-
A 100 Mb/s CMOS 100Base-T4 Fast Ethernet transceiver for category 3, 4 and 5 UTPChan, K. / Berman, M. / Kruse, D. / Lu, F. / Tran, H. / Yousefi, N. / Samueli, H. et al. | 1998
- 210
-
A 10/100 Mb/s CMOS Ethernet transceiver for 10BaseT, 100BaseTX, and 100BaseFXEveritt, J. / Parker, J. / Hurst, P. / Nack, D. / Konda, K. / Raad, C. et al. | 1998
- 214
-
A 10b 250MSample/s CMOS DAC in 1mm^2Lin, C.-H. / Bult, K. / IEEE et al. | 1998
- 214
-
A 10 b 250 M sample/s CMOS DAC in 1 mm/sup 2/Lin, C.-H. / Bult, K. et al. | 1998
- 216
-
A 12 b accuracy 300 Msample/s update rate CMOS DACMarques, A. / Bastos, J. / Van den Bosch, A. / Vandenbussche, J. / Steyaert, M. / Sansen, W. et al. | 1998
- 218
-
A practical quality factor tuning scheme for IF and high-Q continuous-time filtersStevenson, J.-M. / Sanchez-Sinencio, E. et al. | 1998
- 220
-
A 2.7V 200kHz 49dBm-IIP3 28nV/VHz Input-Referred-Noise Fully-Balanced Gm-C Filter ICItakura, T. / Ueno, T. / Tanimoto, H. / Yasuda, A. / IEEE et al. | 1998
- 220
-
A 2.7V 200kHz 49dBm-IIP3 28nV/Hz Input-Referred-Noise Fully-Balanced Gm-C Filter ICItakura, T. / Ueno, T. / Tanimoto, H. / Yasuda, A. / IEEE et al. | 1998
- 220
-
A 2.7 V 200 kHz 49 dBm-IIP3 28 nV//spl radic/Hz input-referred-noise fully-balanced gm-C filter ICItakura, T. / Ueno, T. / Tanimoto, H. / Yasuda, A. / Fujimoto, R. / Arai, T. / Kokatsu, H. et al. | 1998
- 222
-
A 20-800 MHz relaxation oscillator with automatic swing controlSowlati, T. / Shakiba, H. et al. | 1998
- 224
-
A fully integrated VCO at 2 GHzZannoth, M. / Kolb, B. / Fenk, J. / Weigel, R. et al. | 1998
- 224
-
FP 14.6: A Fully Integrated VCO at 2GHzZannoth, M. / Kolb, B. / Fenk, J. / Weigel, R. / IEEE et al. | 1998
- 226
-
A Fully Integrated 2.7V 0.35m CMOS VCO for 5GHz Wireless ApplicationsKinget, P. / IEEE et al. | 1998
- 226
-
A fully integrated 2.7 V 0.35 /spl mu/m CMOS VCO for 5 GHz wireless applicationsKinget, P. et al. | 1998
- 230
-
A 1.0 GHz single-issue 64 b powerPC integer processorSilberman, J. / Aoki, N. / Boerstler, D. / Burns, J. / Dhong, S. / Essbaum, A. / Heidel, D. / Hofstee, P. / Lee, K. / Meltzer, D. et al. | 1998
- 230
-
FP 15.1: A 1.0GHz Single-Issue 64b PowerPC Integer ProcessorSilberman, J. / Aoki, N. / Boerstler, Q. / Burns, J. / IEEE et al. | 1998
- 232
-
Design tradeoffs in stall-control circuits for 600 MHz instruction queuesFischer, T. / Leibholz, D. et al. | 1998
- 234
-
A commercial multithreaded RISC processorStorino, S. / Aipperspach, A. / Borkenhagen, J. / Eickemeyer, R. / Kunkel, S. / Levenstein, S. / Uhlmann, G. et al. | 1998
- 236
-
A 450 MHz IA32 P6 family microprocessorSchutz, J. / Wallace, R. et al. | 1998
- 238
-
A 200 MHz 32 b 0.5 W CMOS RISC microprocessorStephany, R. / Anne, K. / Bell, J. / Cheney, G. / Eno, J. / Hoeppner, G. / Joe, G. / Kaye, R. / Lear, J. / Litch, T. et al. | 1998
- 238
-
FP 15.5: A 200MHz 32b 0.5W CMOS RISC MicroprocessorStephany, R. / Anne, K. / Bell, J. / Cheney, G. / IEEE et al. | 1998
- 240
-
A 480MHz RISC Microprocessor in a 0.12m L~o~f~f CMOS Technology with Copper InterconnectsRohrer, N. / Akrout, C. / Canada, M. / Cawthron, D. / IEEE et al. | 1998
- 240
-
A 480MHz RISC Microprocessor in a 0.12m L~e~f~f CMOS Technology with Copper InterconnectsRohrer, N. / Akrout, C. / Canada, M. / Cawthron, D. / IEEE et al. | 1998
- 240
-
A 480 MHz RISC microprocessor in a 0.12 /spl mu/m L/sub eff/ CMOS technology with copper interconnectsRohrer, N. / Akrout, C. / Canada, M. / Cawthron, D. / Floyd, R. / Geissler, S. / Goldblatt, R. / Houle, R. / Kartschoke, P. / Kramer, D. et al. | 1998
- 240
-
A 480 MHz RISC microprocessor in a 0.12 mu m Leff CMOS technology with copper interconnectsRohrer, N. / Akrout, C. / Canada, M. / Cawthron, D. / Davari, B. / Floyd, R. / Geissler, S. / Goldblatt, R. / Houle, R. / Kartschoke, P. et al. | 1998
- 242
-
A 0.25m x86 Microprocessor with a 100MHz Socket 7 InterfaceKhanna, R. / Ben-Meir, A. / DiGregorio, L. / Draper, D. / IEEE et al. | 1998
- 242
-
A 0.25 mm x86 microprocessor with a 100 MHz socket 7 interfaceKhanna, R. / Ben-Meir, A. / DiGregorio, L. / Draper, D. / Krishna, R. / Maley, R. / Mehta, A. / Oberman, S. / Tsai, L. / Williams, T. et al. | 1998
- 246
-
FP 16.1: RF Circuit Design Aspects of Spiral Inductors on SiliconBurghartz, J. / Edelstein, D. / Soyuer, U. / Ainspan, H. / IEEE et al. | 1998
- 246
-
RF circuit design aspects of spiral inductors on siliconBurghartz, J. / Edelstein, D. / Ainspan, H. / Jenkins, K. et al. | 1998
- 248
-
Silicon-on-silicon integration of a GSM transceiver with VCO resonatorDavis, P. / Smith, P. / Campbell, E. / Lin, J. / Gross, K. / Bath, G. / Low, Y. / Lau, M. / Degani, Y. / Gregus, J. et al. | 1998
- 250
-
A 3.5 mW 2.5 GHz diversity receiver and a 1.2 mW 3.6 GHz VCO in silicon-on-anythingWagemans, A. / Dekker, R. / Hoogstraate, A. / Maas, H. / Tombeur, A. / Van Sinderen, J. et al. | 1998
- 252
-
K-band Si MMIC amplifier and mixer using three-dimensional masterslice MMIC technologyNishikawa, K. / Toyoda, I. / Kamogawa, K. / Tokumitsu, T. / Yamaguchi, C. / Hirano, M. et al. | 1998
- 254
-
RF perspective of sub-tenth-micron CMOSWann, C. / Su, L. / Jenkins, K. / Chang, R. / Frank, D. / Taur, Y. et al. | 1998
- 256
-
Fractal capacitorsSamavati, H. / Hajimiri, A. / Shahani, A. / Nasserbakht, G. / Lee, T. et al. | 1998
- 258
-
Muiti-GHz A/D Converter using Resonant-Tunneling Multiple-Valued Logic CircuitsWaho, T. / Itoh, T. / Maezawa, K. / Yamamoto, M. / IEEE et al. | 1998
- 258
-
Multi-GHz A/D converter using resonant-tunnelling multiple-valued logic circuitsWaho, T. / Itoh, T. / Maezawa, K. / Yamamoto, M. et al. | 1998
- 258
-
Multi-GHz A/D Converter using Resonant-Tunneling Multiple-Valued Logic CircuitsWaho, T. / Itoh, T. / Maezawa, K. / Yamamoto, M. / IEEE et al. | 1998
- 262
-
Will CMOS Image Sensors Survive Scaling?IEEE et al. | 1998
- 264
-
How will Media Signal Processors Dominate the Next Decade?IEEE et al. | 1998
- 266
-
LSI Solutions and Enabling Technologies for Mobile Multimedia Devices in the Year 2002IEEE et al. | 1998
- 268
-
Global Communications: the Good, the Bad, and the UglyIEEE et al. | 1998
- 272
-
Active CMOS biochips: an electro-addressed DNA probeBelleville, M. / Clerc, F. / Massit, C. et al. | 1998
- 274
-
An active charge-cancellation system for switched-capacitor sensor interface circuitsSchiffer, B. / Burstein, A. / Kaiser, W. et al. | 1998
- 276
-
An IEEE 1451 standard transducer interface chipCummins, T. / Brannick, D. / Byrne, E. / O'Mara, B. / Stapleton, H. / Cleary, J. / O'Riordan, J. / Lynch, D. / Noonan, L. / Dempsey, D. et al. | 1998
- 278
-
A 16A Interface Circuit for a Capacitive Flow SensorRodgers, B. / Goenewan, S. / Yunus, M. / Kaneko, Y. / IEEE et al. | 1998
- 278
-
A 16 mu A interface circuit for a capacitive-flow sensorRodgers, B. / Goenawan, S. / Yunas, M. / Kaneko, Y. / Yoshlike, J. et al. | 1998
- 278
-
A 16 /spl mu/A interface circuit for a capacitive-flow sensorRodgers, B. / Goenawan, S. / Kaneko, Y. / Yoshlike, J. et al. | 1998
- 280
-
Monolithic 4-20 mA isolating current replicator using GMR resistorsBlack, W. / Hermann, T. et al. | 1998
- 282
-
A 256/spl times/256 BCAST motion detector with simultaneous video outputNomura, H. / Shima, T. / Kamashita, A. / Ishida, T. / Yoneyama, T. et al. | 1998
- 282
-
A 256x256 BCAST Motion Detector with Simultaneous Video OutputNomura, H. / Shima, T. / Kamashita, A. / Ishida, T. / IEEE et al. | 1998
- 284
-
A Robust, 1.8V 250mW Direct-Contact 500dpi Fingerprint SensorInglis, D. / Manchanda, L. / Comizzoli, R. / Dickinson, A. / IEEE et al. | 1998
- 284
-
A Robust, 1.8V 260mW Direct-Contact 500dpi Fingerprint SensorInglis, D. / Manchanda, L. / Comizzoli, R. / Dickinson, A. / IEEE et al. | 1998
- 284
-
A robust, 1.8 V 250 /spl mu/W direct-contact 500 dpi fingerprint sensorInglis, C. / Manchanda, L. / Dickinson, A. / Martin, E. / Weber, G. / Ackland, B. / O'Gorman, L. et al. | 1998
- 288
-
A 200 MHz 1.2 W 1.4 GFLOPS microprocessor with graphic operation unitNishii, O. / Arakawa, F. / Ishibashi, K. / Nakano, S. / Shimura, T. / Suzuki, K. / Tachibana, M. / Totsuka, Y. / Tsunoda, T. / Uchiyama, K. et al. | 1998
- 290
-
A 1.2W 2.16 GOP/720 MFLOPS Embedded Superscalar Microprocessor for Multimedia ApplicationKubosawa, H. / Takahashi, H. / Ando, S. / Asada, Y. / IEEE et al. | 1998
- 290
-
A 1.2 W 2.16 GOPS/720 MFLOPS embedded superscalar microprocessor for multimedia applicationsKubosawa, H. / Takahashi, H. / Ando, S. / Asada, Y. / Asato, A. / Suga, A. / Kimura, M. / Higaki, N. / Miyake, H. / Sato, T. et al. | 1998
- 292
-
An 800 MOPS 110 mW 1.5 V parallel DSP for mobile multimedia processingIgura, H. / Narita, S. / Naito, Y. / Kazama, K. / Kuroda, I. / Motomura, M. / Yamashina, M. et al. | 1998
- 294
-
A 667 MHz RISC microprocessor containing a 6.0 ns 64 b integer multiplierCarlson, D. / Jain, A. / Bannon, P. / Benninghoff, T. / Bertone, M. / Blake-Campos, R. / Bouchard, G. / Brasili, D. / Castelino, R. / Lilly, B. et al. | 1998
- 296
-
A 2.7ns 0.25m CMOS 54x54b MultiplierHagihara, Y. / Inui, S. / Yoshikawa, A. / Nakazato, S. / IEEE et al. | 1998
- 296
-
A 2.7ns 0.25m CMOS 64x54b MultiplierHagihara, Y. / Inui, S. / Yoshikawa, A. / Nakazato, S. / IEEE et al. | 1998
- 296
-
A 2.7 ns 0.25 /spl mu/m CMOS 54/spl times/54 b multiplierHagihara, Y. / Inui, S. / Yoshikawa, A. / Nakazato, S. / Iriki, S. / Ikeda, R. / Shibue, Y. / Inaba, T. / Kagamihara, M. / Yamashina, M. et al. | 1998
- 298
-
A low-cost 300 MHz RISC CPU with attached media processorSanthanam, S. / Baum, A. / Bertucci, D. / Braganza, M. / Broch, K. / Broch, T. / Burnette, J. / Chang, E. / Dobberpuhl, D. / Donahue, P. et al. | 1998
- 302
-
A 10Gb/s Si-Bipolar TX/RX Chipset for Computer Data TransmissionWalker, R. / Hsieh, K.-C. / Knotts, T. / Yen, C.-S. / IEEE et al. | 1998