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Cost-Effective and Variable-Channel FastICA Hardware Architecture and Implementation for EEG Signal Processing
British Library Online Contents | 2016| -
Digital Circuits and Systems - Generalized Low-Error Area-Efficient Fixed-Width Multipliers
Online Contents | 2005| -
A New 2-D Systolic Digital Filter Architecture Without Global Broadcast
British Library Online Contents | 2002| -
TRANSACTIONS BRIEFS - Design of the Lower Error Fixed-Width Multiplier and Its Application
Online Contents | 2000| -
A Power-Area Efficient Geometry Engine With Low-Complexity Subdivision Algorithm for 3-D Graphics System
British Library Online Contents | 2011| -
Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers
British Library Online Contents | 2009| -
Generalized Low-Error Area-Efficient Fixed-Width Multipliers
British Library Online Contents | 2005| -
An Improved NoC Design Methodology Using Latency-Guarantee Network Architecture and Communication-Contention-Aware Cost Function
British Library Online Contents | 2012| -
Energy-Efficient FastICA Implementation for Biomedical Signal Separation
British Library Online Contents | 2011| -
An Efficient Systolic Architecture for the DLMS Adaptive Filter and Its Applications
British Library Online Contents | 2001| -
Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor
British Library Online Contents | 2008| -
PIPELINED RLS ADAPTIVE ARCHITECTURE USING RELAXED GIVENS ROTATIONS (RGR)
British Library Conference Proceedings | 2002| -
VLSI Architecture for the Low-Computation Cycle and Power-Efficient Recursive DFT/IDFT Design
British Library Online Contents | 2007| -
A GENERALIZED METHODOLOGY FOR LOWER-ERROR AREA-EFFICIENT FIXED-WIDTH MULTIPLIERS
British Library Conference Proceedings | 2002|
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