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An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs
Springer Verlag | 2006| -
An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs
Online Contents | 2006| -
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories
Online Contents | 2005| -
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions
Online Contents | 2006| -
Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives
Springer Verlag | 2005| -
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories
Springer Verlag | 2005|
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