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Review of Circuit Level Leakage Minimization Techniques in CMOS VLSI Circuits
Taylor & Francis Verlag | 2017| -
Performance Comparison of 1-Bit Conventional and Hybrid Full Adder Circuits
Springer Verlag | 2018| -
Dynamic Threshold Sleep Transistor Technique for High Speed and Low Leakage in CMOS Circuits
Online Contents | 2016| -
Dynamic Threshold Sleep Transistor Technique for High Speed and Low Leakage in CMOS Circuits
Springer Verlag | 2016| -
Dynamic Threshold Sleep Transistor Technique for High Speed and Low Leakage in CMOS Circuits
Online Contents | 2016| -
Comparative analysis of texture feature extraction techniques for rice grain classification
Free accessWiley | 2020| -
Comparative analysis of texture feature extraction techniques for rice grain classification
Free accessIET | 2020|
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