IEEE transactions on advanced packaging : a publication of the IEEE Components, Packaging, and Manufacturing Technology Society and the Lasers and Electro-Optics Society
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
Table of contents
- 2
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Foreword Wafer Level Packaging: More of ManyNguyen, Luu T. et al. | 2008
- 4
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SPECIAL SECTION PAPERS - Integrating Through-Wafer Interconnects With Active Devices and CircuitsJozwiak, J. et al. | 2008
- 4
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Integrating Through-Wafer Interconnects With Active Devices and CircuitsJozwiak, J. / Southwick, R.G. / Johnson, V.N. et al. | 2008
- 14
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On Ultra-Fine Leak Detection of Hermetic Wafer Level PackagesGoswami, A. / Bongtae Han, et al. | 2008
- 22
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Low-K Dielectric Compatible Wafer-Level Compliant Chip-to-Substrate InterconnectsKacker, K. / Lo, G.C. / Sitaraman, S.K. et al. | 2008
- 33
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Electrophoretic Materials in Wafer Level Packages for Solid State Imagers to Meet Automotive Reliability StandardsHumpston, G. / Rosenstein, C. / Axelrod, E. et al. | 2008
- 39
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Advanced Packaging: The Redistributed Chip PackageKeser, B. / Amrine, C. / Trung Duong, et al. | 2008
- 44
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Development of 3-D Stack Package Using Silicon Interposer for High-Power ApplicationKhan, N. / Seung Wook Yoon, / Viswanath, A.G.K. et al. | 2008
- 51
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Influence of Intermetallic Properties on Reliability of Lead-Free Flip-Chip Solder JointsLimaye, P. / Vandevelde, B. / Labie, R. et al. | 2008
- 58
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150-mm Pitch Cu-Low-k Flip Chip Packaging With Polymer Encapsulated Dicing Line (PEDL) and Cu Column InterconnectsYoon, S.W. et al. | 2008
- 58
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150- Formula Not Shown Pitch Cu/Low- Formula Not Shown Flip Chip Packaging With Polymer Encapsulated Dicing Line (PEDL) and Cu Column InterconnectsYoon, S.W. / Thew, S.M.L. / Lim, S.Y.L. et al. | 2008
- 58
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150-$\mu{\rm m}$ Pitch Cu/Low-${\rm k}$ Flip Chip Packaging With Polymer Encapsulated Dicing Line (PEDL) and Cu Column InterconnectsSeung Wook Yoon, / Thew, S.M.L. / Lim, S.Y.L. et al. | 2008
- 66
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Evaluation on Influencing Factors of Board-Level Drop Reliability for Chip Scale Packages (Fine-Pitch Ball Grid Array)Chong, D.Y.R. / Che, F.X. / Pang, J.H.L. et al. | 2008
- 76
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A Random Trimming Approach for Obtaining High-Precision Embedded ResistorsSandborn, P. / Sandborn, P.A. et al. | 2008
- 82
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High-Speed Flex-Circuit Chip-to-Chip InterconnectsBraunisch, H. / Jaussi, J.E. / Mix, J.A. et al. | 2008
- 91
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Interfacial Fracture Investigation of Low-k Packaging Using J-Integral MethodologyChang-Chun Lee, / Tai-Chun Huang, / Chin-Chiu Hsia, et al. | 2008
- 100
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Measurement of Surface Tension of Epoxy Resins Used in Dispensing Process for Manufacturing Thin Film Transistor-Liquid Crystal DisplaysChin-Hsiang Cheng, / Hung-Hsiang Lin, et al. | 2008
- 107
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Analyzing the Value of Using Three-Dimensional Electronics for a High-Performance Computational SystemMountain, D.J. et al. | 2008
- 118
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Structural Modal Analysis for Detecting Open Solder Bumps on Flip ChipsErdahl, D.S. / Allen, M.S. / Ume, I.C. et al. | 2008
- 127
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Reliability of a Silicon Stacked Module for 3-D SiP MicrosystemSeung Wook Yoon, / Lim, S.Y.L. / Viswanath, A.G.K. et al. | 2008
- 135
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Design and Analysis of Shock-Absorbing Structure for Flat Panel DisplayChih-Chun Cheng, / Tsai, T.D. / Lin, D.W. et al. | 2008
- 143
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Mechanically Flexible Chip-to-Substrate Optical Interconnections Using Optical PillarsBakir, M.S. / Glebov, A.L. / Lee, M.G. et al. | 2008
- 154
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Efficient Full-Wave Characterization of Discrete High-Density Multiterminal Decoupling Capacitors for High-Speed Digital SystemsDan Jiao, / Joong-Ho Kim, / Jiangqi He, et al. | 2008
- 163
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System-on-Packaging with Electroabsorption Modulator for a 60-GHz Band Radio-Over-Fiber LinkKwang-Seong Choi, / Yong-Duck Chung, / Dong-Suk Jun, et al. | 2008
- 170
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Low-Loss and Wideband Package Transitions for Microwave and Millimeter-Wave MCMsKangasvieri, T. / Komulainen, M. / Jantunen, H. et al. | 2008
- 182
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Surface Finish Effects on High-Speed Signal DegradationXin Wu, / Cullen, D. / Brist, G. et al. | 2008
- 190
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Passive Closed-Form Transmission Line Macromodel Using Method of CharacteristicsDounavis, A. / Pothiwala, V.A. et al. | 2008
- 203
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Modeling and Analyzing High-Speed and High-Density Connectors by Using Multisegment Multiple Transmission Lines ModelMu-Shui Zhang, / Yu-Shan Li, / Li-Ping Li, et al. | 2008
- 211
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Design of Reflectionless Vias Using Neural Network-Based ApproachKu-Teng Hsu, / Wei-Da Guo, / Guang-Hwa Shiue, et al. | 2008
- 219
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A Hybrid ADI and SBTD Scheme for Unconditionally Stable Time-Domain Solutions of Maxwell's EquationsZhenyu Huang, / Guangwen Pan, / Diaz, R. et al. | 2008
- 227
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Correction to “A Hybrid Evolutionary Modeling/Optimization Technique for Collector-Up/Down HBTs in RFIC and OEIC Modules”Tseng, Hsien-Cheng et al. | 2008
- 227
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ERRATA - Correction to "A Hybrid Evolutionary Modeling-Optimization Technique for Collector-Up-Down HBTs in RFIC and OEIC Modules"| 2008
- 228
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Order Form for Reprints| 2008
- 229
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Leading the field since 1884| 2008
- 230
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Table of contents| 2008
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IEEE Transactions on Advanced Packaging publication information| 2008
- C3
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IEEE Components, Packaging, and Manufacturing Technology Society Information for authors| 2008
- C4
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IEEE Components, Packaging, and Manufacturing Technology Society Information| 2008
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SPECIAL SECTION ON WAFER LEVEL PACKAGING| 2008