-Particle-Induced Soft Errors in Submicron SOI SRAM (English)
- New search for: Tosaka, Y.
- New search for: Suzuki, K.
- New search for: Sugii, T.
- New search for: IEEE| Japan Society of Applied Physics
- New search for: Tosaka, Y.
- New search for: Suzuki, K.
- New search for: Sugii, T.
- New search for: IEEE| Japan Society of Applied Physics
In:
VLSI technology
1995
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39-40
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1995
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ISBN:
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ISSN:
- Conference paper / Print
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Title:-Particle-Induced Soft Errors in Submicron SOI SRAM
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Contributors:Tosaka, Y. ( author ) / Suzuki, K. ( author ) / Sugii, T. ( author ) / IEEE| Japan Society of Applied Physics
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Conference:50th Symposium, VLSI technology ; 1995 ; Kyoto; Japan
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Published in:VLSI technology , 1995 ; 39-40SYMPOSIUM ON VLSI TECHNOLOGY , 1995 ; 39-40
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Publisher:
- New search for: IEEE
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Publication date:1995-01-01
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Size:2 pages
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Remarks:IEEE cat no 95CH3578-1
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ISBN:
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ISSN:
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Type of media:Conference paper
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Type of material:Print
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Language:English
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Keywords:
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Source:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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Semiconductor CIM system, innovation toward the year 2000Inoue, G. / Asakura, S. / Iiri, M. et al. | 1995
- 1
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Semiconductor CIM System; Innovation Toward The Year 2000 (Invited)Iiri, M. / Inoue, G. / Asakura, S. / IEEE| Japan Society of Applied Physics et al. | 1995
- 5
-
Manufacturing technology challenges for low power electronicsLemnios, Z.J. et al. | 1995
- 5
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Manufacturing Technology Challenges for Low Power Electronics (Invited)Lemnios, Z. J. / IEEE| Japan Society of Applied Physics et al. | 1995
- 9
-
High performance sub-tenth micron CMOS using advanced boron doping and WSi/sub 2/ dual gate processTakeuchi, K. / Yamamoto, T. / Furukawa, A. / Tamura, T. / Yoshida, K. et al. | 1995
- 9
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High Performance Sub-Tenth Micron CMOS Using Advanced Boron Doping and WSi~2 Dual Gate ProcessTakeuchi, K. / Yamamoto, T. / Furukawa, A. / Tamura, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 11
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Silicided Silicon-Sidewall Source and Drain (S^4D) Structure for High-Performance 75-nm Gate Length pMOSFETsYoshitomi, T. / Saito, M. / Ohguro, T. / Ono, M. / IEEE| Japan Society of Applied Physics et al. | 1995
- 11
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Silicided silicon-sidewall source and drain (S/sup 4/D) structure for high-performance 75-nm gate length pMOSFETsYoshitomi, T. / Saito, M. / Ohguro, T. / Ono, M. / Momose, H.S. / Iwai, H. et al. | 1995
- 13
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A 6.93 micron2 n-gate full CMOS SRAM cell technology with high-performance 1.8 V dual-gate CMOS for peripheral circuitsMinami, M. / Ohki, N. / Ishida, H. / Yamanaka, T. / Ishibashi, K. / Shimidu, A. / Kure, T. et al. | 1995
- 13
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A 6.93-m^2 n-Gate Full CMOS SRAM Cell Technology with High-Performance 1.8-V Dual-Gate CMOS for Peripheral CircuitsMinami, M. / Ohki, N. / Ishida, H. / Yamanaka, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 13
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A 6.93-/spl mu/m/sup 2/ n-gate full CMOS SRAM cell technology with high-performance 1.8-V dual-gate CMOS for peripheral circuitsMinami, M. / Ohki, N. / Ishida, H. / Yamanaka, T. / Ishibashi, K. / Shimizu, A. / Kure, T. / Nishida, T. / Nagano, T. et al. | 1995
- 15
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A fully planarized 0.25 micron technology for 256 Mbit DRAM and beyondBronner, G. / Aochi, H. / Gall, M. / Gambino, J. / Gernhardt, S. / Hammerl, E. / Ho, H. / Iba, J. et al. | 1995
- 15
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A Fully Planarized 0.25 m CMOS Technology for 256 Mbit DRAM and BeyondBronner, G. / Aochi, H. / Gall, M. / Gambino, J. / IEEE| Japan Society of Applied Physics et al. | 1995
- 15
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A fully planarized 0.25 /spl mu/m CMOS technology for 256 Mbit DRAM and beyondAochi, H. / Gall, M. / Gambino, J. / Hammerl, E. / Ho, H. / Iba, J. / Ishiuchi, H. / Jaso, M. / Kleinhenz, R. / Mii, T. et al. | 1995
- 17
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New CoSi/sub 2/ SALICIDE technology for 0.1 /spl mu/m processes and belowWang, Q.F. / Maex, K. / Kubicek, S. / Jonckheere, R. / Kerkwijk, B. / Verbeeck, R. / Biesemans, S. / De Meyer, K. et al. | 1995
- 17
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New CoSi~2 SALICIDE Technology for 0.1 m Processes and BelowWang, Q. F. / Maex, K. / Kubicek, S. / Jonckheere, R. / IEEE| Japan Society of Applied Physics et al. | 1995
- 17
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New CoSi2 SALICIDE technology for 0.1 micron processes and belowWang, Q.F. / Maex, K. / Kubicek, S. / Jonckheere, R. / Kerkwijk, B. / Verbeeck, R. et al. | 1995
- 19
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Highly reliable 0.15 /spl mu/m MOSFETs with Surface Proximity Gettering (SPG) and nitrided oxide spacer using nitrogen implantationKuroi, T. / Shimizu, S. / Furukawa, A. / Komori, S. / Kawasaki, Y. / Kusunoki, S. / Okumura, Y. / Inuishi, N. / Tsubouchi, N. / Horie, K. et al. | 1995
- 19
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Highly Reliable 0.15 m MOSFETs with Surface Proximity Gettering(SPG) and Nitrided Oxide Spacer Using Nitrogen ImplantationKuroi, T. / Shimizu, S. / Furukawa, A. / Komori, S. / IEEE| Japan Society of Applied Physics et al. | 1995
- 21
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The Influence of Oxygen at Epitaxial Si/Si Substrate Interface for 0.1 m Epitaxial Si Channel N-MOSFETs Grown by UHV-CVDOhguro, T. / Sugiyama, N. / Imai, K. / Usuda, K. / IEEE| Japan Society of Applied Physics et al. | 1995
- 21
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The influence of oxygen at epitaxial Si/Si substrate interface for 0.1 /spl mu/m epitaxial Si channel N-MOSFETs grown by UHV-CVDOhguro, T. / Sugiyama, N. / Imai, K. / Usuda, K. / Saito, M. / Yoshitomi, T. / Ono, M. / Momose, H.S. / Iwai, H. et al. | 1995
- 23
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A Channel Engineering Combined with Channel Epitaxy Optimization and TED Suppression for 0.15 m n-n Gate CMOS TechnologyAbiko, H. / Ono, A. / Ueno, R. / Masuoka, S. / IEEE| Japan Society of Applied Physics et al. | 1995
- 23
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A channel engineering combined with channel epitaxy optimization and TED suppression for 0.15 /spl mu/m n-n gate CMOS technologyAbiko, H. / Ono, A. / Ueno, R. / Masuoka, S. / Shishiguchi, S. / Nakajima, K. / Sakai, I. et al. | 1995
- 25
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Copper integration into 0.5 /spl mu/m BiCMOS technologyGelatos, A.V. / Nguyen, B.-Y. / Perry, K. / Marsh, R. / Peschke, J. / Filipiak, S. / Travis, E. / Bhat, N. / La, L.B. / Thompson, M. et al. | 1995
- 25
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Copper integration into 0.5 micron BiCMOS technologyGelatos, A.V. / Nguyen, B.Y. / Perry, K. / Marsh, R. / Peschke, J. / Filipiak, S. / Travis, E. / Bhat, N. et al. | 1995
- 25
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Copper Integration into 0.5 m BiCMOS TechnologyGelatos, A. V. / Nguyen, B.-Y. / Perry, K. / Marsh, R. / IEEE| Japan Society of Applied Physics et al. | 1995
- 27
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A half-micron pitch Cu interconnection technologyUeno, K. / Ohto, K. / Tsunenari, K. et al. | 1995
- 29
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Performance of MOCVD tantalum nitride diffusion barrier for copper metallizationSun, S.C. / Tsai, M.H. / Tsai, C.E. / Chiu, H.T. et al. | 1995
- 31
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A novel self-aligned surface-silicide passivation technology for reliability enhancement in copper interconnectsTakewaki, T. / Ohmi, T. / Nitta, T. et al. | 1995
- 33
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High-Current, Small Parasitic Capacitance MOS FET on a Poly-Si Interlayered (PSI:psi) SOI WaferHoriuchi, M. / Teshima, T. / Tokumasu, K. / Yamaguchi, K. / IEEE| Japan Society of Applied Physics et al. | 1995
- 33
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High-Current, Small Parasitic Capacitance MOS FET on a Poly-Si Interlayered(PSI:cap psi) SOI WaferHoriuchi, M. / Teshima, T. / Tokumasu, K. / Yamaguchi, K. / IEEE| Japan Society of Applied Physics et al. | 1995
- 33
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High-current, small parasitic capacitance MOS FET on a poly-Si interlayered (PSI: /spl Psi/) SOI waferHoriuchi, M. / Teshima, T. / Tokumasu, K. / Yamaguchi, K. et al. | 1995
- 35
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Suppression of the floating-body effects in SOI MOSFETs by bandgap engineeringTerauchi, M. / Yoshimi, M. / Ushiku, Y. et al. | 1995
- 37
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A PELOX isolated sub-0.5 micron thin-film SOI technologyGilbert, P.V. / Sun, S.-W. et al. | 1995
- 39
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/spl alpha/-particle-induced soft errors in submicron SOI SRAMTosaka, Y. / Suzuki, K. / Sugii, T. et al. | 1995
- 39
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-Particle-Induced Soft Errors in Submicron SOI SRAMTosaka, Y. / Suzuki, K. / Sugii, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 41
-
Novel Si surface cleaning technology with plasma hydrogenation and its application to selective CVD-W clad layer formationKosugi, T. / Ishii, H. / Arita, Y. et al. | 1995
- 43
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Pressure-Controlled Two-Step TEOS-O~3 CVD Eliminating the Base Material EffectSaito, M. / Kudoh, Y. / Homma, Y. / IEEE| Japan Society of Applied Physics et al. | 1995
- 43
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Pressure-controlled two-step TEOS-O/sub 3/ CVD eliminating the base material effectSaito, M. / Kudoh, Y. / Homma, Y. et al. | 1995
- 45
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Application of Force Fill Al-Plug Technology to 64 Mb DRAM and 0.35 m LogicMizobuchi, K. / Hamamoto, K. / Utsugi, M. / Dixit, G. A. / IEEE| Japan Society of Applied Physics et al. | 1995
- 45
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Application of force fill Al-plug technology to 64 Mbit DRAM and 0.35 micron logicMizobuchi, K. / Hamamoto, K. / Utsugi, M. / Dixit, G.A. / Poarch, S. / Havemann, R.H. et al. | 1995
- 45
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Application of force fill Al-plug technology to 64 Mb DRAM and 0.35 /spl mu/m logicMizobuchi, K. / Hamamoto, K. / Utsugi, M. / Dixit, G.A. / Poarch, S. / Havemann, R.H. / Dobson, C.D. / Jeffryes, A.I. / Holverson, P.J. / Rich, P. et al. | 1995
- 47
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Fully integrated multilevel interconnect process for low cost sub-half-micron ASIC applicationsNorishima, M. / Matsuno, T. / Anand, M.B. / Murota, M. / Inohara, M. / Inoue, K. / Ohtani, H. / Miyamoto, K. / Ogawa, R. / Seto, M. et al. | 1995
- 49
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Evolution of integrated electronics from microelectronics to nanoelectronicsSugano, T. et al. | 1995
- 49
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Evolution of Integrated Electronics from Microelectronics to Nanoelectronics (Invited)Sugano, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 53
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Manufacturing Gigachips in the Year 2005 (Invited)Chatterjee, P. K. / Doering, R. / IEEE| Japan Society of Applied Physics et al. | 1995
- 53
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Manufacturing gigachips in the year 2005Chatterjee, P.K. / Doering, R.R. et al. | 1995
- 57
-
Sub-quarter micron titanium salicide technology with in-situ silicidation using high-temperature sputteringFujii, K. / Kikuta, K. / Kikkawa, T. et al. | 1995
- 59
-
Low capacitance multilevel interconnection using low-/spl epsi/ organic spin-on glass for quarter-micron high-speed ULSIsFurusawa, T. / Homma, Y. et al. | 1995
- 59
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Low Capacitance Multilevel Interconnection Using Low- Organic Spin-on Glass for Quarter-Micron High-Speed ULSIsFurusawa, T. / Homma, Y. / IEEE| Japan Society of Applied Physics et al. | 1995
- 59
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Low Capacitance Multilevel Interconnection Using Low-curly epsilon Organic Spin-on Glass for Quarter-Micron High-Speed ULSIsFurusawa, T. / Homma, Y. / IEEE| Japan Society of Applied Physics et al. | 1995
- 61
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Highly porous interlayer dielectric for interconnect capacitance reductionJeng, S.-P. / Taylor, K. / Seha, T. / Chang, M.-C. / Fattaruso, J. / Havemann, R.H. et al. | 1995
- 63
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Reoxidized nitric oxide (ReoxNO) process and its effect on the dielectric reliability of the LOCOS edgeMaiti, B. / Tobin, P.J. / Okada, Y. / Ajuria, S. / Reid, K.G. / Hegde, R.I. / Kaushik, V. et al. | 1995
- 65
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A symmetric 0.25 /spl mu/m CMOS technology for low-power, high-performance ASIC applications using 248 nm DUV lithographyBoulin, D.M. / O'Connor, K.J. / Bevk, J. / Brasen, D. / Cheng, M. / Cirelli, R.A. / Eshraghi, S.A. / Green, M.L. / Guinn, K.V. / Hillenius, S.J. et al. | 1995
- 65
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A Symmetric 0.25 m CMOS Technology for Low-Power, High-Performance ASIC Applications Using 248 nm DUV LithographyBoulin, D. M. / Mansfield, W. M. / O'Connor, K. J. / Bevk, J. / IEEE| Japan Society of Applied Physics et al. | 1995
- 65
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A symmetric 0.25 mum CMOS technology for low-power, high-performance ASIC applications using 248 nm DUV lithographyBaulin, D.M. / Mansfield, W.M. / O'Conor, K.J. / Berk, J. / Brasen, D. / Chena, M. / Cirelli, R.A. et al. | 1995
- 67
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A self-aligned counter well-doping technology utilizing channeling ion implantation and its application to 0.25 /spl mu/m CMOS processNakamura, H. / Horiuchi, T. et al. | 1995
- 67
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A Self-Aligned Counter Well-Doping Technology Utilizing Channeling Ion Implantation and Its Application to 0.25 m CMOS ProcessNakamura, H. / Horiuchi, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 69
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Impact of the reduction of the gate to drain capacitance on low voltage operated CMOS devicesYamashita, K. / Nakaoka, H. / Kurimoto, K. / Umimoto, H. / Odanaka, S. et al. | 1995
- 71
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Advantage of small geometry silicon MOSFETs for high-frequency analog applications under low power supply voltage of 0.5 VSaito, M. / Ono, M. / Fujimoto, R. / Takahashi, C. / Tanimoto, H. / Ito, N. / Ohguro, T. / Yoshitomi, T. / Momose, H.S. / Iwai, H. et al. | 1995
- 71
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Advantage of small geometry silicon MOSFETs for high-frequency analog applications under low power supply voltage 0.5 VSaito, M. / Ono, M. / Fujimoto, R. / Takahashi, C. / Tanimoto, H. / Ito, N. / Ohguro, T. et al. | 1995
- 73
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CVD SiNx Anti-Reflective Coating for Sub-0.5 m LithographyOng, T. P. / Roman, B. / Paulson, W. / Lin, J. H. / IEEE| Japan Society of Applied Physics et al. | 1995
- 73
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CVD SiN/sub X/ anti-reflective coating for sub-0.5 /spl mu/m lithographyOng, T.P. / Roman, B. / Paulson, W. / Lin, J.H. / King, C. / Hayden, J. / Ku, Y.C. / Fu, C.C. / Luo, M. / Philbin, C. et al. | 1995
- 75
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High Performance 0.3 m CMOS Using I-Line Lithography and BARCThakar, G. V. / Madan, S. K. / Garza, C. M. / Krisa, W. L. / IEEE| Japan Society of Applied Physics et al. | 1995
- 75
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High performance 0.3 /spl mu/m CMOS using I-line lithography and BARCThakar, G.V. / Madan, S.K. / Garza, C.M. / Krisa, W.L. / Nicollian, P.E. / Wise, J.L. / Lee, C.K. / McKee, J.A. / Appel, A.T. / Esquivel, A.L. et al. | 1995
- 77
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Analysis of Critical Dimension Control for Optical-, EB-, and X-Ray Lithography below the 0.2-m RegionFukuda, H. / Okazaki, S. / IEEE| Japan Society of Applied Physics et al. | 1995
- 77
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Analysis of critical dimension control for optical-, EB-, and X-ray lithography below the 0.2-/spl mu/m regionFukuda, H. / Okazaki, S. et al. | 1995
- 79
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Phase edge lithography for sub 0.1 /spl mu/m electrical channel length in a 200 mm full CMOS processAgnello, P. / Newman, T. / Crabbe, E. / Subbanna, S. / Ganin, E. / Liebmann, L. / Comfort, J. / Sunderland, D. et al. | 1995
- 79
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Phase Edge Lithography for Sub 0.1 m Electrical Channel Length in a 200 MM Full CMOS ProcessAgnello, P. / Newman, T. / Crabbe, E. / Subbanna, S. / IEEE| Japan Society of Applied Physics et al. | 1995
- 81
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Boron as a primary source of radiation in high density DRAMsBaumann, R. / Hossain, T. / Smith, E. / Murata, S. / Kitagawa, H. et al. | 1995
- 83
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A new method to monitor gate-oxide reliability degradationCheung, K.P. et al. | 1995
- 85
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An ESD protection scheme for deep sub-micron ULSI circuitsSharma, M. / Campbell, J. / Choe, H. / Kuo, C. / Prinz, E. / Raghunathan, R. / Gardner, P. / Avery, L. et al. | 1995
- 87
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Effects of process-induced mechanical stress on ESD performanceKubota, K. / Okuyama, K. / Miura, H. / Kawashima, Y. / Ishizuka, H. / Hashimoto, C. et al. | 1995
- 89
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An etching model to predict minimum-microloading gas pressureIzawa, M. / Kumihashi, T. / Ohji, Y. et al. | 1995
- 91
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Metal etch with HI-addition to conventional chemistryFrank, W.E. et al. | 1995
- 93
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Low-energy large-mass ion bombardment process for low-temperature high-quality silicon epitaxyShindo, W. / Ohmi, T. et al. | 1995
- 93
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Low-energy large-mass ion bombardement process for low-temperature high-quality silicon epitaxyShindo, W. / Ohmi, T. et al. | 1995
- 95
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A smart batch type RTA technology for beyond 256 Mbit DRAMLee, G.G. / Fujihara, K. / Kim, S.J. / Oh, C.W. / Chung, U.I. / Ahn, S.T. / Lee, M.Y. et al. | 1995
- 97
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Gigabit DRAM vs Gigabit FlashKunio, T. / Ogura, S. / IEEE| Japan Society of Applied Physics et al. | 1995
- 97
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Mini-fabs vs Mega-fabsArai, E. / Doering, B. / IEEE| Japan Society of Applied Physics et al. | 1995
- 97
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Next Wafer Size -When Will It Happen?Abe, T. / Seidel, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 98
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Interconnect Limitation for Sub-0.25 m Devices (Technology and Circuits Joint Session)Asada, K. / Ogawa, S. / Bidermann, W. / IEEE| Japan Society of Applied Physics et al. | 1995
- 98
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Scaling Limit of Gate DielectricsTaniguchi, K. / Sun, J. Y.-C. / IEEE| Japan Society of Applied Physics et al. | 1995
- 99
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Accurate modeling of Coulombic scattering, and its impact on scaled MOSFETsMujtaba, A. / Takagi, S.-I. / Dutton, R. et al. | 1995
- 101
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Gate current by impact ionization feedback in sub-micron MOSFET technologiesBude, J.D. et al. | 1995
- 103
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Direct observation of the lateral nonuniform channel doping profile in submicron MOSFET's from an anomalous charge pumping measurement resultsChung, S.S. / Cheng, S.M. / Lee, G.H. / Guo, J.C. et al. | 1995
- 105
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Sub 0.1 m nMOSFETs Fabricated Using Experimental Design Techniques to Optimise Performance and Minimise Process SensitivityKubicek, S. / Biesemans, S. / Wang, Q. F. / Maex, K. / IEEE| Japan Society of Applied Physics et al. | 1995
- 105
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Sub 0.1 mum nMOSFETs fabricated using experimental design techniques to optimise performance and minimise process sensitivityKubicek, S. / Biesemann, S. / Wang, Q.F. / Maex, K. / Meyer, K. de et al. | 1995
- 105
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Sub 0.1 /spl mu/m nMOSFETs fabricated using experimental design techniques to optimise performance and minimise process sensitivityKubicek, S. / Biesemans, S. / Wang, Q.F. / Maex, K. / De Meyer, K. et al. | 1995
- 107
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Novel oxynitridation technology for highly reliable thin dielectricsMoon-Sig Joo, / Seok-Hee Lee, / Seok-Kiu Lee, / Byung-Jin Cho, / Jong-Choul Kim, / Soo-Han Choi, et al. | 1995
- 107
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Novel oxynidridation technology for hihly reliable thin dielectricsJoo, Moon-Sig / Lee, Seok-Hee / Lee, Seok-Kiu / Ong, Byung-Jin / Kim, Jong-Choul et al. | 1995
- 109
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Extending gate dielectric scaling limit by use of nitride or oxynitrideWang, X.W. / Shi, Y. / Ma, T.P. / Cui, G.J. / Tamagawa, T. / Golz, J.W. / Schmitt, J.J. et al. | 1995
- 111
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High quality ultra-thin (4 nm) gate oxide by UV/O/sub 3/ surface pre-treatment of native oxideOhkubo, S. / Tamura, Y. / Sugino, R. / Nakanishi, T. / Sugita, Y. / Awaji, N. / Takasaki, K. et al. | 1995
- 111
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High Quality Ultra-Thin(4 nm) Gate Oxide by UV/O~3 Surface Pre-Treatment of Native OxideOhkubo, S. / Tamura, Y. / Sugino, R. / Nakanishi, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 113
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Isolation Dependence of Gate Oxide Quality at the LOCOS Edge Using an In-Situ HCI-Based Pre-Gate PyrocleanAjuria, S. A. / Tobin, P. J. / Nguyen, B.-Y. / Limb, Y. / IEEE| Japan Society of Applied Physics et al. | 1995
- 113
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Isolation dependence of gate oxide quality at the LOCOS edge using an in-situ HCl-based pre-gate PyrocleanAjuria, S.A. / Tobin, P.J. / Nguyen, B.-Y. / Limb, Y. / Mele, T.C. et al. | 1995
- 115
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High-performance sub-0.1-/spl mu/m CMOS with low-resistance T-shaped gates fabricated by selective CVD-WHisamoto, D. / Umeda, K. / Nakamura, Y. / Kobayashi, N. / Kimura, S. / Nagai, R. et al. | 1995
- 115
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High-Performance Sub-0.1-m CMOS with Low-Resistance T-Shaped Gates Fabricated by Selective CVD-WHisamoto, D. / Umeda, K. / Nakamura, Y. / Kobayashi, N. / IEEE| Japan Society of Applied Physics et al. | 1995
- 117
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A New SSS-OSELO Technology for 0.15-m Low-Defect IsolationSudoh, Y. / Kaga, T. / Yugami, J. / Kure, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 117
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A new SSS-OSELO technology for 0.15-/spl mu/m low-defect isolationSudoh, Y. / Kaga, T. / Yugami, J. / Kure, T. et al. | 1995
- 119
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Characteristics of CMOSFETs with sputter-deposited W/TiN stack gateLee, D.H. / Joo, S.H. / Lee, G.H. / Moon, J. / Shim, T.E. / Lee, J.G. et al. | 1995
- 121
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Rapid thermal chemical vapor deposition of in-situ nitrogen-doped poly-silicon for dual gate CMOSSun, S.C. / Wang, L.S. / Yeh, F.L. / Chen, C.H. et al. | 1995
- 123
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A ferroelectric capacitor over bit-line (F-COB) cell for high density nonvolatile ferroelectric memoriesTanabe, N. / Matsuki, T. / Saitoh, S. / Takeuchi, T. / Kobayashi, S. / Nakajima, T. / Maejima, Y. / Hayashi, Y. / Amanuma, K. / Hase, T. et al. | 1995
- 125
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Ultra-thin fatigue free lead zirconate titanate thin films for gigabit DRAMsTorii, K. / Kawakami, H. / Kushida, K. / Yano, F. / Ohji, Y. et al. | 1995
- 127
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A novel low-temperature process for high dielectric constant BST thin films for ULSI DRAM applicationsKhamankar, R. / Jiang, B. / Tsu, R. / Hsu, W.-Y. / Nulman, J. / Summerfelt, S. / Anthony, M. / Lee, J. et al. | 1995
- 129
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Fast and accurate programming method for multi-level NAND EEPROMsHemink, G.J. / Tanaka, T. / Endoh, T. / Aritome, S. / Shirota, R. et al. | 1995
- 131
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A 62.8 GHz fmax LP-CVD epitaxially grown silicon base bipolar transistor with extremely high early voltage of 85.7 VYoshino, C. / Inou, K. / Matsuda, S. / Nakajima, H. / Tsuboi, Y. / Naruse, H. / Sugaya, H. / Katsumata, Y. / Iwai, H. et al. | 1995
- 133
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A low thermal budget, fully self-aligned lateral BJT on thin film SOI substrate for low power BiCMOS applicationsChen, V.M.C. / Woo, J.C.S. et al. | 1995
- 135
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A new 3-D MCM fabrication technology for high-speed chip-to-chip communication: vertically connected thin-film chip (VCTC) technologyTakahashi, S. / Onodera, T. / Hayashi, Y. / Kunio, T. et al. | 1995
- 137
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0.29-/spl mu/m/sup 2/ trench cell technologies for 1G-bit DRAMs with open/folded-bit-line layout and selective growth techniqueNoguchi, M. / Ozaki, T. / Aoki, M. / Hamamoto, T. / Habu, M. / Kato, Y. / Takigami, Y. / Shibata, T. / Nakasugi, T. / Niiyama, H. et al. | 1995
- 137
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0.29-m^2 Trench Cell Technologies for 1 G-Bit DRAMs with Open/Folded-Bit-Line Layout and Selective Growth TechniqueNoguchi, M. / Ozaki, T. / Aoki, M. / Hamamoto, T. / IEEE| Japan Society of Applied Physics et al. | 1995
- 137
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0.29 mum(exp2) trench cell technologies for 1-G-bit DRAMs with open/folded-bit-line layout and selective growth techniqueNoguchi, M. / Ozaki, T. / Aoki, M. / Hamamoto, T. / Habu, M. / Kato, Y. / Takigami, Y. et al. | 1995
- 139
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Planar gain cell for low voltage operation and gigabit memoriesKrautschneider, W.H. / Hofmann, F. / Ruderer, E. / Risch, L. et al. | 1995
- 141
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Leakage mechanism due to floating body and countermeasure on dynamic retention mode of SOI-DRAMMorishita, F. / Suma, K. / Hirose, M. / Tsuruda, T. / Yamaguchi, Y. / Eimori, T. / Oashi, T. / Arimoto, K. / Inoue, Y. / Nishimura, T. et al. | 1995
- 143
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A high performance 16M DRAM on a thin film SOIHyoung-Sub Kim, / Sang-Bo Lee, / Dong-Uk Choi, / Jae-Hoon Shim, / Kyu-Han Lee, / Kyu-Pil Lee, / Ki-Nam Kim, / Jong-Woo Park, et al. | 1995
- 145
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Direct measurement of the soft-error immunity on the DRAM well structure by using the nuclear microprobeOhno, Y. / Kishimoto, T. / Sayama, H. / Komori, S. / Kinomura, A. / Horino, Y. / Fujii, K. / Nishimura, T. / Takai, M. / Miyoshi, H. et al. | 1995
- 147
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Author index| 1995
- i
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1995 Symposium on VLSI Technology. Digest of Technical Papers| 1995