Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures (English)
- New search for: Wirthlin, M. J.
- New search for: McMurtrey, B.
- New search for: Wirthlin, M. J.
- New search for: McMurtrey, B.
- New search for: Brebner, G.
- New search for: Woods, R.
In:
Field programmable logic and applications
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555-564
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2001
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ISBN:
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ISSN:
- Conference paper / Print
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Title:Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures
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Contributors:
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Conference:Conference; 11th, Field programmable logic and applications ; 2001 ; Belfast
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Published in:LECTURE NOTES IN COMPUTER SCIENCE ; 555-564
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Publisher:
- New search for: Springer
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Place of publication:Berlin , London
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Publication date:2001-01-01
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Size:10 pages
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Remarks:Also known as FPL 2001; Includes bibliographical references and index
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ISBN:
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ISSN:
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Type of media:Conference paper
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Type of material:Print
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Language:English
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Keywords:
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Source:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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Technology Trends and Adaptive ComputingFlynn, M. J. / Liddicoat, A. A. et al. | 2001
- 6
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Prototyping Framework for Reconfigurable ProcessorsSawitzki, S. / Kohler, S. / Spallek, R. G. et al. | 2001
- 17
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An Emulator for Exploring RaPiD Configurable Computing ArchitecturesFisher, C. / Rennie, K. / Xing, G. / Berg, S. G. / Bolding, K. / Naegle, J. / Parshall, D. / Portnov, D. / Sulejmanpasic, A. / Ebeling, C. et al. | 2001
- 27
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A New Placement Method for Direct Mapping into LUT-Based FPGAsAbke, J. / Barke, E. et al. | 2001
- 37
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fGREP - Fast Generic Routing Demand Estimation for Placed FPGA CircuitsKannan, P. / Balachandran, S. / Bhatia, D. et al. | 2001
- 48
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Macrocell Architectures for Product Term Embedded Memory ArraysLin, E. / Wilton, S. J. E. et al. | 2001
- 59
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Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAsGoda, B. S. / Kraft, R. P. / Carlough, S. R. / Krawczyk, T. W. / McDonald, J. F. et al. | 2001
- 70
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Memory Synthesis for FPGA-Based Reconfigurable ComputersKasat, A. / Ouaiss, I. / Vemuri, R. et al. | 2001
- 81
-
Implementing a Hidden Markov Model Speech Recognition System in Programmable LogicMelnikoff, S. J. / Quigley, S. F. / Russell, M. J. et al. | 2001
- 91
-
Implementation of (Normalised) RLS Lattice on VirtexAlbu, F. / Kadlec, J. / Softley, C. / Matousek, R. / Hermanek, A. / Coleman, N. / Fagan, A. et al. | 2001
- 101
-
Accelerating Matrix Product on Reconfigurable Hardware for Signal ProcessingAmira, A. / Bouridane, A. / Milligan, P. et al. | 2001
- 112
-
Static Profile-Driven Compilation for FPGAsCadambi, S. / Goldstein, S. C. et al. | 2001
- 123
-
Synthesizing RTL Hardware from Java Byte CodesWirthlin, M. J. / Hutchings, B. L. / Worth, C. et al. | 2001
- 133
-
PuMA++: From Behavioral Specification to Multi-FPGA-PrototypeHarbich, K. / Barke, E. et al. | 2001
- 142
-
Secure Configuration of Field Programmable Gate ArraysKean, T. et al. | 2001
- 152
-
Single-Chip FPGA Implementation of the Advanced Encryption Standard AlgorithmMcLoone, M. / McCanny, J. V. et al. | 2001
- 162
-
JBits™ Implementations of the Advanced Encryption Standard (Rijndael)McMillan, S. / Patterson, C. et al. | 2001
- 172
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Task-Parallel Programming of Reconfigurable SystemsWeinhardt, M. / Luk, W. et al. | 2001
- 182
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Chip-Based Reconfigurable Task ManagementBrebner, G. / Diessel, O. et al. | 2001
- 192
-
Configuration Caching and SwappingSudhir, S. / Nath, S. / Goldstein, S. C. et al. | 2001
- 203
-
Multiple Stereo Matching Using an Extended ArchitectureArias-Estrada, M. / Xicotencatl, J. M. et al. | 2001
- 213
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Implementation of a NURBS to Bezier Conversor with Constant LatencyMallon, P. N. / Boo, M. / Bruguera, J. D. et al. | 2001
- 223
-
Reconfigurable Frame-Grabber for Real-Time Automated Visual Inspection (RT-AVI) SystemsCuenca, S. A. / Ibarra, F. / Alvarez, R. et al. | 2001
- 232
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Processing Models for the Next Generation Network [Abstract]Lawrence, J. et al. | 2001
- 233
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Tightly Integrated Placement and Routing for FPGAsKannan, P. / Bhatia, D. et al. | 2001
- 243
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Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-ArraysKarro, J. / Cohoon, J. et al. | 2001
- 254
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Reconfigurable Router Modules Using Network Protocol WrappersBraun, F. / Lockwood, J. / Waldvogel, M. et al. | 2001
- 264
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Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and HardwareHa, Y. / Mei, B. / Schaumont, P. / Vernalde, S. / Lauwereins, R. / De Man, H. et al. | 2001
- 275
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The MOLEN rhomu-Coded ProcessorVassiliadis, S. / Wong, S. / Cotofana, S. et al. | 2001
- 286
-
Run-Time Optimized Reconfiguration Using Instruction ForecastingIliopoulos, M. / Antonakopoulos, T. et al. | 2001
- 296
-
CRISP: A Template for Reconfigurable Instruction Set Processorsde Beeck, P. O. / Barat, F. / Jayapala, M. / Lauwereins, R. et al. | 2001
- 306
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Evaluation of an FPGA Implementation of the Discrete Element MethodSchafer, B. C. / Quigley, S. F. / Chan, A. H. C. et al. | 2001
- 315
-
Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT SolversDandalis, A. / Prasanna, V. K. / Thiruvengadam, B. et al. | 2001
- 326
-
A Reconfigurable Embedded Input Device for Kinetically Challenged PersonsDollas, A. / Papademetriou, K. / Aslanides, N. / Kean, T. et al. | 2001
- 336
-
Bubble Partitioning for LUT-Based Sequential CircuitsWolz, F. / Kolla, R. et al. | 2001
- 346
-
Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBitsSingh, S. / James-Roxby, P. et al. | 2001
- 357
-
Placing, Routing, and Editing Virtual FPGAsLagadec, L. / Lavenier, D. / Fabiani, E. / Pottier, B. et al. | 2001
- 367
-
Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures ReceiverTing, L.-K. / Woods, R. / Cowan, C. et al. | 2001
- 377
-
A Music Synthesizer on FPGASaito, T. / Maruyama, T. / Hoshino, T. / Hirano, S. et al. | 2001
- 388
-
Motivation from a Full-Rate Specific Design to a DSP Core Approach for GSM VocodersSheidaei, S. / Noori, H. / Akbari, A. / Pedram, H. et al. | 2001
- 398
-
Loop Tiling for Reconfigurable AcceleratorsDerrien, S. / Rajopadhye, S. et al. | 2001
- 409
-
The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded SystemsSassatelli, G. / Torres, L. / Galy, J. / Cambon, G. / Diou, C. et al. | 2001
- 420
-
A n-Bit Reconfigurable Scalar QuantiserCadenas, O. / Megson, G. et al. | 2001
- 430
-
Real Time Morphological Image Contrast Enhancement in Virtex FPGAKasperek, J. et al. | 2001
- 441
-
Demonstrating Real-Time JPEG Image Compression-Decompression Using Standard Component IP Cores on a Programmable Logic Based Platform for DSP and Image ProcessingSimpson, A. / Hunter, J. / Wylie, M. / Hu, Y. / Mann, D. et al. | 2001
- 451
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Design and Implementation of an Accelerated Gabor Filter Bank Using Parallel HardwareVoss, N. / Mertsching, B. et al. | 2001
- 461
-
The Evolution of Programmable Logic: Past, Present, and Future Predictions [Abstract]Carter, B. et al. | 2001
- 462
-
Dynamically Reconfigurable CoresMacBeth, J. / Lysaght, P. et al. | 2001
- 473
-
Reconfigurable Breakpoints for Co-debugPrice, T. / Patterson, C. et al. | 2001
- 483
-
Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional VerificationWheeler, T. / Graham, P. / Nelson, B. / Hutchings, B. et al. | 2001
- 493
-
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI CircuitsCivera, P. / Macchiarulo, L. / Rebaudengo, M. / Reorda, M. S. / Violante, M. et al. | 2001
- 503
-
A Generic Library for Adaptive Computing EnvironmentsNeumann, T. / Koch, A. et al. | 2001
- 513
-
Generative Development System for FPGA Processors with Active ComponentsRuhl, S. / Dillinger, P. / Hezel, S. / Manner, R. et al. | 2001
- 523
-
Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing MachinesCardoso, J. M. P. / Neto, H. C. et al. | 2001
- 534
-
System Level Tools for DSP in FPGAsHwang, J. / Milne, B. / Shirazi, N. / Stroomer, J. D. et al. | 2001
- 544
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Parameterized Function Evaluation for FPGAsMencer, O. / Boullis, N. / Luk, W. / Styles, H. et al. | 2001
- 555
-
Efficient Constant Coefficient Multiplication Using Advanced FPGA ArchitecturesWirthlin, M. J. / McMurtrey, B. et al. | 2001
- 565
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A Digit-Serial Structure for Reconfigurable MultipliersVisavakul, C. / Cheung, P. Y. K. / Luk, W. et al. | 2001
- 574
-
FPGA Resource Reduction Through Truncated MultiplicationWires, K. E. / Schulte, M. J. / McCarley, D. et al. | 2001
- 584
-
Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array ArchitecturesBecker, J. / Liebau, N. / Pionteck, T. / Glesner, M. et al. | 2001
- 590
-
An FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free GrammarsCiressan, C. / Sanchez, E. / Rajman, M. / Chappelier, J.-C. et al. | 2001
- 595
-
Hardware-Software Partitioning: A Reconfigurable and Evolutionary Computing ApproachHarkin, J. / McGinnity, T. M. / Maguire, L. P. et al. | 2001
- 601
-
An Approach to Real-Time Visualization of PIV Method with FPGAMaruyama, T. / Yamaguchi, Y. / Kawase, A. et al. | 2001
- 607
-
FPGA-Based Discrete Wavelet Transforms SystemNibouche, M. / Bouridane, A. / Murtagh, F. / Nibouche, O. et al. | 2001
- 613
-
X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data CompressorNunez, J. L. / Feregrino, C. / Jones, S. / Bateman, S. et al. | 2001
- 618
-
Arithmetic Operation Oriented Reconfigurable Chip: RHWYamauchi, T. / Nakaya, S. / Inuo, T. / Kajihara, N. et al. | 2001
- 623
-
Initial Analysis of the Proteus ArchitectureDales, M. et al. | 2001
- 628
-
Building Asynchronous Circuits with JBitsKeller, E. et al. | 2001
- 633
-
Case Study of Integration of Reconfigurable Logic as a Coprocessor into a SCI-Cluster under RT-LinuxLehmann, T. / Schreckenberg, A. et al. | 2001
- 638
-
A Reconfigurable Approach to Packet FilteringSinnappan, R. / Hazelhurst, S. et al. | 2001
- 643
-
FPGA-Based Modelling Unit for High Speed Lossless Arithmetic CodingStefo, R. / Nunez, J. L. / Feregrino, C. / Mahapatra, S. / Jones, S. et al. | 2001
- 648
-
A Data Re-use Based Compiler Optimization for FPGAsSubramanian, R. / Pande, S. et al. | 2001
- 653
-
Dijkstra's Shortest Path Routing Algorithm in Reconfigurable HardwareTommiska, M. / Skytta, J. et al. | 2001
- 658
-
A System on Chip for Power Line Communications According to European Home Systems SpecificationsUrriza, I. / Garcia-Nicolas, J. I. / Sanz, A. / Valdovinos, A. et al. | 2001