Tester Architecture for the Source-Synchronous Bus (English)
- New search for: Sivaram, A.
- New search for: Shimanouchi, M.
- New search for: Maassen, H.
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- New search for: Sivaram, A.
- New search for: Shimanouchi, M.
- New search for: Maassen, H.
- New search for: Jackson, R.
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In:
Test; International test conference 2004
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738-747
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2004
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ISBN:
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ISSN:
- Conference paper / Print
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Title:Tester Architecture for the Source-Synchronous Bus
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Contributors:Sivaram, A. ( author ) / Shimanouchi, M. ( author ) / Maassen, H. ( author ) / Jackson, R. ( author ) / IEEE
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Conference:International conference, Test; International test conference 2004 ; 2004 ; Charlotte, NC
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Published in:Test; International test conference 2004 ; 738-747INTERNATIONAL TEST CONFERENCE ; 738-747
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Publisher:
- New search for: IEEE
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Publication date:2004-01-01
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Size:10 pages
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Remarks:Also known as ITC 2004. IEEE cat no 04CH37586.
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ISBN:
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ISSN:
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Type of media:Conference paper
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Type of material:Print
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Language:English
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Keywords:
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Source:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 0_1
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Proceedings. International Test Conference 2004 (IEEE Cat. No.04CH37586)| 2004
- 1
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Welcome Message| 2004
- 2
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International Test Conference 2004 - Steering Committee and Subcommittees| 2004
- 4
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In Memoriam Nathaniel "Ned" Kornfield| 2004
- 5
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ITC 2003 Paper Awards| 2004
- 6
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ITC 2004 - Technical Program Committee| 2004
- 9
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International Test Conference 2004 - Technical Program Committee| 2004
- 10
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ITC Technical Paper Evaluation and Selection Process| 2004
- 11
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International Test Conference 2005 - Call for Papers| 2004
- 12
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Test in the Era of "What You see Is NOT What You Get"Koenemann, B. / IEEE et al. | 2004
- 12
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Test in the era of "What you see is not what you get" - Keynote addressKoenemann, B. et al. | 2004
- 13
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New Test Paradigms for Yield and ManufacturabilityMadge, R. / IEEE et al. | 2004
- 13
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New test paradigms for yield and manufacturability - Invited addressMadge, R. et al. | 2004
- 14
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TTTC: Test Technology Technical Council| 2004
- 17
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International Test Conference - 2004 Technical Paper Reviewers| 2004
- 23
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AC IO loopback design for high speed /spl mu/processor IO testProvost, B. / Huang, T. / Lim, C.H. / Tian, K. / Bashir, M. / Atha, M. / Muhtaroglu, A. / Zhao, C. / Muljono, H. et al. | 2004
- 23
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AC IO Loopback Design for High-Speed muProcessor IO TestProvost, B. / Huang, T. / Lim, C.-H. / Tian, K. / Bashir, M. / Atha, M. / Muhtaroglu, A. / Zhao, C. / Muljono, H. / IEEE et al. | 2004
- 31
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On correlating structural tests with functional tests for speed binning of high performance designZeng, J. / Abadir, M. / Vandling, G. / Wang, L. / Kolhatkar, A. / Abraham, J. et al. | 2004
- 38
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An optimized DFT and test pattern generation strategy for an Intel high performance microprocessorWu, D.M. / Lin, M. / Reddy, M. / Jaber, T. / Sabbavarapu, A. / Thatcher, L. et al. | 2004
- 48
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Efficient pattern mapping for deterministic logic BISTGherman, V. / Wunderlich, H.-J. / Vranken, H. / Hapke, F. / Wittke, M. / Garbers, M. et al. | 2004
- 57
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Logic BIST with scan chain segmentationLiyang Lai, / Patel, J.H. / Rinderknecht, T. / Wu-Tung Cheng, et al. | 2004
- 67
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Spectral analysis for statistical response compaction during built-in self-testingOmar Khan, / Bushnell, M.L. et al. | 2004
- 77
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A real-time jitter measurement board for high-performance computer and communication systemsYamaguchi, T.J. / Ishida, M. / Soma, M. / Ichiyama, K. / Christian, K. / Ohsawa, K. / Sugai, M. et al. | 2004
- 85
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Experimental results for high-speed jitter measurement techniqueTaylor, K. / Nelson, B. / Chong, A. / Nguyen, H. / Lin, H. / Soma, M. / Haggag, H. / Huard, J. / Braatz, J. et al. | 2004
- 95
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An automated, complete, structural test solution for SERDESSunter, S. / Roy, A. / Cote, J.-F. et al. | 2004
- 105
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A design for test technique for parametric analysis of SRAM: on-die low yield analysisMauck, B.M. / Ravichandran, V. / Mughal, U.A. et al. | 2004
- 114
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Detecting Faults in Peripheral Circuits and an Evaluation of SRAM Testsvan de Goor, A. / Hamdioui, S. / Wadsworth, R. / IEEE et al. | 2004
- 114
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Detecting faults in the peripheral circuits and an evaluation of SRAM testsvan de Goor, Ad.J. / Hamdioui, S. / Wadsworth, R. et al. | 2004
- 124
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MRAM defect analysis and fault modelingChin-Lung Su, / Rei-Fu Huang, / Cheng-Wen Wu, / Chien-Chung Hung, / Ming-Jer Kao, / Yeong-Jar Chang, / Wen-Ching Wu, et al. | 2004
- 134
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CMOS IC Diagnostics Using the Luminescence of Off-State Leakage CurrentPolonsky, S. / Jenkins, K. / Weger, A. / Cho, S. / IEEE et al. | 2004
- 134
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CMOS IC diagnostics using the luminescence of off-state leakage currentsPolonsky, S. / Jenkins, K.A. / Weger, A. / Shinho Cho, et al. | 2004
- 140
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A novel scan chain diagnostics technique based on light emission from leakage currentSong, P. / Stellari, F. / Xia, T. / Weger, A.J. et al. | 2004
- 148
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Impact of negative bias temperature instability on product parametric driftReddy, V. / Carulli, J. / Krishnan, A. / Bosch, W. / Burgess, B. et al. | 2004
- 156
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At-speed interconnect test and diagnosis of external memories on a systemKim, H.C. / Jun, H.-S. / Xinli Gu, / Chung, S.S. et al. | 2004
- 163
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Interconnect test pattern generation algorithm for meeting device and global SSO limits with safe initial vectorsBaker, K. / Nourani, M. et al. | 2004
- 173
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Removing JTAG bottlenecks in system interconnect testHong-Shin Jun, / Chung, S.S. / Baeg, S.H. et al. | 2004
- 181
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ATE data collection - a comprehensive requirements proposal to maximize ROI of testRehani, M. / Abercrombie, D. / Madge, R. / Teisher, J. / Saw, J. et al. | 2004
- 190
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Non-deterministic DUT behavior during functional testing of high speed serial busses: challenges and solutionsHops, J. / Swing, B. / Phelps, B. / Sudweeks, B. / Pane, J. / Kinslow, J. et al. | 2004
- 197
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Divide and conquer based Fast Shmoo algorithmsPatten, P. et al. | 2004
- 203
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In search of the optimum test set - adaptive test methods for maximum defect coverage and lowest test costMadge, R. / Benware, B. / Turakhia, R. / Daasch, R. / Schuermyer, C. / Ruffler, J. et al. | 2004
- 213
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On hazard-free patterns for fine-delay fault testingKruseman, B. / Majhi, A.K. / Gronthoud, G. / Eichenberger, S. et al. | 2004
- 223
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K longest paths per gate (KLPG) test generation for scan-based sequential circuitsQiu, W. / Jing Wang, / Walker, D.M.H. / Reddy, D. / Xiang Lu, / Zhuo Li, / Weiping Shi, / Balachandran, H. et al. | 2004
- 232
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A critical path selection method for delay testingPadmanaban, S. / Tragoudas, S. et al. | 2004
- 242
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Evaluating the effectiveness of detecting delay defects in the slack interval: a simulation studyHaihua Yan, / Singh, A.D. et al. | 2004
- 252
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Quasi-oscillation based test for improved prediction of analog performance parametersRaghunathan, A. / Chun, J.H. / Abraham, J.A. / Chatterjee, A. et al. | 2004
- 262
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On-chip impulse response generation for analog and mixed-signal testingSingh, A. / Patel, C. / Plusquellic, J. et al. | 2004
- 271
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Automatic linearity (IP3) test with built-in pattern generator and analyzerDai, F. / Stroud, C. / Yang, D. / Shuying Qi, et al. | 2004
- 281
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Extending the digital core-based test methodology to support mixed-signalSeuren, G. / Waayers, T. et al. | 2004
- 290
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Systematic defects in deep sub-micron technologiesKruseman, B. / Majhi, A. / Hora, C. / Eichenberger, S. / Meirlevede, J. et al. | 2004
- 300
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Minimum testing requirements to screen temperature dependent defectsSchuermyer, C. / Ruffler, J. / Daasch, R. / Madge, R. et al. | 2004
- 309
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Random and systematic defect analysis using IDDQ signature analysis for understanding fails and guiding test decisionsNigh, P. / Gattiker, A. et al. | 2004
- 319
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Defect detection under realistic leakage models using multiple I/sub DDQ/ measurementsPatel, C. / Singh, A. / Plusquellic, J. et al. | 2004
- 319
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Defect Detection Under Realistic Leakage Models Using Multiple I~D~D~Q MeasurementsPatel, C. / Singh, A. / Plusquellic, J. / IEEE et al. | 2004
- 329
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Testing micropipelined asynchronous circuitsKing, M.L. / Saluja, K.K. et al. | 2004
- 339
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Scan based side channel attack on dedicated hardware implementations of Data Encryption StandardBo Yang, / Kaijie Wu, / Ramesh Karri, et al. | 2004
- 345
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A holistic parallel and hierarchical approach towards design-for-testRavikumar, C.P. / Hetherington, G. et al. | 2004
- 355
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Minimizing power consumption in scan testing: pattern generation and DFT techniquesButler, K.M. / Saxena, J. / Jain, A. / Fryars, T. / Lewis, J. / Hetherington, G. et al. | 2004
- 365
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A new probing technique for high-speed/high-density printed circuit boardsParker, K.P. et al. | 2004
- 375
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On-chip mixed-signal test structures re-used for board testSchuttert, R. / van Geest, D.C.L. et al. | 2004
- 384
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Test strategy cost model innovationsMichel, C. / Reinosa, R.D. et al. | 2004
- 393
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Production test effectiveness of combined automated inspection and ICT test strategiesVerma, A. / Robinson, C. / Butkovich, S. et al. | 2004
- 403
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Open architecture test system: system architecture and designRajsuman, R. / Noriyuki, M. et al. | 2004
- 413
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Test programming environment in a modular, open architecture test systemPramanick, A. / Krishnaswamy, R. / Elston, M. / Adachi, T. / Harsanjeet Singh, / Parnas, B. / Chen, L. et al. | 2004
- 423
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Extending STIL 1450 standard for test program flowDowding, D. / Wahl, E. / Organ, D. et al. | 2004
- 432
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X-tolerant signature analysisMitra, S. / Lumetta, S.S. / Mitzenmacher, M. et al. | 2004
- 442
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X-masking during logic BIST and its impact on defect coverageYuyi Tang, / Wunderlich, H.-J. / Vranken, H. / Hapke, F. / Wittke, M. / Engelke, P. / Polian, I. / Becker, B. et al. | 2004
- 452
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Channel masking synthesis for efficient on-chip test compressionChickermane, V. / Foutz, B. / Keller, B. et al. | 2004
- 462
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CAEN-BIST: testing the nanofabricBrown, J.G. / Blanton, R.D. et al. | 2004
- 472
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Fault tolerant arithmetic with applications in nanotechnology based systemsWenjing Rao, / Orailoglu, A. / Karri, R. et al. | 2004
- 479
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Routability and fault tolerance of FPGA interconnect architecturesJing Huang, / Tahoori, M.B. / Lombardi, F. et al. | 2004
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Z-DFD: design-for-diagnosability based on the concept of Z-detectionPomeranz, I. / Venkataraman, S. / Reddy, S.M. et al. | 2004
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Fault diagnosis in designs with convolutional compactorsMrugalski, G. / Pogiel, A. / Rajski, J. / Tyszer, J. / Chen Wang, et al. | 2004
- 508
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Benchmarking diagnosis algorithms with a diverse set of IC deformationsVogels, T. / Zanon, T. / Desineni, R. / Blanton, R.D. / Maly, W. / Brown, J.G. / Nelson, J.E. / Fei, Y. / Huang, X. / Gopalakrishnan, P. et al. | 2004
- 518
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An economic analysis and ROI model for nanometer testKeller, B. / Tegethoff, M. / Bartenstein, T. / Chickermane, V. et al. | 2004
- 525
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Realizing high test quality goals with smart test resource usageXinli Gu, / Wang, C. / Lee, A. / Eklow, B. / Kun-Han Tsai, / Tofte, J.A. / Kassab, M. / Rajski, J. et al. | 2004
- 534
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Low overhead delay testing of ASICsGillis, P. / McCauley, K. / Woytowich, F. / Ferko, A. et al. | 2004
- 534
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Low-Overhead Delay Testing of IBM ASICsGillis, P. / McCauley, K. / Woytowich, F. / Ferko, A. / IEEE et al. | 2004
- 543
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IEEE standard 1149.6 implementation for a XAUI-to-serial 10-Gbps transceiverShaikh, S.A. et al. | 2004
- 543
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IEEE Std 1149.6 Implementation for a XAUI-to-Serial 10-Gbps TransceiverShaikh, S. / IEEE et al. | 2004
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A frequency mixing and sub-sampling based RF-measurement apparatus for IEEE 1149.4Hakkinen, J. / Syri, P. / Voutilainen, J.-V. / Moilanen, M. et al. | 2004
- 560
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Integrating boundary scan into multi-GHz I/O circuitryRearick, J. / Patterson, S. / Dorner, K. et al. | 2004
- 567
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Timing accuracy enhancement by a new calibration scheme for multi-Gbps ATEShimanouchi, M. et al. | 2004
- 577
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Automatic delay calibration method for multi-channel CMOS formatterSyed, A.R. et al. | 2004
- 587
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Active tester interface unit design for data collectionSivaram, A.T. / Pierra, P. / Sheibani, S. / Nancy Wang-Lee, / Solorzano, J.E. / Tran, L. et al. | 2004
- 597
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SPIN-SIM: logic and fault simulation for speed-independent circuitsShi, F. / Makris, Y. et al. | 2004
- 607
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Decision selection and learning for an 'all-solutions ATPG engine'Chandrasekar, K. / Hsiao, M.S. et al. | 2004
- 617
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On random pattern generation with the selfish gene algorithm for testing digital sequential circuitsJunwu Zhang, / Bushnell, M.L. / Agrawal, V.D. et al. | 2004
- 627
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Localizing open interconnect defects using targeted routing in FPGA'sMark, D. / Fan, J. et al. | 2004
- 635
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Interconnect delay testings of designs on programmable logic devicesTahoori, M.B. / Mitra, S. et al. | 2004
- 635
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Interconnect Delay Testing of Designs on Programmable Logic DevicesTahoori, M. B. / Mitra, S. / IEEE et al. | 2004
- 645
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Application-dependent diagnosis of FPGAsBaradaran Tahoori, M. et al. | 2004
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Feed forward test methodology utilizing device identificationCabbibo, A. / Conder, J. / Jacobs, M. et al. | 2004
- 661
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Data mining integrated circuit fails with fail commonalitiesHuisman, L.M. / Kassab, M. / Pastel, L. et al. | 2004
- 669
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Evaluation of the quality of N-detect scan ATPG patterns on a processorAmyeen, M.E. / Venkataraman, S. / Ojha, A. / Sangbong Lee, et al. | 2004
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Trends in manufacturing test methods and their implicationsKundu, S. / Mak, T.M. / Galivanche, R. et al. | 2004
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Trends in testing integrated circuitsVermeulen, B. / Hora, C. / Kruseman, B. / Marinissen, E.J. / van Rijsinge, R. et al. | 2004
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Future trends in test: the adoption and use of low cost structural testersCrouch, A.L. et al. | 2004
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Simulation based system level fault insertion using co-verification toolsEklow, B. / Hosseini, A. / Chi Khuong, / Pullela, S. / Vo, T. / Chau, H. et al. | 2004
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Testing and remote field update of distributed base stations in a wireless networkChen-Huan Chiang, / Wheatley, P.J. / Ho, K.Y. / Cheung, K.L. et al. | 2004
- 719
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IPv6 conformance testing: theory and practiceYujun Zhang, / Zhongcheng Li, et al. | 2004
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A high-throughput 5 Gbps timing and jitter test module featuring localized processingHafed, M.M. / Chan, A.H. / Duerden, G. / Pishdad, B. / Tam, C. / Laberge, S. / Roberts, G.W. et al. | 2004
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Tester architecture for the source synchronous busSivaram, A.T. / Shimanouchi, M. / Maassen, H. / Jackson, R. et al. | 2004
- 748
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Modular extension of ATE to 5 GbpsKeezer, D.C. / Minier, D. / Paradis, M. / Binette, L. et al. | 2004
- 758
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Test strategies for a 40 Gbps framer SoCHeineken, H.T. / Khare, J.B. et al. | 2004
- 764
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A model-based test approach for testing high speed PLLs and phase regulation circuitry in SOC devicesLaquai, B. et al. | 2004
- 773
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DFT for Test Optimisations in a Complex Mixed-Signal SOC-Case Study on Tl's TNETD7300 ADSL Modem DeviceParekhji, R. / Nikila, K. / IEEE et al. | 2004
- 773
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DFT for test optimisations in a complex mixed-signal SOC - case study on TI's TNETD7300 ADSL modem deviceNikila, K. / Parekhji, R.A. et al. | 2004
- 783
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Delayed-RF based test development for FM transceivers using signature analysisAcar, E. / Ozev, S. et al. | 2004
- 793
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RF testing on a mixed signal testerBrown, D. / Ferrario, J. / Wolf, R. / Li, J. / Bhagat, J. et al. | 2004
- 801
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Use of Embedded Sensors for Built-in Test of RF CircuitsBhattacharya, S. / Chatterjee, A. / IEEE et al. | 2004
- 801
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Use of embedded sensors for built-in-test RF circuitsBhattacharya, S. / Chatterjee, A. et al. | 2004
- 810
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Formal verification of a system-on-chip using computation slicingSen, A. / Bhadra, J. / Garg, V.K. / Abraham, J.A. et al. | 2004
- 820
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State variable extraction to reduce problem complexity for ATPG and design validationWu, Q. / Hsiao, M.S. et al. | 2004
- 830
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Verification on port connectionsGeeng-Wei Lee, / Chun-Yao Wang, / Juinn-Dar Huang, / Jing-Yang Jou, et al. | 2004
- 837
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Built-in self-test for system-on-chip: a case studyStroud, C. / Sunwoo, J. / Garimella, S. / Harris, J. et al. | 2004
- 847
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Hierarchical DFT methodology - a case studyRemmers, J. / Villalba, M. / Fisette, R. et al. | 2004
- 857
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A code-less BIST processor for embedded test and in-system configuration of boards and systemsClark, C.J. / Ricchetti, M. et al. | 2004
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Towards microagent based DBIST/DBISRMiclea, L. / Enyedi, S. / Toderean, G. / Benso, A. / Prinetto, P. et al. | 2004
- 875
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Embedded test for a new memory-card architectureResnick, D. et al. | 2004
- 883
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Concurrent testing of droplet-based microfluidic systems for multiplexed biomedical assaysSu, F. / Ozev, S. / Chakrabarty, K. et al. | 2004
- 893
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Testing the configurable analog blocks of field programmable analog arraysBalen, T. / Andrade, A. / Azais, F. / Lubaszewski, M. / Renovell, M. et al. | 2004
- 903
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I/O self-leakage testMuhtaroglu, A. / Provost, B. / Rahal-Arabi, T. / Taylor, G. et al. | 2004
- 907
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Defect coverage analysis of partitioned testingChakravarty, S. / Savage, E.W. / Tran, E.N. et al. | 2004
- 916
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VirtualScan: a new compressed scan technology for test cost reductionWang, L.-T. / Xiaoqing Wen, / Furukawa, H. / Fei-Sheng Hsu, / Shyh-Horng Lin, / Sen-Wei Tsai, / Abdel-Hafez, K.S. / Shianling Wu, et al. | 2004
- 926
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Data compression for multiple scan chains using dictionaries with correctionsWurtenberger, A. / Tautermann, C.S. / Hellebrand, S. et al. | 2004
- 936
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Improving encoding efficiency for linear decompressors using scan inversionBalakrishnan, K.J. / Touba, N.A. et al. | 2004
- 945
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Test cost reduction through a reconfigurable scan architectureArslan, B. / Orailoglu, A. et al. | 2004
- 953
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Reducing measurement uncertainty in a DSP-based mixed-signal test environment without increasing test timeTaillefer, C. / Roberts, G.W. et al. | 2004
- 963
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Controlled sine wave fitting for ADC testMattes, H. / Sattler, S. / Dworski, C. et al. | 2004
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Precise pulse width measurement in write pre-compensation testOkawara, H. et al. | 2004
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Power supply ramping for quasi-static testing of PLLsPineda de Gyvez, J. / Gronthoud, G. / Cenci, C. / Posch, M. / Burger, T. / Koller, M. et al. | 2004
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Programmable at-speed array and functional BIST for embedded DRAM LSIKume, M. / Uehara, K. / Itakura, M. / Sawamoto, H. / Kobayashi, T. / Hasegawa, M. / Hayashi, H. et al. | 2004
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A modular wrapper enabling high speed BIST and repair for small wide memoriesAitken, R.C. et al. | 2004
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An SRAM weak cell fault model and a DFT technique with a programmable detection thresholdPavlov, A. / Sachdev, M. / Pineda de Gyvez, J. et al. | 2004
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Post-packaging auto repair techniques for fast row cycle embedded DRAMWada, O. / Namekawa, T. / Ito, H. / Nakayama, A. / Fujii, S. et al. | 2004
- 1024
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Timing-independent testing of crosstalk in the presence of delay producing defects using surrogate fault modelsIrajpour, S. / Gupta, S.K. / Breuer, M.A. et al. | 2004
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Identifying untestable transition faults in latch based designs with multiple clocksSyal, M. / Chakravarty, S. / Hsiao, M.S. et al. | 2004
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Analysis of delay caused by bridging faults in RLC interconnectsZhou, Q. / Mohanram, K. et al. | 2004
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ALAPTF: a new transition fault model and the ATPG algorithmGupta, P. / Hsiao, M.S. et al. | 2004
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A hierarchical DFT architecture for chip, board and system test/debugNjinda, C.A. et al. | 2004
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"Real life" system testing of networking equipmentKalidindi, S. / Huynh, N. / Eklow, B. / Goldstein, J. et al. | 2004
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Practical instrumentation integration considerationsAnderson, T.J. et al. | 2004
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Formal description of test specification and ATE architecture for mixed-signal testDeng, B. / Glauert, W. et al. | 2004
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Simulation requirements for vectors in ATE formatsRaghuraman, R. et al. | 2004
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A DFT technique for delay fault testability and diagnostics in 32-bit high performance CMOS ALUsChatterjee, B. / Sachdev, M. / Keshavarzi, A. et al. | 2004
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Tri-scan: a novel DFT technique for CMOS path delay fault testingDatta, R. / Ravi Gupta, / Sebastine, A. / Abraham, J.A. / d'Abreu, M. et al. | 2004
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Speed clustering of integrated circuitsBrand, K.A. / Mitra, S. / Volkerink, E. / McCluskey, E.J. et al. | 2004
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BER estimation for serial links based on jitter spectrum and clock recovery characteristicsDongwoo Hong, / Chee-Kian Ong, / Kwang-Ting Cheng, et al. | 2004
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A high-resolution flash time-to-digital converter and calibration schemeLevine, P.M. / Roberts, G.W. et al. | 2004
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Transfer functions for the reference clock jitter in a serial link: theory and applicationsMike Li, / Martwick, A. / Talbot, G. / Wilstrup, J. et al. | 2004
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The leading edge of production wafer probe test technologyMann, W.R. / Taber, F.L. / Seitzer, P.W. / Broz, J.J. et al. | 2004
- 1196
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Time/area tradeoffs in testing hierarchical SOCs with hard mega-coresQiang Xu, / Nicolici, N. et al. | 2004
- 1203
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IEEE P1500-compliant test wrapper design for hierarchical coresSehgal, A. / Goel, S.K. / Marinissen, E.J. / Chakrabarty, K. et al. | 2004
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An SOC test integration platform and its industrial realizationKuo-Liang Cheng, / Jing-Reng Huang, / Chih-Wea Wang, / Chih-Yen Lo, / Li-Ming Denq, / Chih-Tsun Huang, / Cheng-Wen Wu, / Shin-Wei Hung, / Jye-Yuan Lee, et al. | 2004
- 1223
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Risks associated with faults within test pattern compactors and their implications on testingMetra, C. / Mak, T.M. / Omana, M. et al. | 2004
- 1232
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Architectures of increased availability wireless sensor network nodesMan Wah Chiang, / Zilic, Z. / Radecka, K. / Chenard, J.-S. et al. | 2004
- 1242
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Low cost concurrent error detection for the advanced encryption standardWu, K. / Ramesh Karri, / Kuznetsov, G. / Goessel, M. et al. | 2004
- 1249
-
Digital synchronization for reconfigurable ATEWest, B.G. / Jones, M.F. et al. | 2004
- 1255
-
34.1 Gbps low jitter, low BER high-speed parallel CMOS interface for interconnections in high-speed memory test systemWatanabe, D. / Suda, M. / Okayasu, T. et al. | 2004
- 1263
-
System monitor for diagnostic, calibration and system configurationGavardoni, M. / Jones, M. / Poffenberger, R. / Conde, M. et al. | 2004
- 1269
-
Impact of body bias on delay fault testing of nanoscale CMOS circuitsPaul, B.C. / Neau, C. / Roy, K. et al. | 2004
- 1276
-
Within die thermal gradient impact on clock-skew: a new type of delay-fault mechanismBota, S.A. / Rosales, M. / Rosello, J.L. / Keshavarzi, A. / Segura, J. et al. | 2004
- 1285
-
Affordable and effective screening of delay defects in ASICs using the inline resistance fault modelBenware, B. / Lu, C. / Van Slyke, J. / Prabhu Krishnamurthy, / Madge, R. / Keim, M. / Kassab, M. / Rajski, J. et al. | 2004
- 1295
-
Jitter models and measurement methods for high-speed serial interconnectsKuo, A. / Farahmand, T. / Ou, N. / Tabatabaei, S. / Ivanov, A. et al. | 2004
- 1303
-
Implementation of an economic jitter compliance test for a multi-gigabit device on ATEHansel, G. / Stieglbauer, K. / Schulze, G. / Moreira, J. et al. | 2004
- 1313
-
Jitter generation and measurement for test of multi-Gbps serial IOTabatabaei, S. / Lee, M. / Ben-Zeev, F. et al. | 2004
- 1322
-
Reducing power consumption in memory ECC checkersGhosh, S. / Basu, S. / Touba, N.A. et al. | 2004
- 1332
-
Evaluating the effects of transient faults on vehicle dynamic performance in automotive systemsCorno, F. / Esposito, F. / Sonza Reorda, M. / Tosato, S. et al. | 2004
- 1340
-
On-line testing field programmable analog array circuitsHaibo Wang, / Kulkarni, S. / Tragoudas, S. et al. | 2004
- 1349
-
Integrating core selection in the SOC test solution design-flowLarsson, E. et al. | 2004
- 1359
-
Autonomous yet deterministic test of SOC coresSinanoglu, O. / Orailoglu, A. et al. | 2004
- 1369
-
Test scheduling for network-on-chip with BIST and precedence constraintsChunsheng Liu, / Cota, E. / Sharif, H. / Pradhan, D.K. et al. | 2004
- 1379
-
Testing high resolution ADCs with low resolution/accuracy deterministic dynamic element matched DACsHanjun Jiang, / Olleta, B. / Degang Chen, / Geiger, R.L. et al. | 2004
- 1389
-
Performance characterization of mixed-signal circuits using a ternary signal representationHak-Soo Yu, / Shin, H. / Chun, J.H. / Abraham, J.A. et al. | 2004
- 1398
-
A computationally efficient method for accurate spectral testing without requiring coherent samplingZhongjun Yu, / Degang Chen, / Geiger, R. et al. | 2004
- 1408
-
Open architecture ATE: dream or reality?Robinson, G.D. et al. | 2004
- 1409
-
The critical need for open ATE architecturePerez, S.M. et al. | 2004
- 1410
-
Open architecture ATE: prospects and problemsWest, B.G. et al. | 2004
- 1411
-
Security vs. test quality: can we really only have one at a time?Marinissen, E.J. et al. | 2004
- 1411
-
Security vs. Test Quality: Can We Only Have One at a Time?Marinissen, E. / IEEE et al. | 2004
- 1412
-
Electronic circuit comprising a secret sub-moduleFleury, H. et al. | 2004
- 1413
-
Security vs. test quality: fully embedded test approaches are the key to having bothPateras, S. et al. | 2004
- 1414
-
Security vs. test quality: are they mutually exclusive?Kapur, R. et al. | 2004
- 1415
-
Testing a secure device: high coverage with very low observabilitySourgen, L. et al. | 2004
- 1416
-
Glamorous analog testability - we already test them and ship them... so what is the problem?Hafed, M.M. et al. | 2004
- 1417
-
100 DPPM in nanometer technology... is it achievable?Aldrich, G. et al. | 2004
- 1417
-
100 DPM in Nanometer Technology-Is it achievable?Aldrich, G. / IEEE et al. | 2004
- 1418
-
Achieving sub 100 DPPM defect levels on VDSM and nanometer ASICsBenware, B.R. et al. | 2004
- 1419
-
Sure you can get to 100 DPPM in deep submicron, but it'll cost yaButler, K.M. et al. | 2004
- 1420
-
Achieving quality levels of 100 DPM: it's possible... but roll up your sleeves and be prepared to do some workNigh, P. et al. | 2004
- 1421
-
Test strategies for nanometer technologiesSengupta, S. et al. | 2004
- 1422
-
Testing in a high volume DSM environmentStorey, T. et al. | 2004
- 1423
-
What do you mean my board test stinks?Eklow, B. et al. | 2004
- 1424
-
Functional test coverage effectiveness on the declineNejedlo, J.J. et al. | 2004
- 1425
-
To test or to inspect, what is the coverage?Jukna, R. et al. | 2004
- 1426
-
Board test coverage needs to be standardizedParker, K.P. et al. | 2004
- 1427
-
What do you mean by board test stinks?Smith, J.M. et al. | 2004
- 1428
-
Dude! where's my data? - cracking open the hermetically sealed testerDaasch, R. / Rehani, M. et al. | 2004
- 1429
-
Redefining ATE: "Data Collection Engines that Drive Yield Learning & Process Optimization"Nigh, P. / IEEE et al. | 2004
- 1429
-
Redefining ATE: "data collection engines that drive yield learning and process optimization"Nigh, P. et al. | 2004
- 1430
-
ATE Value Add through Open Data CollectionMadge, R. / IEEE et al. | 2004
- 1430
-
ATE value add through open data collection panel position paper for "Dude! where's my data? - cracking open the hermetically sealed tester"Madge, R. et al. | 2004
- 1431
-
Cost of Test - Taking ControlMukherjee, N. / IEEE et al. | 2004
- 1431
-
Panel 7 : cost of test - taking control [failure mechanism]Mukherjee, N. et al. | 2004
- 1432
-
ITC 2004 panel: cost of test - taking control Mike Tripp Intel CorporationTripp, M. et al. | 2004
- 1433
-
Is "design to production" the ultimate answer for jitter, noise, and BER challenges for multi GB/s ICs?Li, M. et al. | 2004
- 1434
-
Loopback or not?Yamaguchi, T. / IEEE et al. | 2004
- 1434
-
Loopback or not? (loopback testing)Yamaguchi, T.J. et al. | 2004
- 1435
-
Options for High-Volume Test of Multi-GBIs PortsJohnson, J. / IEEE et al. | 2004
- 1435
-
Options for high-volume test of multi-Gb/s portsJohnson, J.C. et al. | 2004
- 1436
-
Is "Heisenberg uncertainty principle" hold for designing and testing multiple Gb/s ICs ?Li, M. et al. | 2004
- 1436
-
Will "Heisenberg Uncertainty Principle" Hold For Designing and Testing Multiple GB/s ICs?Li, M. / IEEE et al. | 2004
- 1437
-
A little DFT goes a long way when testing multi-Gb/s I/O signalsSproch, J. et al. | 2004
- 1438
-
Panel synopsis - diagnosis meets physical failure analysis: how long can we succeed?Okuda, Y. et al. | 2004
- 1441
-
Diagnosis meets physical failure analysis: how long can we succeed?Gattiker, A. et al. | 2004
- 1439
-
Panel 9 - diagnostics vs failure analysisBartenstein, T.W. et al. | 2004
- 1439
-
Diagnostics vs. Failure AnalysisBartenstein, T. / IEEE et al. | 2004
- 1440
-
Global failure localization: we have to, but on what and how?Cole, E.I. et al. | 2004
- 1442
-
Diagnosis meets physical failure analysis: what is needed to succeed?Venkataraman, S. et al. | 2004
- 1443
-
How long can we succeed using the OBIRCH and its derivatives?Nikawa, K. et al. | 2004
- 1444
-
Investment vs. yield relationship for memories in SOCZorian, Y. et al. | 2004
- 1445
-
Memory yield improvement - SoC design perspectiveKhare, J.B. et al. | 2004
- 1446
-
Investment vs. yield relationship for memories and IP in SoCReynick, J.A. et al. | 2004
- 1447
-
Plan ahead for yieldJun Qian, et al. | 2004
- 1448
-
Elimination of traditional functional testing of interface timings at IntelTripp, M. / Mak, T.M. / Meixner, A. et al. | 2004
- 1457
-
Author index| 2004
- 1462
-
Back Cover Page| 2004
- i
-
Proceedings International Test Conference 2004 - Title Page| 2004
- ii
-
Copyright| 2004
- iii
-
Table of Contents| 2004