Regular Expression Pattern Matching Supporting Constrained Repetitions (English)
- New search for: Yun, S.
- New search for: Lee, K.
- New search for: Yun, S.
- New search for: Lee, K.
- New search for: Becker, Jurgen
In:
Reconfigurable computing: architectures tools and applications ARC 2009
5453
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300-305
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2009
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ISBN:
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ISSN:
- Conference paper / Print
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Title:Regular Expression Pattern Matching Supporting Constrained Repetitions
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Contributors:
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Conference:Conference; 5th, Reconfigurable computing: architectures tools and applications ARC 2009 ; 2009 ; Karlsruhe, Germany
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Published in:LECTURE NOTES IN COMPUTER SCIENCE , 5453 ; 300-305
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Publisher:
- New search for: Springer
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Place of publication:Berlin
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Publication date:2009-01-01
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Size:6 pages
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Remarks:Includes bibliographical references and index.
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ISBN:
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ISSN:
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Type of media:Conference paper
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Type of material:Print
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Language:English
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Keywords:
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Source:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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FPGA Design Productivity - A Discussion of the State of the Art and a Research AgendaNelson, B. et al. | 2009
- 2
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Resiliency in Elemental ComputingHassoun, J. et al. | 2009
- 3
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The Colour of Embedded ComputationPhillips, I. et al. | 2009
- 4
-
A HyperTransport 3 Physical Layer Interface for FPGAsLitz, H. / Froening, H. / Bruening, U. et al. | 2009
- 15
-
Parametric Design for Reconfigurable Software-Defined RadioBecker, T. / Luk, W. / Cheung, P.Y.K. et al. | 2009
- 27
-
Hardware/Software FPGA Architecture for Robotics ApplicationsEugenio, J.C.M. / Estrada, M.A. et al. | 2009
- 39
-
Reconfigurable Operator Based Multimedia Embedded ProcessorMenard, D. / Casseau, E. / Khan, S. / Sentieys, O. / Chevobbe, S. / Guyetant, S. / David, R. et al. | 2009
- 50
-
A Protocol for Secure Remote Updates of FPGA ConfigurationsDrimer, S. / Kuhn, M.G. et al. | 2009
- 62
-
FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable ComputingKepa, K. / Morgan, F. / Kosciuszkiewicz, K. / Braun, L. / Hubner, M. / Becker, J. et al. | 2009
- 74
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An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics ApplicationsLanuzza, M. / Zicari, P. / Frustaci, F. / Perri, S. / Corsonello, P. et al. | 2009
- 85
-
Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAsSterpone, L. et al. | 2009
- 97
-
A Novel Local Interconnect Architecture for Variable Grain Logic CellInoue, K. / Amagasaki, M. / Iida, M. / Sueyoshi, T. et al. | 2009
- 110
-
Dynamically Adapted Low Power ASIPsRutzig, M.B. / Beck, A.C.S. / Carro, L. et al. | 2009
- 123
-
Fast Optical Reconfiguration of a Nine-Context DORGANakajima, M. / Watanabe, M. et al. | 2009
- 133
-
Heterogeneous Architecture Exploration: Analysis vs. Parameter SweepKahoul, A. / Constantinides, G.A. / Smith, A.M. / Cheung, P.Y.K. et al. | 2009
- 145
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On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega NetworksFerreira, R. / Damiany, A. / Vendramini, J. / Teixeira, T. / Cardoso, J.M.P. et al. | 2009
- 157
-
A New Datapath Merging Method for Reconfigurable SystemFazlali, M. / Fallah, M.K. / Zolghadr, M. / Zakerolhosseini, A. et al. | 2009
- 169
-
Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC PlatformGuo, X. / Schaumont, P. et al. | 2009
- 181
-
Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher AlgorithmYi, J. / Park, K. / Park, J. / Ro, W.W. et al. | 2009
- 193
-
Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAsZhou, G. / Michalik, H. / Hinsenkamp, L. et al. | 2009
- 204
-
Compiling Techniques for Coarse Grained Runtime Reconfigurable ArchitecturesAlle, M. / Varadarajan, K. / Fell, A. / Nandy, S.K. / Narayan, R. et al. | 2009
- 216
-
Online Task Scheduling for the FPGA-Based Partially Reconfigurable SystemsLu, Y. / Marconi, T. / Bertels, K. / Gaydadjiev, G. et al. | 2009
- 231
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Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number GeneratorSaiprasert, C. / Bouganis, C.-S. / Constantinides, G.A. et al. | 2009
- 243
-
FPGA-Based Anomalous Trajectory Detection Using SOFMAppiah, K. / Hunter, A. / Kluge, T. / Aiken, P. / Dickinson, P. et al. | 2009
- 255
-
SORU: A Reconfigurable Vector Unit for Adaptable Embedded SystemsMoya, J.M. / Rodriguez, J. / Martin, J. / Vallejo, J.C. / Malagon, P. / Araujo, A. / de Goyeneche, J.-M. / Rubio, A. / Romero, E. / Villanueva, D. et al. | 2009
- 261
-
A Parallel Branching Program Machine for Emulation of Sequential CircuitsNakahara, H. / Sasao, T. / Matsuura, M. / Kawamura, Y. et al. | 2009
- 268
-
Memory Sharing Approach for TMR Softcore ProcessorIchinomiya, Y. / Tanoue, S. / Ishida, T. / Amagasaki, M. / Kuga, M. / Sueyoshi, T. et al. | 2009
- 275
-
The Need for Reconfigurable Routers in Networks-on-ChipMatos, D. / Concatto, C. / Carro, L. / Kastensmidt, F. / Susin, A. et al. | 2009
- 281
-
Transparent Dynamic Reconfiguration as a Service of a System-Level MiddlewareRincon, F. / Barba, J. / Moya, F. / Lopez, J.C. / Dondo, J. et al. | 2009
- 287
-
Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes DecoderYazdani, S. / Goubier, T. / Pottier, B. / Dezan, C. et al. | 2009
- 293
-
Tile-Based Fault Tolerant Approach Using Partial ReconfigurationKanamaru, A. / Kawai, H. / Yamaguchi, Y. / Yasunaga, M. et al. | 2009
- 300
-
Regular Expression Pattern Matching Supporting Constrained RepetitionsYun, S. / Lee, K. et al. | 2009
- 306
-
Accelerating Calculations on the RASC Platform: A Case Study of the Exponential FunctionWielgosz, M. / Jamro, E. / Wiatr, K. et al. | 2009
- 312
-
AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet CommunicationsLazaro, J. / Astarloa, A. / Bidarte, U. / Jimenez, J. / Zuloaga, A. et al. | 2009
- 318
-
CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key CiphersTheodoropoulos, D. / Siskos, A. / Pnevmatikatos, D. et al. | 2009
- 324
-
Object Tracking and Motion Capturing in Hardware-Accelerated Multi-camera SystemLeephokhanon, S. / Wiangtong, T. et al. | 2009
- 330
-
Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined ArchitectureWeber, R. / Rettberg, A. et al. | 2009
- 336
-
A Hardware Accelerated Simulation Environment for Spiking Neural NetworksGlackin, B. / Harkin, J. / McGinnity, T.M. / Maguire, L.P. et al. | 2009
- 342
-
Survey of Advanced CABAC Accelerator Architectures for Future MultimediaJan, Y. / Jozwiak, L. et al. | 2009
- 349
-
Real Time Simulation in Floating Point Precision Using FPGA ComputingApopei, B. / Mills, A. / Dodd, T. / Thompson, H. et al. | 2009
- 355
-
A Hardware Analysis of Twisted Edwards Curves for an Elliptic Curve CryptosystemBaldwin, B. / Moloney, R. / Byrne, A. / McGuire, G. / Marnane, W.P. et al. | 2009
- 362
-
A Seamless Virtualization Approach for Transparent Dynamical Function Mapping Targeting Heterogeneous and Reconfigurable SystemsBuchty, R. / Kramer, D. / Nowak, F. / Karl, W. et al. | 2009
- 368
-
Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical SimulatorIshimori, T. / Yamada, H. / Shibata, Y. / Osana, Y. / Yoshimi, M. / Nishikawa, Y. / Amano, H. / Funahashi, A. / Hiroi, N. / Oguri, K. et al. | 2009
- 374
-
ACCFS - Operating System Integration of Computational Accelerators Using a VFS ApproachHeinig, A. / Strunk, J. / Rehm, W. / Schick, H. et al. | 2009
- 374
-
ACCFS - operating system integration of computational accelerators using a XFS approachHeinig, Andreas / Strunk, Jochen / Rehm, Wolfgang / Schick, Heiko et al. | 2009
- 380
-
A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA PlatformsHappe, M. / Lubbers, E. / Platzner, M. et al. | 2009