A Fully Integrated Architecture for Fast and Accurate Programming of Floating Gates Over Six Decades of Current (English)
- New search for: Basu, A.
- New search for: Hasler, P. E.
- New search for: Basu, A.
- New search for: Hasler, P. E.
In:
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS
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19
, 6
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953-962
;
2011
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ISSN:
- Article (Journal) / Print
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Title:A Fully Integrated Architecture for Fast and Accurate Programming of Floating Gates Over Six Decades of Current
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Contributors:Basu, A. ( author ) / Hasler, P. E. ( author )
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Published in:IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS ; 19, 6 ; 953-962
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Publisher:
- New search for: INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS
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Publication date:2011-01-01
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Size:10 pages
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ISSN:
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Type of media:Article (Journal)
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Type of material:Print
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Language:English
- New search for: 321.395
- Further information on Dewey Decimal Classification
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Classification:
DDC: 321.395 -
Source:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Table of contents – Volume 19, Issue 6
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 925
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A Low-Power High-Performance H.264/AVC Intra-Frame Encoder for 1080pHD VideoHuang-Chih Kuo, / Li-Cian Wu, / Hao-Ting Huang, / Sheng-Tsung Hsu, / Youn-Long Lin, et al. | 2011
- 925
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VLSI Design - A Low-Power High-Performance H.264/AVC Intra-Frame Encoder for 1080pHD VideoKuo, H-C et al. | 2011
- 939
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A Novel Pixel Design for AM-OLED Displays Using Nanocrystalline Silicon TFTsChen-Wei Lin, / Chao, M C / Yen-Shih Huang, et al. | 2011
- 953
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Memory Design - A Fully Integrated Architecture for Fast and Accurate Programming of Floating Gates Over Six Decades of CurrentBasu, A et al. | 2011
- 953
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A Fully Integrated Architecture for Fast and Accurate Programming of Floating Gates Over Six Decades of CurrentBasu, Arindam / Hasler, Paul E et al. | 2011
- 963
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A Dynamic Longest Prefix Matching Content Addressable Memory for IP RoutingMaurya, S K / Clark, L T et al. | 2011
- 973
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Autonomous, Multilevel Ring Tuning Scheme for Post-Silicon Active Clock Deskewing Over Intra-Die VariationsMueller, J G / Saleh, R A et al. | 2011
- 973
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Clocking - Autonomous, Multilevel Ring Tuning Scheme for Post-Silicon Active Clock Deskewing Over Intra-Die VariationsMueller, J G et al. | 2011
- 987
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Process Modeling/Simulation - Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge RoughnessYe, Y et al. | 2011
- 987
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Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge RoughnessYun Ye, / Liu, Frank / Min Chen, / Nassif, Sani / Yu Cao, et al. | 2011
- 997
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On Reducing Hidden Redundant Memory Accesses for DSP ApplicationsMeng Wang, / Zili Shao, / Jingling Xue, et al. | 2011
- 997
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VLSI Architectures - On Reducing Hidden Redundant Memory Accesses for DSP ApplicationsWang, M et al. | 2011
- 1011
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A Dedicated Monitoring Infrastructure for Multicore ProcessorsJia Zhao, / Madduri, S / Vadlamani, R / Burleson, W / Tessier, R et al. | 2011
- 1023
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A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead LogicAbdel-Hafeez, S / Gordon-Ross, A et al. | 2011
- 1034
-
A Flexible Parallel Hardware Architecture for AdaBoost-Based Real-Time Object DetectionKyrkou, C / Theocharides, T et al. | 2011
- 1048
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Design Optimizations for Tiled Partially Reconfigurable SystemsKoester, M / Luk, W / Hagemeyer, J / Porrmann, M / Ruckert, U et al. | 2011
- 1048
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Reconfigurable Systems - Design Optimizations for Tiled Partially Reconfigurable SystemsKoester, M et al. | 2011
- 1062
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EGRA: A Coarse Grained Reconfigurable Architectural TemplateAnsaloni, Giovanni / Bonzini, Paolo / Pozzi, Laura et al. | 2011
- 1075
-
A Distributed Filter Within a Switching Converter for Application to 3-D Integrated CircuitsRosenfeld, J / Friedman, E G et al. | 2011
- 1075
-
Analog Design/3-D Circuits - A Distributed Filter Within a Switching Converter for Application to 3-D Integrated CircuitsRosenfeld, J et al. | 2011
- 1086
-
Robust Two-Phase RZ Asynchronous SoC InterconnectsElrabaa, M E S et al. | 2011
- 1086
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TRANSACTIONS BRIEFS - Robust Two-Phase RZ Asynchronous SoC InterconnectsElrabaa, M E S et al. | 2011
- 1090
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An Accumulator—Based Test-Per-Clock SchemeMagos, D / Voyiatzis, I / Tarnick, S et al. | 2011
- 1094
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On Functional Broadside Tests With Functional Propagation ConditionsPomeranz, I / Reddy, S M et al. | 2011
- 1099
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A Reduced-Complexity Architecture for LDPC Layered Decoding SchemesSangmin Kim, / Sobelman, Gerald E / Lee, Hanho et al. | 2011
- 1104
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Broadside and Functional Broadside Tests for Partial-Scan CircuitsPomeranz, I / Reddy, S M et al. | 2011
- 1108
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Static Test Data Volume Reduction Using Complementation or Modulo-$M$ AdditionPomeranz, I / Reddy, S M et al. | 2011
- 1108
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Static Test Data Volume Reduction Using Complementation or Modulo- Formula Not Shown AdditionPomeranz, I. / Reddy, S. M. et al. | 2011
- 1113
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A Low-Power and Portable Spread Spectrum Clock Generator for SoC ApplicationsDuo Sheng, / Ching-Che Chung, / Chen-Yi Lee, et al. | 2011
- 1118
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A 1.2-V Piecewise Curvature-Corrected Bandgap Reference in 0.5 $\mu$m CMOS ProcessJing-Hu Li, / Xing-bao Zhang, / Ming-yan Yu, et al. | 2011
- 1118
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A 1.2-V Piecewise Curvature-Corrected Bandgap Reference in 0.5 Formula Not Shown m CMOS ProcessLi, J. H. / Zhang, X. B. / Yu, M. Y. et al. | 2011
- 1120
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A 1.2-V Piecewise Curvature-Corrected Bandgap Reference in 0.5 μm CMOS ProcessLi, J-H et al. | 2011
- 1123
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors| 2011
- 1124
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IEEE Foundation| 2011
- C1
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Table of contents| 2011
- C2
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information| 2011
- C3
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information| 2011