TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC (English)
- New search for: Jung, M.
- New search for: Mitra, J.
- New search for: Pan, D. Z.
- New search for: Lim, S. K.
- New search for: Jung, M.
- New search for: Mitra, J.
- New search for: Pan, D. Z.
- New search for: Lim, S. K.
In:
IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
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31
, 8
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1194-1207
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2012
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ISSN:
- Article (Journal) / Print
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Title:TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC
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Contributors:
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Published in:IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS ; 31, 8 ; 1194-1207
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Publisher:
- New search for: IEEE INSTITUTE OF ELECTRICAL AND ELECTRONICS
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Publication date:2012-01-01
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Size:14 pages
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ISSN:
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Type of media:Article (Journal)
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Type of material:Print
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Language:English
- New search for: 621.38173 / 621
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Table of contents – Volume 31, Issue 8
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1145
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MARS: Matching-Driven Analog SizingEick, Michael / Graeb, Helmut E. et al. | 2012
- 1145
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Analog, Mixed-Signal, and RF Circuits - MARS: Matching-Driven Analog SizingEick, M et al. | 2012
- 1159
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Embedded Systems - TCEC: Temperature and Energy-Constrained Scheduling in Real-Time Multitasking SystemsQin, X et al. | 2012
- 1159
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TCEC: Temperature and Energy-Constrained Scheduling in Real-Time Multitasking SystemsQin, Xiaoke / Wang, Weixun / Mishra, Prabhat et al. | 2012
- 1169
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FIR Filter Synthesis Based on Interleaved Processing of Coefficient Generation and Multiplier-Block SynthesisKong, Byeong Yong / Park, In-Cheol et al. | 2012
- 1169
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High-Level Synthesis - FIR Filter Synthesis Based on Interleaved Processing of Coefficient Generation and Multiplier-Block SynthesisKong, B Y et al. | 2012
- 1180
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Time-Domain Analysis of Large-Scale Circuits by Matrix Exponential Method With Adaptive ControlWeng, Shih-Hung / Chen, Quan / Cheng, Chung-Kuan et al. | 2012
- 1180
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Modeling and Simulation - Time-Domain Analysis of Large-Scale Circuits by Matrix Exponential Method With Adaptive ControlWeng, S-H et al. | 2012
- 1194
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TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D ICJung, Moongon / Mitra, Joydeep / Pan, David Z. / Lim, Sung Kyu et al. | 2012
- 1194
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Physical Design - TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D ICJung, M et al. | 2012
- 1208
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An Analytical Placer for VLSI Standard Cell PlacementChen, Jianli / Zhu, Wenxing et al. | 2012
- 1222
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Variation-Aware Clock Network Design Methodology for Ultralow Voltage (ULV) CircuitsZhao, Xin / Tolbert, Jeremy R. / Mukhopadhyay, Saibal / Lim, Sung Kyu et al. | 2012
- 1235
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A Dynamically Adjusting Gracefully Degrading Link-Level Fault-Tolerant Mechanism for NoCsVitkovskiy, Arseniy / Soteriou, Vassos / Nicopoulos, Chrysostomos et al. | 2012
- 1235
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System-Level Design - A Dynamically Adjusting Gracefully Degrading Link-Level Fault-Tolerant Mechanism for NoCsVitkovskiy, A et al. | 2012
- 1249
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Automatic TLM Fault Localization for SystemCLe, Hoang M. / Grosse, Daniel / Drechsler, Rolf et al. | 2012
- 1263
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On Signal Selection for Visibility Enhancement in Trace-Based Post-Silicon ValidationLiu, Xiao / Xu, Qiang et al. | 2012
- 1263
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Test - On Signal Selection for Visibility Enhancement in Trace-Based Post-Silicon ValidationLiu, X et al. | 2012
- 1275
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Testability-Driven Statistical Path SelectionChung, Jaeyong / Xiong, Jinjun / Zolotov, Vladimir / Abraham, Jacob A. et al. | 2012
- 1288
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Inferring Assertion for Complementary SynthesisShen, ShengYu / Qin, Ying / Wang, KeFei / Pang, ZhengBin / Zhang, JianMin / Li, SiKun et al. | 2012
- 1288
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SHORT PAPERS - Inferring Assertion for Complementary SynthesisShen, S et al. | 2012
- 1293
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A Novel Method for Reducing Metal Variation With Statistical Static Timing AnalysisForeman, Eric A. / Habitz, Peter A. / Cheng, Ming-C. / Visweswariah, Chandu et al. | 2012
- 1297
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Concurrent Generation of Concurrent Programs for Post-Silicon ValidationAdir, Allon / Nahir, Amir / Ziv, Avi et al. | 2012
- 1303
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IEEE Copyright Form| 2012
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Table of contents| 2012
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information| 2012
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information| 2012
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors| 2012