Beyond the Roofline: Cache-Aware Power and Energy-Efficiency Modeling for Multi-Cores (English)
- New search for: Ilic, A.
- New search for: Pratas, F.
- New search for: Sousa, L.
- New search for: Ilic, A.
- New search for: Pratas, F.
- New search for: Sousa, L.
In:
IEEE TRANSACTIONS ON COMPUTERS
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66
, 1
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52-58
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2017
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ISSN:
- Article (Journal) / Print
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Title:Beyond the Roofline: Cache-Aware Power and Energy-Efficiency Modeling for Multi-Cores
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Contributors:
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Published in:IEEE TRANSACTIONS ON COMPUTERS ; 66, 1 ; 52-58
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Publisher:
- New search for: IEEE INSTITUTE OF ELECTRICAL AND ELECTRONICS
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Publication date:2017-01-01
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Size:7 pages
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ISSN:
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Type of media:Article (Journal)
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Type of material:Print
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Language:English
- New search for: 621.38195 / 621.3
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Table of contents – Volume 66, Issue 1
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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2016 Index IEEE Transactions on Computers Vol. 65| 2017
- 1
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State of the JournalMontuschi, Paolo et al. | 2017
- 3
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A Custom Accelerator for Homomorphic Encryption ApplicationsOzturk, Erdinc / Doroz, Yarkin / Savas, Erkay / Sunar, Berk et al. | 2017
- 17
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Adaptive Scheduling of Task Graphs with Dynamic ResilienceMenglan Hu, / Jun Luo, / Yang Wang, / Veeravalli, Bharadwaj et al. | 2017
- 24
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An Analytical Model for Coding-Based Reprogramming Protocols in Lossy Wireless Sensor NetworksJun-Wei Li, / Shi-Ning Li, / Yu Zhang, / Tao Gu, / Yee Wei Law, / Zhe Yang, / Xingshe Zhou, / Palaniswami, Marimuthu et al. | 2017
- 38
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An On-Chip Error Detection Method to Reduce the Post-Silicon Debug TimeHyunggoy Oh, / Taewoo Han, / Inhyuk Choi, / Sungho Kang, et al. | 2017
- 45
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A SISO Register Circuit Tailored for Input Data with Low Transition ProbabilityNapoli, Ettore / Castellano, Gerardo / De Caro, Davide / Esposito, Darjn / Petra, Nicola / Strollo, Antonio G. M. et al. | 2017
- 52
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Beyond the Roofline: Cache-Aware Power and Energy-Efficiency Modeling for Multi-CoresIlic, Aleksandar / Pratas, Frederico / Sousa, Leonel et al. | 2017
- 59
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Construction of Rotation Symmetric S-Boxes with High Nonlinearity and Improved DPA ResistivityMazumdar, Bodhisatwa / Mukhopadhyay, Debdeep et al. | 2017
- 73
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DaDianNao: A Neural Network SupercomputerTao Luo, / Shaoli Liu, / Ling Li, / Yuqing Wang, / Shijin Zhang, / Tianshi Chen, / Zhiwei Xu, / Temam, Olivier / Yunji Chen, et al. | 2017
- 89
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Hierarchical Multipartite Function EvaluationShen-Fu Hsiao, / Chia-Sheng Wen, / Yi-Hau Chen, / Kuei-Chun Huang, et al. | 2017
- 100
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Latch-Based Structure: A High Resolution and Self-Reference Technique for Hardware Trojan DetectionZarrinchian, Ghobad / Zamani, Morteza Saheb et al. | 2017
- 114
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Multi-Inherited Search Tree for Dynamic IP Router-TablesPo-Cheng Hsu, / Sun-Yuan Hsieh, et al. | 2017
- 127
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Short Code: An Efficient RAID-6 MDS Code for Optimizing Degraded Reads and Partial Stripe WritesYingxun Fu, / Jiwu Shu, / Xianghong Luo, / Zhirong Shen, / Qingda Hu, et al. | 2017
- 138
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The Repetitive Turn Model for Adaptive RoutingMinghua Tang, / Xiaola Lin, / Palesi, Maurizio et al. | 2017
- 147
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Thermal Safe Power (TSP): Efficient Power Budgeting for Heterogeneous Manycore Systems in Dark SiliconPagani, Santiago / Khdr, Heba / Jian-Jia Chen, / Shafique, Muhammad / Minming Li, / Henkel, Jorg et al. | 2017
- 163
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Towards an Energy-Efficient Anomaly-Based Intrusion Detection Engine for Embedded SystemsViegas, Eduardo / Santin, Altair O. / França, Andre / Jasinski, Ricardo / Pedroni, Volnei A. / Oliveira, Luiz S. et al. | 2017
- 178
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2016 Reviewers List Formula Not Shown| 2017
- 178
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2016 Reviewers List$^\ast$| 2017