Approaching Speed-of-light Distortionless Communication for On-chip Interconnect (English)
- New search for: Zhu, Haikun
- New search for: Shi, Rui
- New search for: Cheng, Chung-Kuan
- New search for: Chen, Hongyu
- New search for: Zhu, Haikun
- New search for: Shi, Rui
- New search for: Cheng, Chung-Kuan
- New search for: Chen, Hongyu
In:
2007 Asia and South Pacific Design Automation Conference
;
684-689
;
2007
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ISBN:
- Conference paper / Electronic Resource
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Title:Approaching Speed-of-light Distortionless Communication for On-chip Interconnect
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Contributors:Zhu, Haikun ( author ) / Shi, Rui ( author ) / Cheng, Chung-Kuan ( author ) / Chen, Hongyu ( author )
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Published in:
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Publisher:
- New search for: IEEE
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Publication date:2007-01-01
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Size:859637 byte
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ISBN:
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DOI:
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Type of media:Conference paper
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Type of material:Electronic Resource
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Language:English
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 316
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Symbolic Model Checking of Analog/Mixed-Signal CircuitsWalter, David / Little, Scott / Seegmiller, Nicholas / Myers, Chris J. / Yoneda, Tomohiro et al. | 2007
- 774
-
A Current-based Method for Short Circuit Power Calculation under Noisy Input WaveformsFatemi, Hanif / Nazarian, Shahin / Pedram, Massoud et al. | 2007
- 932
-
Trace Compaction using SAT-based Reachability AnalysisSafarpour, Sean / Veneris, Andreas / Mangassarian, Hratch et al. | 2007
- 74
-
PLLSim - An Ultra Fast Bang-Bang Phase Locked Loop Simulation ToolChan, Michael / Postula, Adam / Ding, Yong et al. | 2007
- 56
-
System Architecture for Software PeripheralsChoudhuri, Siddharth / Givargis, Tony et al. | 2007
- 286
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A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional UnitsShiro, Takeshi / Abe, Masaaki / Sakanushi, Keishi / Takeuchi, Yoshinori / Imai, Masaharu et al. | 2007
- 1
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A 2.8-V multibit complex bandpass Delta Sigma AD modulator in 0.18 micrometer CMOSSan, H. / Jingu, Y. / Wada, H. / Hagiwara, H. / Hayakawa, A. / Kobayashi, H. / Hotta, M. et al. | 2007
- 792
-
On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan DesignLu, Chao-Hung / Chen, Hung-Ming / Liu, Chien-Nan Jimmy et al. | 2007
- 38
-
Software Performance Estimation in MPSoC DesignOyamada, Marcio / Wagner, Flavio R. / Bonaciu, Marius / Cesario, Wander / Jerraya, Ahmed et al. | 2007
- 13
-
Coupling-aware Dummy Metal Insertion for LithographyDeng, Liang / Wong, Martin D. F. / Chao, Kai-Yuan / Xiang, Hua et al. | 2007
- 920
-
Micro-architecture Pipelining Optimization with Throughput-Aware FloorplanningMa, Yuchun / Li, Zhuoyuan / Cong, Jason / Hong, Xianlong / Reinman, Glenn / Dong, Sheqin / Zhou, Qiang et al. | 2007
- 492
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MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-ChipKumar, T.S. Rajesh / Ravikumar, C.P. / Govindarajan, R. et al. | 2007
- 1
-
Model Based Layout Pattern Dependent Metal Filling Algorithm for Improved Chip Surface Uniformity in the Copper ProcessSinha, Subarna / Luo, Jianfeng / Chiang, Charles et al. | 2007
- 866
-
Flow Time Minimization under Energy ConstraintsChen, Jian-Jia / Iwama, Kazuo / Kuo, Tei-Wei / Lu, Hseuh-I et al. | 2007
- 565
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Modeling the Overshooting Effect for CMOS Inverter in Nanometer TechnologiesHuang, Zhangcai / Yu, Hong / Kurokawa, Atsushi / Inoue, Yasuaki et al. | 2007
- 486
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Signal-to-Memory Mapping Analysis for Multimedia Signal ProcessingLuican, Ilie I. / Zhu, Hongwei / Balasa, Florin et al. | 2007
- 262
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A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree ConstructionWu, Pei-Ci / Gao, Jhih-Rong / Wang, Ting-Chi et al. | 2007
- 100
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Design of Active Substrate Noise Canceller using Power Supply di/dt DetectorKazama, Taisuke / Nakura, Toru / Ikeda, Makoto / Asada, Kunihiro et al. | 2007
- 268
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A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque BlocksYan, Tan / Li, Shuting / Takashima, Yasuhiro / Murata, Hiroshi et al. | 2007
- 872
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Integrating Power Management into Distributed Real-time Systems at Very Low Implementation CostGorjiara, Bita / Bagherzadeh, Nader / Chou, Pai et al. | 2007
- 823
-
AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCsBahukudumbi, Sudarshan / Ozev, Sule / Chakrabarty, Krishnendu / Iyengar, Vikram et al. | 2007
- 1
-
Predicting the performance and reliability of carbon nanotube bundles for on-chip interconnectNieuwoudt, A. / Mondal, M. / Massoud, Y. et al. | 2007
- 432
-
Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologiesGielen, Georges G.E. et al. | 2007
- 50
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Creating Explicit Communication in SoC Models Using Interactive Re-CodingChandraiah, Pramod / Peng, Junyu / Domer, Rainer et al. | 2007
- 547
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An Efficient Computation of Statistically Critical Sequential Paths Under RetimingEkpanyapong, Mongkol / Zhao, Xin / Lim, Sung Kyu et al. | 2007
- 221
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Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFMHuang, Jun-Fu / Chang, Victor C.Y. / Liu, Sally / Doong, Kelvin Y.Y. / Chang, Keh-Jeng et al. | 2007
- 763
-
Fast Placement Optimization of Power Supply PadsZhong, Yu / Wong, Martin D. F. et al. | 2007
- 798
-
Voltage Island Generation under Performance Requirement for SoC DesignsMak, Wai-Kei / Chen, Jr-Wei et al. | 2007
- 384
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Abstract, Multifaceted Modeling of Embedded Processors for System Level DesignSchirner, Gunar / Gerstlauer, Andreas / Domer, Rainer et al. | 2007
- 609
-
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design SpaceLiu, Jianhua / Zhu, Yi / Zhu, Haikun / Cheng, Chung-Kuan / Lillis, John et al. | 2007
- 86
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Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube SwitchesBhunia, Swarup / Tabib-Azar, Massood / Saab, Daniel et al. | 2007
- 890
-
CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-timePeddersen, Jorgen / Parameswaran, Sri et al. | 2007
- 274
-
LEAF: A System Level Leakage-Aware Floorplanner for SoCsGupta, Aseem / Dutt, Nikil D. / Kurdahi, Fadi J. / Khouri, Kamal S. / Abadir, Magdy S. et al. | 2007
- 878
-
A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process VariationGoudarzi, Maziar / Ishihara, Tohru / Yasuura, Hiroto et al. | 2007
- 571
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Flow-Through-Queue based Power Management for Gigabit Ethernet ControllerJung, Hwisung / Hwang, Andy / Pedram, Massoud et al. | 2007
- 147
-
ECO-system: Embracing the Change in PlacementRoy, Jarrod A. / Markov, Igor L. et al. | 2007
- 7
-
Fast and Accurate OPC for Standard-Cell LayoutsPawlowski, David M. / Deng, Liang / Wong, Martin D. F. et al. | 2007
- 19
-
Fast Buffer Insertion for Yield Optimization Under Process VariationsChen, Ruiming / Zhou, Hai et al. | 2007
- 24
-
A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew YieldLiu, Bao / Kahng, Andrew B. / Xu, Xu / Hu, Jiang / Venkataraman, Ganesh et al. | 2007
- 32
-
Control-Flow Aware Communication and Conflict Analysis of Parallel ProcessesSiebenborn, Axel / Viehl, Alexander / Bringmann, Oliver / Rosenstiel, Wolfgang et al. | 2007
- 44
-
Effective OpenMP Implementation and Translation For Multiprocessor System-On-Chip without Using OSJeun, Woo-Chul / Ha, Soonhoi et al. | 2007
- 62
-
A New Boundary Element Method for Multiple-Frequency Parameter Extraction of Lossy SubstratesWang, Xiren / Yu, Wenjian / Wang, Zeyi et al. | 2007
- 68
-
Expression of Concern: Hierarchical Optimization Methodology for Wideband Low Noise AmplifiersNieuwoudt, Arthur / Ragheb, Tamer / Massoud, Yehia et al. | 2007
- 80
-
A Programmable Fully-Integrated GPS receiver in 0.18 μm CMOS with Test CircuitsJenabi, Mahta / Riahi, Noushin / Fotowat-Ahmady, Ali et al. | 2007
- 92
-
A 1Tb/s 3W Inductive-Coupling Transceiver ChipMiura, Noriyuki / Kuroda, Tadahiro et al. | 2007
- 94
-
22-29GHz Ultra-Wideband CMOS Pulse Generator for Collision Avoidance Short Range Vehicular Radar SensorsOncu, Ahmet / Badalawa, B.B.M. Wasanthamala / Wang, Tong / Fujishima, Minoru et al. | 2007
- 96
-
A 2.8-V Multibit Complex Bandpass ΔΣAD Modulator in 0.18μm CMOSSan, H. / Jingu, Y. / Wada, H. / Hagiwara, H. / Hayakawa, A. / Kobayashi, H. / Hotta, M. et al. | 2007
- 98
-
A Wideband CMOS LC-VCO Using Variable InductorOhashi, Kazuma / Ito, Yusaku / Yoshihara, Yoshiaki / Okada, Kenichi / Masu, Kazuya et al. | 2007
- 102
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A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES InterfacesHsu, Yu-Hao / Kao, Min-Sheng / Tzeng, Hou-Cheng / Chiu, Ching-Te / Wu, Jen-Ming / Hsu, Shuo-Hung et al. | 2007
- 104
-
Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self CompensationFukuda, Satoshi / Kawazoe, Daisuke / Okada, Kenichi / Masu, Kazuya et al. | 2007
- 106
-
Psuedo-Millimeter-Wave Up-Conversion Mixer with On-Chip Balun for Vehicular Radar SystemsLai, Ivan / Fujishima, Minoru et al. | 2007
- 108
-
Improving Execution Speed of FPGA using Dynamically Reconfigurable TechniquePantonial, Roel / Khan, Md. Ashfaquzzaman / Miyamoto, Naoto / Kotani, Koji / Sugawa, Shigetoshi / Ohmi, Tadahiro et al. | 2007
- 110
-
Single-Issue 1500MIPS Embedded DSP with Ultra Compact CodesLin, Li-Chun / Ou, Shih-Hao / Lin, Tay-Jyi / Deng, Siang-Den / Liu, Chih-Wei et al. | 2007
- 112
-
A Highly Integrated 8mW H.264/AVC Main Profile Real-time CIF Video Decoder on a 16MHz SoC PlatformPeng, Huan-Kai / Lee, Chun-Hsin / Chen, Jian-Wen / Lo, Tzu-Jen / Chang, Yung-Hung / Hsu, Sheng-Tsung / Lin, Yuan-Chun / Chao, Ping / Hung, Wei-Cheng / Jan, Kai-Yuan et al. | 2007
- 114
-
Configurable AMBA On-Chip Real-Time Signal TracerKao, Chung-Fu / Lin, Chi-Hung / Huang, Ing-Jer et al. | 2007
- 116
-
Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor LogicMatsunaga, S. / Hanyu, T. / Kimura, H. / Nakamura, T. / Takasu, H. et al. | 2007
- 118
-
A Multi-Drop Transmission-Line Interconnect in Si LSISeita, Junki / Ito, Hiroyuki / Okada, Kenichi / Sato, Takashi / Masu, Kazuya et al. | 2007
- 120
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A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS TechnologyKuboki, Takeshi / Tsuchiya, Akira / Onodera, Hidetoshi et al. | 2007
- 122
-
A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die VariationsSugihara, Y. / Kotani, M. / Katsuki, K. / Kobayashi, K. / Onodera, H. et al. | 2007
- 124
-
A 0.35um CMOS 1,632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSIWatanabe, Minoru / Kobayashi, Fuminori et al. | 2007
- 126
-
Low-Power High-Speed 180-nm CMOS Clock DriversEnomoto, Tadayoshi / Nagayama, Suguru / Kobayashi, Nobuaki et al. | 2007
- 128
-
Fast Analytic Placement using Minimum Cost FlowAgnihotri, Ameya R. / Madden, Patrick H. et al. | 2007
- 135
-
FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion ControlViswanathan, Natarajan / Pan, Min / Chu, Chris et al. | 2007
- 141
-
Hippocrates: First-Do-No-Harm Detailed PlacementRen, Haoxing / Pan, David Z. / Alpert, Charles J. / Nam, Gi-Joon / Villarrubia, Paul et al. | 2007
- 153
-
Bisection Based Placement for the X ArchitectureOno, Satoshi / Tilak, Sameer / Madden, Patrick H. et al. | 2007
- 159
-
Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded SystemsJun, Minje / Bang, Kwanhu / Lee, Hyuk-Jun / Chang, Naehyuck / Chung, Eui-Young et al. | 2007
- 165
-
A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC BusesLin, Bu-Ching / Lee, Geeng-Wei / Huang, Juinn-Dar / Jou, Jing-Yang et al. | 2007
- 171
-
Communication Architecture Synthesis of Cascaded Bus MatrixYoo, Junhee / Lee, Dongwook / Yoo, Sungjoo / Choi, Kiyoung et al. | 2007
- 178
-
Topology exploration for energy efficient intra-tile communicationGuo, Jin / Papanikolaou, Antonis / Catthoor, Francky et al. | 2007
- 184
-
Application Specific Network-on-Chip Design with Guaranteed Quality Approximation AlgorithmsSrinivasan, Krishnan / Chatha, Karam S. / Konjevod, Goran et al. | 2007
- 191
-
Thermal-driven Symmetry Constraint for Analog Layout with CBL RepresentationLiu, Jiayi / Dong, Sheqin / Ma, Yuchun / Di Long, / Hong, Xianlong et al. | 2007
- 197
-
A Graph Reduction Approach to Symbolic Circuit AnalysisShi, Guoyong / Chen, Weiwei / Shi, C.-J. Richard et al. | 2007
- 203
-
Robust Analog Circuit Sizing Using Ellipsoid Method and Affine ArithmeticLiu, Xuexin / Luk, Wai-Shing / Song, Yu / Tang, Pushan / Zeng, Xuan et al. | 2007
- 209
-
WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory DesignZhang, Peng / Luk, Wai-Shing / Song, Yu / Tong, Jiarong / Tang, Pushan / Zeng, Xuan et al. | 2007
- 215
-
Structured Placement with Topological Regularity EvaluationNakatake, Shigetoshi et al. | 2007
- 226
-
DFM reality in sub-nanometer IC designVerghese, Nishath / Hurat, Philippe et al. | 2007
- 232
-
DFM/DFY practices during physical designs for timing, signal integrity, and powerChen, Shi-Hao / Chu, Ke-Cheng / Lin, Jiing-Yuan / Tsai, Cheng-Hong et al. | 2007
- 238
-
Recent Research and Emerging Challenges in Physical Design for Manufacturability/ReliabilityLin, Chung-Wei / Tsai, Ming-Chao / Lee, Kuang-Yao / Chen, Tai-Chen / Wang, Ting-Chi / Chang, Yao-Wen et al. | 2007
- 244
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A Novel Performance-Driven Topology Design AlgorithmPan, Min / Chu, Chris / Patra, Priyadarshan et al. | 2007
- 250
-
FastRoute 2.0: A High-quality and Efficient Global RouterPan, Min / Chu, Chris et al. | 2007
- 256
-
DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing AlgorithmCao, Zhen / Jing, Tong / Xiong, Jinjun / Hu, Yu / He, Lei / Hong, Xianlong et al. | 2007
- 280
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Protocol Transducer Synthesis using Divide and Conquer approachWatanabe, Shota / Seto, Kenshu / Ishikawa, Yuji / Komatsu, Satoshi / Fujita, Masahiro et al. | 2007
- 292
-
Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline ArchitectureKawakami, Kentaro / Kuroda, Mitsuhiko / Kawaguchi, Hiroshi / Yoshimoto, Masahiko et al. | 2007
- 298
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Architectural Optimizations for Text to Speech Synthesis in Embedded SystemsDey, Soumyajit / Kedia, Monu / Basu, Anupam et al. | 2007
- 304
-
Deeper Bound in BMC by Combining Constant Propagation and AbstractionArmoni, Roy / Fix, Limor / Fraer, Ranan / Heyman, Tamir / Vardi, Moshe / Vizel, Yakir / Zbar, Yael et al. | 2007
- 310
-
Efficient BMC for Multi-Clock Systems with Clocked SpecificationsGanai, Malay K / Gupta, Aarti et al. | 2007
- 324
-
Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware EmulationBoule, Marc / Zilic, Zeljko et al. | 2007
- 330
-
Model-based Programming Environment of Embedded Software for MPSoCHa, Soonhoi et al. | 2007
- 336
-
RTOS and Codesign Toolkit for Multiprocessor Systems-on-ChipHonda, Shinya / Tomiyama, Hiroyuki / Takada, Hiroaki et al. | 2007
- 342
-
Energy-Efficient Real-Time Task Scheduling in Multiprocessor DVS SystemsChen, Jian-Jia / Yang, Chuan-Yue / Kuo, Tei-Wei / Shih, Chi-Sheng et al. | 2007
- 350
-
Towards scalable and secure execution platform for embedded systemsHiroaki, Inoue / Edahiro, Masato / Sakai, Junji et al. | 2007
- 355
-
Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor FormYan, Boyuan / Tan, Sheldon X.-D. / Liu, Pu / McGaughy, Bruce et al. | 2007
- 361
-
Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise MethodsDabas, Sandeep / Dong, Ning / Roychowdhury, Jaijeet et al. | 2007
- 367
-
Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial ChaosZou, Yi / Cai, Yici / Zhou, Qiang / Hong, Xianlong / Tan, Sheldon X.-D. / Le Kang, et al. | 2007
- 373
-
Reduced-Order Wide-Band Interconnect Model Realization using Filter-Based Spline InterpolationNieuwoudt, Arthur / Alam, Mehboob / Massoud, Yehia et al. | 2007
- 379
-
Frequency Selective Model Order Reduction via Spectral Zero ProjectionAlam, Mehboob / Nieuwoudt, Arthur / Massoud, Yehia et al. | 2007
- 390
-
Flexible and Executable Hardware/Software Interface Modeling for Multiprocessor SoC Design Using SystemCChureau, Alexandre / Bouchhima, Aimen / Jerraya, Ahmed Amine / Gerin, Patrice / Shen, Hao et al. | 2007
- 396
-
A Retargetable Software Timing Analyzer Using Architecture Description LanguageLi, Xianfeng / Roychoudhury, Abhik / Mitra, Tulika / Mishra, Prabhat / Cheng, Xu et al. | 2007
- 402
-
Automating Logic Rectification by Approximate SPFDsYang, Yu-Shen / Sinha, Subarna / Veneris, Andreas / Brayton, Robert K. et al. | 2007
- 408
-
BddCut: Towards Scalable Symbolic Cut EnumerationLing, Andrew C. / Zhu, Jianwen / Brown, Stephen D. et al. | 2007
- 414
-
Node Mergers in the Presence of Don't CaresPlaza, Stephen M. / Chang, Kai-hui / Markov, Igor L. / Bertacco, Valeria et al. | 2007
- 420
-
Synthesis of Reversible Sequential ElementsChuang, Min-Lun / Wang, Chun-Yao et al. | 2007
- 426
-
Recognition of Fanout-free FunctionsLee, Tsung-Lin / Wang, Chun-Yao et al. | 2007
- 438
-
Challenges to Accuracy for the Design of Deep-Submicron RF-CMOS CircuitsYoshitomi, Sadayuki et al. | 2007
- 442
-
Advanced tools for simulation and design of oscillators/PLLsLai, Xiaolue / Roychowdhury, Jaijeet et al. | 2007
- 450
-
A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography EffectsZhou, Ying / Li, Zhuo / Tian, Yuxin / Shi, Weiping / Liu, Frank et al. | 2007
- 456
-
Simple and Accurate Models for Capacitance Increment due to Metal Fill InsertionKim, Youngmin / Petranovic, Dusan / Sylvester, Dennis et al. | 2007
- 462
-
New Block-Based Statistical Timing Analysis Approaches Without Moment MatchingChen, Ruiming / Zhou, Hai et al. | 2007
- 468
-
Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) MethodMitev, Alexander / Marefat, Michael / Ma, Dongsheng / Wang, Janet et al. | 2007
- 474
-
Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process VariationsTao, Jun / Zeng, Xuan / Cai, Wei / Su, Yangfeng / Zhou, Dian / Chiang, Charles et al. | 2007
- 480
-
Retiming for Synchronous Data Flow GraphsLiveris, N. / Lin, C. / Wang, J. / Zhou, H. / Banerjee, P. et al. | 2007
- 498
-
A Run-Time Memory Protection MethodologySeshua, Udaya / Bussa, Nagaraju / Vermeulen, Bart et al. | 2007
- 504
-
Short-Circuit Compiler Transformation: Optimizing Conditional BlocksGhodrat, Mohammad Ali / Givargis, Tony / Nicolau, Alex et al. | 2007
- 511
-
Optimization of Arithmetic Datapaths with Finite Word-Length OperandsGopalakrishnan, Sivaram / Kalla, Priyank / Enescu, Florian et al. | 2007
- 517
-
Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selectionOchoa-Montiel, M. A. / Al-Hashimi, B. M. / Kollig, P. et al. | 2007
- 523
-
A Parameterized Architecture Model in High Level Synthesis for Image Processing ApplicationsDong, Yazhuo / Dou, Yong et al. | 2007
- 529
-
High-Level Power Estimation and Low-Power Design Space Exploration for FPGAsChen, Deming / Cong, Jason / Fan, Yiping / Zhang, Zhiru et al. | 2007
- 535
-
Numerical Function Generators Using Edge-Valued Binary Decision DiagramsNagayama, Shinobu / Sasao, Tsutomu / Butler, Jon T. et al. | 2007
- 541
-
Clock Skew Scheduling with Delay Padding for Prescribed Skew DomainsLin, Chuan / Zhou, Hai et al. | 2007
- 553
-
Fast Electrical Correction Using Resizing and BufferingKarandikar, Shrirang K. / Alpert, Charles J. / Yildiz, Mehmet C. / Villarrubia, Paul / Quay, Steve / Mahmud, Tuhin et al. | 2007
- 559
-
SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI designRoy, Sanghamitra / Chen, Charlie Chung-Ping et al. | 2007
- 577
-
Approximation Algorithm for Process Mapping on Network Processor ArchitecturesOstler, Chris / Chatha, Karam S. / Konjevod, Goran et al. | 2007
- 583
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Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell ArchitectureKhan, Zahid / Arslan, Tughrul et al. | 2007
- 589
-
VLSI Design of Multi Standard Turbo Decoder for 3G and BeyondAhmed, Imran / Arslan, Tughrul et al. | 2007
- 595
-
A High-Throughput Low-Power AES Cipher for Network ApplicationsLin, Shin-Yi / Huang, Chih-Tsun et al. | 2007
- 601
-
Improving XOR-Dominated Circuits by Exploiting Dependencies between OperandsVerma, Ajay K. / Ienne, Paolo et al. | 2007
- 616
-
An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order OptimizationZhu, Haikun / Zhu, Yi / Cheng, Chung-Kuan / Harris, David M. et al. | 2007
- 622
-
Optimization of Robust Asynchronous Circuits by Local Input Completeness RelaxationJeong, Cheoljoo / Nowick, Steven M. et al. | 2007
- 628
-
Safe Delay Optimization for Physical SynthesisChang, Kai-hui / Markov, Igor L. / Bertacco, Valeria et al. | 2007
- 634
-
Overview on Low Power SoC Design TechnologyUsami, Kimiyoshi et al. | 2007
- 637
-
Development of Low-power and Real-time VC-1/H.264/MPEG-4 Video Processing HardwareHase, Masaru / Akie, Kazushi / Nobori, Masaki / Matsumoto, Keisuke et al. | 2007
- 644
-
Development of Low Power ISDB-T One-Segment Decoder by Mobile Multi-Media Engine SoC (S1G)Mori, K. / Suzuki, M. / Ohara, Y. / Matsuo, S. / Asano, A. et al. | 2007
- 649
-
Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier"Nakajima, Masaitsu / Yamamoto, Takao / Yamasaki, Masayuki / Hosoki, Tetsu / Sumita, Masaya et al. | 2007
- 654
-
Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS CircuitsShin, Youngsoo / Heo, Sewan / Kim, Hyung-Ock / Choi, Jung Yun et al. | 2007
- 660
-
Runtime leakage power estimation technique for combinational circuitsLin, Yu-Shiang / Sylvester, Dennis et al. | 2007
- 666
-
Logic and Layout Aware Voltage Island Generation for Low Power DesignGuo, Liangpeng / Cai, Yici / Zhou, Qiang / Hong, Xianlong et al. | 2007
- 672
-
A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller CostWu, Tsung-Yi / Tzeng, Jr-Luen / Chen, Kuang-Yao et al. | 2007
- 678
-
A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAsHassan, Hassan / Anis, Mohab / Elmasry, Mohamed et al. | 2007
- 684
-
Approaching Speed-of-light Distortionless Communication for On-chip InterconnectZhu, Haikun / Shi, Rui / Cheng, Chung-Kuan / Chen, Hongyu et al. | 2007
- 690
-
Delay Uncertainty Reduction by Interconnect and Gate SplittingAgarwal, Vineet / Sun, Jin / Mitev, Alexander / Wang, Janet et al. | 2007
- 696
-
Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip InterconnectsAkl, Charbel J. / Bayoumi, Magdy A. et al. | 2007
- 702
-
Fast Buffered Delay Estimation Considering Process VariationsFang, Tien-Ting / Wang, Ting-Chi et al. | 2007
- 708
-
Expression of Concern: Predicting the Performance and Reliability of Carbon Nanotube Bundles for On-Chip InterconnectNieuwoudt, Arthur / Mondal, Mosin / Massoud, Yehia et al. | 2007
- 714
-
Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP CoresZhao, Dan / Chandran, Unni / Fujiwara, Hideo et al. | 2007
- 720
-
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional BusesHussin, Fawnizu Azmadi / Yoneda, Tomokazu / Orailoglu, Alex / Fujiwara, Hideo et al. | 2007
- 726
-
An Architecture for Combined Test Data Compression and Abort-on-Fail TestLarsson, Erik / Persson, Jon et al. | 2007
- 732
-
RunBasedReordering: A Novel Approach for Test Data Compression and Scan PowerFang, Hao / Tong, Chenguang / Cheng, Xu et al. | 2007
- 738
-
Systematic Scan ReconfigurationAl-Yamani, Ahmad A. / Devta-Prasanna, Narendra / Gunda, Arun et al. | 2007
- 744
-
Configurable Multi-Processor Platforms for Next Generation Embedded SystemsGoodwin, David / Rowen, Chris / Martin, Grant et al. | 2007
- 747
-
ARM MPCore; The streamlined and scalable ARM11 processor coreHirata, Kazuyuki / Goodacre, John et al. | 2007
- 749
-
Nomadik®: AMobile Multimedia Application Processor PlatformPaganini, Maurizio et al. | 2007
- 751
-
Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk ApproachLe Kang, / Cai, Yici / Zou, Yi / Shi, Jin / Hong, Xianlong / Tan, Sheldon X.-D. et al. | 2007
- 757
-
Timing-Aware Decoupling Capacitance Allocation in Power Distribution NetworksPant, Sanjay / Blaauw, David et al. | 2007
- 768
-
Efficient Second-Order Iterative Methods for IR Drop Analysis in Power GridZhong, Yu / Wong, Martin D. F. et al. | 2007
- 780
-
Thermal-Aware 3D IC Placement Via TransformationCong, Jason / Luo, Guojie / Wei, Jie / Zhang, Yan et al. | 2007
- 786
-
Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture ProfilingMohamood, Fayez / Healy, Michael B. / Lim, Sung Kyu / Lee, Hsien-Hsin S. et al. | 2007
- 804
-
Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board CodesignLee, Ren-Jie / Lai, Ming-Fang / Chen, Hung-Ming et al. | 2007
- 810
-
A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited CaptureWang, Seongmoon / Wei, Wenlong et al. | 2007
- 817
-
Warning: Launch off Shift Tests for Delay Faults May Contribute to Test EscapesZhang, Zhuo / Reddy, Sudhakar M. / Pomeranz, Irith et al. | 2007
- 829
-
Fault Dictionary Size Reduction for Million-Gate Large CircuitsHong, Yu-Ru / Huang, Juinn-Dar et al. | 2007
- 835
-
Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter TechnologiesLee, Chun-Yi / Lin, Hung-Mao / Wang, Fang-Min / Li, James Chien-Mo et al. | 2007
- 841
-
Preferable Improvements and Changes to FB-DiMM High-Speed Channel for 9.6Gbps OperationHiraishi, Atsushi / Sugano, Toshio / Kusamitsu, Hideki et al. | 2007
- 846
-
Xbox360 Front Side Bus - A 21.6 GB/s End-to-End Interface DesignSiljenberg, David / Baumgartner, Steve / Buchholtz, Tim / Maxson, Mark / Timpane, Trevor / Johnson, Jeff et al. | 2007
- 854
-
Design Consideration of 6.25 Gbps Signaling for High-Performance ServerJiang, Jian Hong / Gai, Weixin / Hattori, Akira / Hidaka, Yasuo / Horie, Takeshi / Koyanagi, Yoichi / Osone, Hideki et al. | 2007
- 858
-
System Co-Design and Co-Analysis Approach to Implementing the XDR Memory System of the Cell Broadband Engine Processor; Realizing 3.2 Gbps Data Rate per Memory Lane in Low Cost, High Volume ProductionYip, Wai-Yeung / Best, Scott / Beyene, Wendemagegnehu / Schmitt, Ralf et al. | 2007
- 884
-
Program Phase Directed Dynamic Cache Way Reconfiguration for Power EfficiencyBanerjee, Subhasis / G, Surendra / Nandy, S. K. et al. | 2007
- 896
-
Design Methodology for 2.4GHz Dual-Core MicroprocessorIto, Noriyuki / Komatsu, Hiroaki / Kanuma, Akira / Yoshitake, Akihiro / Tanamura, Yoshiyasu / Sugiyama, Hiroyuki / Yamashita, Ryoichi / Nabeya, Ken-ichi / Yoshino, Hironobu / Yamanaka, Hitoshi et al. | 2007
- 902
-
An Embedded Low Power/Cost 16-Bit Data/Instruction Microprocessor Compatible with ARM7 Software ToolsYang, Fu-Ching / Huang, Ing-Jer et al. | 2007
- 908
-
A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia ApplicationsLiu, Zhenyu / Arslan, Tughrul / Erdogan, Ahmet T. et al. | 2007
- 914
-
Exploration of Low Power Adders for a SIMD Data PathPaci, G. / Marchal, P. / Benini, L. et al. | 2007
- 926
-
Multithreaded SAT SolvingLewis, Matthew / Schubert, Tobias / Becker, Bernd et al. | 2007
- 938
-
Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and ResetsDisch, Stefan / Scholl, Christoph et al. | 2007
- 944
-
Fixing Design Errors with Counterexamples and ResynthesisChang, Kai-Hui / Markov, Igor L. / Bertacco, Valeria et al. | 2007
- 951
-
Author index| 2007
- C1
-
Covers| 2007
- ii
-
Copyright page| 2007
- iii
-
ASP-DAC 2007 General Chair's Message| 2007
- iv
-
Message from Technical Program Committee| 2007
- ix
-
How Foundry can Help Improve your Bottom-Line? Accuracy Matters!Hsu, Fu-Chieh et al. | 2007
- nil1
-
Call for Papers| 2007
- nil2
-
Call for Designs| 2007
- v
-
University LSI Design Contest| 2007
- vi
-
Designers' Forum| 2007
- vii
-
Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-ChainsRutenbar, Rob A. et al. | 2007
- viii
-
Meeting with the Forthcoming IC Design -- The Era of Power, Variability and NRE Explosion and a Bit of the Future --Sakurai, Takayasu et al. | 2007
- x
-
ASP-DAC 2007 Best Papers| 2007
- xii
-
ASP-DAC 2007 Organizing Committee| 2007
- xvi
-
ASP-DAC Steering Committee| 2007
- xx
-
ASP-DAC 2007 Technical Program Committee| 2007
- xxiii
-
University LSI Design Contest Committee| 2007
- xxiv
-
Industry Liaison| 2007
- xxv
-
List of Reviewers| 2007
- xxvii
-
Contents| 2007