3 gb/s AC coupled chip-to-chip communication using a low swing pulse receiver (English)
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In:
IEEE Journal of Solid-State Circuits
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41
, 1
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287-296
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2006
- Article (Journal) / Electronic Resource
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Title:3 gb/s AC coupled chip-to-chip communication using a low swing pulse receiver
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Contributors:Luo, L. ( author ) / Wilson, J.M. ( author ) / Mick, S.E. ( author ) / Jian Xu, ( author ) / Liang Zhang, ( author ) / Franzon, P.D. ( author )
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Published in:IEEE Journal of Solid-State Circuits ; 41, 1 ; 287-296
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Publisher:
- New search for: IEEE
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Publication date:2006-01-01
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Size:2889817 byte
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ISSN:
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DOI:
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Type of media:Article (Journal)
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Type of material:Electronic Resource
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Language:English
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Source:
Table of contents – Volume 41, Issue 1
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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Table of contents| 2006
- 3
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EDITORIAL - Introduction to the Special Issue on the 2005 IEEE International Solid-State Circuits ConferenceSpiegel, J.Van der et al. | 2006
- 3
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Introduction to the Special Issue on the 2005 IEEE International Solid-State Circuits ConferenceVanderSpiegel, J. / Krishnamurthy, R.K. / Natarajan, S. / Yang, C.-K. et al. | 2006
- 7
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Monolithic above-IC resonator technology for integrated architectures in mobile and wireless communicationDubois, M.-A. / Carpentier, J.-F. / Vincent, P. / Billard, C. / Parat, G. / Muller, C. / Ancey, P. / Conti, P. et al. | 2006
- 7
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TECHNOLOGY DIRECTIONS - Monolithic Above-IC Resonator Technology for Integrated Architectures in Mobile and Wireless CommunicationDubois, M.-A. et al. | 2006
- 17
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A 60-GHz CMOS receiver front-endRazavi, B. et al. | 2006
- 17
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TECHNOLOGY DIRECTIONS - A 60-GHz CMOS Receiver Front-EndRazavi, B. et al. | 2006
- 23
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A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a packageMiura, N. / Mizoguchi, D. / Inoue, M. / Sakurai, T. / Kuroda, T. et al. | 2006
- 23
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TECHNOLOGY DIRECTIONS - A 195-Gb-s 1.2-W Inductive Inter-Chip Wireless Superconnect With Transmit Power Control Scheme for 3-D-Stacked System in a PackageMiura, N. et al. | 2006
- 35
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A 950-MHz rectifier circuit for sensor network tags with 10-m distanceUmeda, T. / Yoshida, H. / Sekine, S. / Fujita, Y. / Suzuki, T. / Otaka, S. et al. | 2006
- 35
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TECHNOLOGY DIRECTIONS - A 950-MHz Rectifier Circuit for Sensor Network Tags With 10-m DistanceUmeda, T. et al. | 2006
- 42
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TECHNOLOGY DIRECTIONS - A VLSI Analog Computer-Digital Computer AcceleratorCowan, G.E.R. et al. | 2006
- 42
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A VLSI analog computer/digital computer acceleratorCowan, G.E.R. / Melville, R.C. / Tsividis, Y.P. et al. | 2006
- 54
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SIGNAL PROCESSING - A 63-mW H.264-MPEG-4 Audio-Visual Codec LSI With Module-Wise Dynamic Voltage-Frequency ScalingFujiyoshi, T. et al. | 2006
- 54
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A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scalingFujiyoshi, T. / Shiratake, S. / Nomura, S. / Nishikawa, T. / Kitasho, Y. / Arakida, H. / Okuda, Y. / Tsuboi, Y. / Hamada, M. / Hara, H. et al. | 2006
- 63
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The microarchitecture of the synergistic processor for a cell processorFlachs, B. / Asano, S. / Dhong, S.H. / Hofstee, H.P. / Gervais, G. / Roy Kim, / Le, T. / Peichun Liu, / Leenstra, J. / Liberty, J. et al. | 2006
- 63
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SIGNAL PROCESSING - The Microarchitecture of the Synergistic Processor for a CELL ProcessorFlachs, B. et al. | 2006
- 71
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SIGNAL PROCESSING - An SoC With 1.3 Gtexels-s 3-D Graphics Full Pipeline for Consumer ApplicationsKim, D. et al. | 2006
- 71
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An SoC with 1.3 gtexels/s 3-D graphics full pipeline for consumer applicationsDonghyun Kim, / Kyusik Chung, / Chang-Hyo Yu, / Chun-Ho Kim, / Inho Lee, / Bae, J. / Young-Jun Kim, / Jae-Hyeon Park, / Sungbeen Kim, / Yong-Ha Park, et al. | 2006
- 85
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SIGNAL PROCESSING - XiSystem: A XiRisc-Based SoC With Reconfigurable IO ModuleLodi, A. et al. | 2006
- 85
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XiSystem: a XiRisc-based SoC with reconfigurable IO moduleLodi, A. / Cappelli, A. / Bocchi, M. / Mucci, C. / Innocenti, M. / De Bartolomeis, C. / Ciccarelli, L. / Giansante, R. / Deledda, A. / Campi, F. et al. | 2006
- 97
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SIGNAL PROCESSING - A Reprogrammable EDGE Baseband and Multimedia Handset SoC With 6-Mbit Embedded DRAMCofler, A.M. et al. | 2006
- 97
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A reprogrammable EDGE baseband and multimedia handset SoC with 6-mbit embedded DRAMCofler, A.M. / Druilhe, F. / Dutoit, D. / Harrand, M. et al. | 2006
- 107
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Concordant memory design: an integrated statistical design approach for multi-gigabit DRAMAkiyama, S. / Sekiguchi, T. / Kajigaya, K. / Hanzawa, S. / Takemura, R. / Kawahara, T. et al. | 2006
- 107
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MEMORY - Concordant Memory Design: An Integrated Statistical Design Approach for Multi-Gigabit DRAMAkiyama, S. et al. | 2006
- 113
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MEMORY - A Read-Static-Noise-Margin-Free SRAM Cell for Low-VDD and High-Speed ApplicationsTakeda, K. et al. | 2006
- 113
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A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applicationsTakeda, K. / Hagihara, Y. / Aimoto, Y. / Nomura, M. / Nakazawa, Y. / Ishii, T. / Kobatake, H. et al. | 2006
- 122
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Enhanced write performance of a 64-mb phase-change random access memoryHyung-rok Oh, / Beak-hyung Cho, / Woo Yeong Cho, / Sangbeom Kang, / Byung-gil Choi, / Hye-jin Kim, / Ki-sung Kim, / Du-eung Kim, / Choong-keun Kwak, / Hyun-geun Byun, et al. | 2006
- 122
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MEMORY - Enhanced Write Performance of a 64-Mb Phase-Change Random Access MemoryOh, H. et al. | 2006
- 127
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A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitterKyu-hyoun Kim, / Young-Soo Sohn, / Chan-Kyoung Kim, / Moonsook Park, / Dong-Jin Lee, / Woo-Seop Kim, / Changhyun Kim, et al. | 2006
- 127
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MEMORY - A 20-Gb-s 256-Mb DRAM With an Inductorless Quadrature PLL and a Cascaded Pre-emphasis TransmitterKim, K. et al. | 2006
- 135
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Design of a 128-mb SOI DRAM using the floating body cell (FBC)Ohsawa, T. / Fujita, K. / Hatsuda, K. / Higashi, T. / Shino, T. / Minami, Y. / Nakajima, H. / Morikado, M. / Inoh, K. / Hamamoto, T. et al. | 2006
- 135
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MEMORY - Design of a 128-Mb SOI DRAM Using the Floating Body Cell (FBC)Ohsawa, T. et al. | 2006
- 146
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A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supplyKevin Zhang, / Bhattacharya, U. / Zhanping Chen, / Hamzaoglu, F. / Murray, D. / Vallepalli, N. / Yih Wang, / Bo Zheng, / Bohr, M. et al. | 2006
- 146
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MEMORY - A 3-GHz 70-Mb SRAM in 65-nm CMOS Technology With Integrated Column-Based Dynamic Power SupplyZhang, K. et al. | 2006
- 152
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A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC schemeSuzuki, T. / Yamagami, Y. / Hatanaka, I. / Shibayama, A. / Akamatsu, H. / Yamauchi, H. et al. | 2006
- 152
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MEMORY - A Sub-0.5-V Operating Embedded SRAM Featuring a Multi-Bit-Error-Immune Hidden-ECC SchemeSuzuki, T. et al. | 2006
- 161
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A 146-mm/sup 2/ 8-gb multi-level NAND flash memory with 70-nm CMOS technologyHara, T. / Fukuda, K. / Kanazawa, K. / Shibata, N. / Hosono, K. / Maejima, H. / Nakagawa, M. / Abe, T. / Kojima, M. / Fujiu, M. et al. | 2006
- 161
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MEMORY - A 146-mm2 8-Gb Multi-Level NAND Flash Memory With 70-nm CMOS TechnologyHara, T. et al. | 2006
- 161
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A 146-mm^2 8-Gb Multi-Level NAND Flash Memory With 70-nm CMOS TechnologyHara, T. / Fukuda, K. / Kanazawa, K. / Shibata, N. / Hosono, K. / Maejima, H. / Nakagawa, M. / Abe, T. / Kojima, M. / Fujiu, M. et al. | 2006
- 170
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PVT-aware leakage reduction for on-die caches with improved read stabilityKim, C.H. / Jae-Joon Kim, / Ik-Joon Chang, / Roy, K. et al. | 2006
- 170
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MEMORY - PVT-Aware Leakage Reduction for On-Die Caches With Improved Read StabilityKim, C.H. et al. | 2006
- 178
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DIGITAL - Overview of the Architecture, Circuit Design, and Physical Implementation of a First-Generation Cell ProcessorPham, D.C. et al. | 2006
- 179
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Overview of the architecture, circuit design, and physical implementation of a first-generation cell processorPham, D.C. / Aipperspach, T. / Boerstler, D. / Bolliger, M. / Chaudhry, R. / Cox, D. / Harvey, P. / Harvey, P.M. / Hofstee, H.P. / Johns, C. et al. | 2006
- 197
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The implementation of a 2-core, multi-threaded itanium family processorNaffziger, S. / Stackhouse, B. / Grutkowski, T. / Josephson, D. / Desai, J. / Alon, E. / Horowitz, M. et al. | 2006
- 197
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DIGITAL - The Implementation of a 2-Core, Multi-Threaded Itanium Family ProcessorNaffziger, S. et al. | 2006
- 210
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DIGITAL - Implementation of a Fourth-Generation 1.8-GHz Dual-Core SPARC V9 MicroprocessorHart, J.M. et al. | 2006
- 210
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Implementation of a fourth-generation 1.8-GHz dual-core SPARC V9 microprocessorHart, J.M. / Lee, K.T. / Chen, D. / Lik Cheng, / Chou, C. / Anand Dixit, / Greenley, D. / Gruber, G. / Ho, K. / Hsu, J. et al. | 2006
- 218
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A 90-nm variable frequency clock system for a power-managed itanium architecture processorFischer, T. / Desai, J. / Doyle, B. / Naffziger, S. / Patella, B. et al. | 2006
- 218
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DIGITAL - A 90-nm Variable Frequency Clock System for a Power-Managed Itanium Architecture ProcessorFischer, T. et al. | 2006
- 229
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Power and temperature control on a 90-nm Itanium family processorMcGowen, R. / Poirier, C.A. / Bostak, C. / Ignowski, J. / Millican, M. / Parks, W.H. / Naffziger, S. et al. | 2006
- 229
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DIGITAL - Power and Temperature Control on a 90-nm Itanium Family ProcessorMcGowen, R. et al. | 2006
- 238
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Ultra-dynamic Voltage scaling (UDVS) using sub-threshold operation and local Voltage ditheringCalhoun, B.H. / Chandrakasan, A.P. et al. | 2006
- 238
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DIGITAL - Ultra-Dynamic Voltage Scaling (UDVS) Using Sub-Threshold Operation and Local Voltage DitheringCalhoun, B.H. et al. | 2006
- 246
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The Parity protected, multithreaded register files on the 90-nm itanium microprocessorFetzer, E.S. / Dahle, D. / Little, C. / Safford, K. et al. | 2006
- 246
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DIGITAL - The Parity Protected, Multithreaded Register Files on the 90-nm Itanium MicroprocessorFetzer, E.S. et al. | 2006
- 256
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DIGITAL - A 110 GOPS-W 16-bit Multiplier and Reconfigurable PLA Loop in 90-nm CMOSHsu, S.K. et al. | 2006
- 256
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A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOSHsu, S.K. / Mathew, S.K. / Anders, M.A. / Zeydel, B.R. / Oklobdzija, V.G. / Krishnamurthy, R.K. / Borkar, S.Y. et al. | 2006
- 265
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DIGITAL - A Sub-10-ps Multiphase Sampling System Using RedundancyLee, L. et al. | 2006
- 265
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A sub-10-ps multiphase sampling system using redundancyLi-min Lee, / Weinlader, D. / Yang, C.-K.K. et al. | 2006
- 274
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DIGITAL - Chip-Package Hybrid Clock Distribution Network and DLL for Low Jitter Clock DeliveryChung, D. et al. | 2006
- 274
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Chip-package hybrid clock distribution network and DLL for low jitter clock deliveryDaehyun Chung, / Chunghyun Ryu, / Hyungsoo Kim, / Choonheung Lee, / Jinhan Kim, / Kicheol Bae, / Jiheon Yu, / Hoijun Yoo, / Joungho Kim, et al. | 2006
- 287
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3 gb/s AC coupled chip-to-chip communication using a low swing pulse receiverLuo, L. / Wilson, J.M. / Mick, S.E. / Jian Xu, / Liang Zhang, / Franzon, P.D. et al. | 2006
- 287
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DIGITAL - 3 Gb-s AC Coupled Chip-to-Chip Communication Using a Low Swing Pulse ReceiverLuo, L. et al. | 2006
- 297
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A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnectsSchinkel, D. / Mensink, E. / Klumperink, E.A.M. / van Tuijl, E. / Nauta, B. et al. | 2006
- 297
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DIGITAL - A 3-Gb-s-ch Transceiver for 10-mm Uninterrupted RC-Limited Global On-Chip InterconnectsSchinkel, D. et al. | 2006
- 307
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International symposium on low power electronics and design-ISLPED'06| 2006
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2006 Bipolar/BiCMOS Circuits and Technology Meeting| 2006
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[Front cover]| 2006
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IEEE Journal of Solid-State Circuits publication information| 2006
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IEEE Journal of Solid-State Circuits information for authors| 2006