A 3.3 V operation nonvolatile memory cell technology (English)
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In:
1992 Symposium on VLSI Technology Digest of Technical Papers
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40-41
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1992
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ISBN:
- Conference paper / Electronic Resource
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Title:A 3.3 V operation nonvolatile memory cell technology
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Contributors:Yoshikawa, K. ( author ) / Sakagami, E. ( author ) / Mori, S. ( author ) / Arai, N. ( author ) / Narita, K. ( author ) / Yamaguchi, Y. ( author ) / Ohshima, Y. ( author ) / Naruke, K. ( author )
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Published in:
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Publisher:
- New search for: IEEE
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Publication date:1992-01-01
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Size:238204 byte
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ISBN:
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DOI:
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Type of media:Conference paper
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Type of material:Electronic Resource
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Language:English
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 0_1
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1992 Symposium on VLSI Technology. Digest of Technical Papers [Front Cover]| 1992
- 2
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Trends in single-wafer processingDoering, R.R. et al. | 1992
- 6
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Technology trend of flash-EEPROM-Can flash-EEPROM overcome DRAM?Masuoka, F. et al. | 1992
- 10
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A 0.72 mu m/sup 2/ recessed STC (RSTC) technology for 256 Mbit DRAMs using quarter-micron phase-shift lithographySagara, K. / Kure, T. / Shukuri, S. / Yugami, J. / Hasegawa, N. / Shinriki, H. / Goto, H. / Yamashita, H. / Takeda, E. et al. | 1992
- 12
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Micro villus patterning (MVP) technology for 256 Mb DRAM stack cellAhn, J.H. / Park, Y.W. / Shin, J.H. / Kim, S.T. / Shim, S.P. / Nam, S.W. / Park, W.M. / Shin, H.B. / Choi, C.S. / Kim, K.T. et al. | 1992
- 14
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A buried-plate trench cell for a 64-Mb DRAMParries, P. / Pan, P. / Tonti, W. / Cote, W. / Dash, S. / Lorenz, P. / Arden, W. / Mohler, R. / Roehl, S. / Bryant, A. et al. | 1992
- 16
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A native-oxide-free process for 4 nm capacitor dielectricsNakano, M. / Shinmura, N. / Iguchi, K. / Watanabe, T. / Sakiyama, K. et al. | 1992
- 18
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Ultra-thin silicon dioxide leakage current and scaling limitSchuegraf, K.F. / King, C.C. / Hu, C. et al. | 1992
- 20
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Conductive channel in ONO formed by controlled dielectric breakdownChiang, S. / Wang, R. / Speers, T. / McCollum, J. / Hamdy, E. / Hu, C. et al. | 1992
- 22
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A new modified HF-last cleaning process for high-performance gate dielectricsVerhaverbeke, S. / Meuris, M. / Schaekers, M. / Haspeslagh, L. / Mertens, P. / Heyns, M.M. / Philipossian, A. et al. | 1992
- 24
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Wafer quality specification for future sub-half-micron ULSI devicesOhmi, T. / Takano, J. / Tsuga, T. / Kogure, M. / Aoyama, S. / Matsumoto, K. / Makihara, K. et al. | 1992
- 26
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Deep subhalf-micron BiCMOS technology using synchrotron X-ray lithography and its application to 58 ps 2 V CMOS gate arrayKyuragi, H. / Konaka, S. / Kobayashi, T. / Deguchi, K. / Yamamoto, E. / Ohki, S. / Yamamoto, Y. et al. | 1992
- 28
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A high performance BiCMOS technology using 0.25 mu m CMOS and double poly 47 GHz bipolarDavari, B. / Wu, B. / Taur, Y. / Wong, C. / Chen, C.L. / Rodriguez, M. / Tang, D.D. / Jenkins, K. / McFarland, P.A. / Klaus, D. et al. | 1992
- 30
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An ultra high speed ECL-bipolar CMOS technology with silicon fillet self-aligned contactsLiu, T.M. / Chin, G.M. / Morris, M.D. / Jeon, D.Y. / Archer, V.D. / Kim, H.H. / Cerullo, M. / Lee, K.F. / Sung, J.M. / Lau, K. et al. | 1992
- 32
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High performance BiCMOS technology design for sub-10 ns 4 Mbit BiCMOS SRAM with 3.3 V operationMaeda, T. / Inoue, K. / Ishimaru, K. / Suzuki, A. / Kato, H. / Kakumu, M. et al. | 1992
- 34
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A high performance 0.6 mu m BiCMOS SRAM technology with emitter-base self-aligned bipolar transistors and retrograde well for MOS transistorsHonda, H. / Uga, K. / Ishida, M. / Ishigaki, Y. / Takahashi, J. / Shiomi, T. / Ohbayashi, S. / Kohno, Y. et al. | 1992
- 36
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A high performance polysilicon TFT using RTA and plasma hydrogenation applicable to highly stable SRAMs of 16 Mbit and beyondHayashi, F. / Kitakata, M. et al. | 1992
- 38
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An asymmetric memory cell using a C-TFT for ULSI SRAMsKuriyama, H. / Okada, T. / Ashida, M. / Sakamoto, O. / Yuzuriha, K. / Tsutsumi, K. / Nishimura, T. / Anami, K. / Kohno, Y. / Miyoshi, H. et al. | 1992
- 40
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A 3.3 V operation nonvolatile memory cell technologyYoshikawa, K. / Sakagami, E. / Mori, S. / Arai, N. / Narita, K. / Yamaguchi, Y. / Ohshima, Y. / Naruke, K. et al. | 1992
- 42
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BiFAMOS technology for high speed mega-bit EPROMsHu, G.J. / Tran, L.C. / Keshtbod, P. / Segal, J. / Park, K.H. / Amin, T. / Prickett, B. / Tsao, S.C. / Yen, J. / Smith, E. et al. | 1992
- 44
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A novel cell structure for giga-bit EPROMs and flash memories using polysilicon thin film transistorsKoyama, S. et al. | 1992
- 46
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High-rate-gas-flow microwave plasma etching of siliconTsujimoto, K. / Kumihashi, T. / Kohuji, N. / Tachi, S. et al. | 1992
- 48
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Highly anisotropic microwave plasma etching for high packing density silicon patternsKure, T. / Gotoh, Y. / Kawakami, H. / Tachi, S. et al. | 1992
- 50
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Sensor fusion for ULSI manufacturing process controlMoslehi, M.M. / Velo, L. / Najm, H. / Breedijk, T. / Dostalik, B. et al. | 1992
- 52
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Rapid thermal multiprocessing using multivariable control of circularly symmetric 3 zone lampApte, P.P. / Saraswat, K.C. et al. | 1992
- 54
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FRACS (fully radiative current path structure)-A high speed bipolar transistor with sub-0.1 mu m emitterOnai, T. / Nakazato, K. / Kiyota, Y. / Nakamura, T. et al. | 1992
- 56
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Perimeter effects in small geometry bipolar transistorsLee, W. / Sun, J.Y.-C. / Warnock, J. / Jenkins, K.A. et al. | 1992
- 58
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Single-poly bipolar transistor with selective epitaxial silicon and chemo-mechanical polishingNguyen, C.T. / Kuehne, S.C. / Wong, S.S. et al. | 1992
- 60
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A Si bipolar transistor with f/sub max/ of 40 GHz and its application to a 35 GHz 1/16 dynamic frequency dividerTakemura, H. / Ogawa, C. / Kurisu, M. / Uemura, G. / Tashiro, T. et al. | 1992
- 62
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A novel selective SiGe epitaxial growth technology for self-aligned HBTsSato, F. / Hashimoto, T. / Tashiro, T. / Tatsumi, T. / Hiroi, M. / Niino, T. et al. | 1992
- 64
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A 35-GHz 20- mu m/sup 2/ self-aligned PNP technology for ultra-high-speed high-density complementary bipolar ULSIsWashio, K. / Shimamoto, H. / Nakamura, T. et al. | 1992
- 66
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A new salicide process (PASET) for sub-half micron CMOSSakai, I. / Abiko, H. / Kawaguchi, H. / Hirayama, T. / Johansson, L.E.G. / Okabe, K. et al. | 1992
- 68
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0.1 mu m contact metallization with SiH/sub 2/F/sub 2/-reduced CVD WYokoyama, N. / Yoshimura, T. / Goto, H. / Kobayashi, N. / Homma, Y. / Takeda, E. et al. | 1992
- 70
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A novel selective Ni/sub 3/Si contact plug technique for deep-submicron ULSIsIijima, T. / Nishiyama, A. / Ushiku, Y. / Kunishima, I. / Suguro, K. / Iwai, H. et al. | 1992
- 72
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A high performance Si on Si multichip module technologyRucker, T.G. / Mencinger, N. / Murali, V. / Regis, K. / Shukla, R. / Sundahl, R. / Siu, B. et al. | 1992
- 74
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A highly reliable sub-half-micron via and interconnect technology using Al alloy high-temperature sputter fillingNishimura, H. / Yamada, T. / Sinclair, R. / Ogawa, S. et al. | 1992
- 76
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Influence of stress-induced void formation on electromigration endurance in quarter-micron aluminum interconnectsMatsunaga, N. / Shibata, H. / Hashimoto, K. et al. | 1992
- 78
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Parameterized SPICE subcircuits for submicron multilevel interconnect modelingChang, K.-J. / Oh, S.-Y. / Chang, N.H. / Lee, K. et al. | 1992
- 84
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A self-learning neural-network LSI using neuron MOSFETsShibata, T. / Ohmi, T. et al. | 1992
- 86
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High performance 0.1- mu m room temperature Si MOSFETsYan, R.H. / Lee, K.F. / Jeon, D.Y. / Kim, Y.O. / Park, B.G. / Pinto, M.R. / Rafferty, C.S. / Tennant, D.M. / Westerwick, E.H. / Chin, G.M. et al. | 1992
- 88
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A high performance asymmetric LDD MOSFET using selective oxide deposition techniqueHoriuchi, T. / Homma, T. / Murao, Y. / Okumura, K. et al. | 1992
- 90
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High drivability and high reliability MOSFETs with non-doped poly-Si spacer LDD structure (SLDD)Shimizu, A. / Ohki, N. / Ishida, H. / Yamanaka, T. / Hashimoto, N. / Hashimoto, T. / Takeda, E. et al. | 1992
- 92
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Design considerations for sub-0.35 mu m buried channel P-MOSFET devicesMazure, A. / Subrahmanyan, R. / Gunderson, C. / Orlowski, M. et al. | 1992
- 94
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Enhanced hot-carrier degradation due to water in TEOS/O/sub 3/-oxide and water blocking effect of ECR-SiO/sub 2/Shimoyama, N. / Machida, K. / Murase, K. / Tsuchiya, T. et al. | 1992
- 96
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Suppression of the MOS transistor hot carrier degradation caused by water desorbed from intermetal dielectricShimokawa, K. / Usami, T. / Tokitou, S. / Hirashita, N. / Yoshimaru, M. / Ino, M. et al. | 1992
- 98
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AC hot-carrier effect under mechanical stress (MOSFET)Hamada, A. / Takeda, E. et al. | 1992
- 100
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Wafer-mapping of hot carrier lifetime due to physical stress effects (MOSFET)MacWilliams, K.P. / Lowry, L.E. / Swanson, D.J. / Scarpulla, J. et al. | 1992
- 102
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An epitaxial emitter cap, SiGe-base bipolar technology with 22 ps ECL gate delay at liquid nitrogen temperatureCressler, J.D. / Crabbe, E.F. / Sun, J.Y.-C. / Stork, J.M.C. et al. | 1992
- 104
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A new CMOS structure for low temperature operation with forward substrate biasYamamoto, T. / Mogami, T. / Terada, K. et al. | 1992
- 106
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A high performance low temperature 0.3 mu m CMOS on SIMOXShahidi, G.G. / Davari, B. / Zicherman, D. / McFarland, P. / Fink, A. / Brodsky, S. / Pettrilo, K. / Lombardi, R. / Rodriguez, M. / Polcari, M. et al. | 1992
- 108
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Photolithographic system using modified illuminationKamon, K. / Miyamoto, T. / Myoi, Y. / Fujinaga, M. / Nagata, H. / Tanaka, M. et al. | 1992
- 110
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Quarter micron KrF excimer laser lithographyEndo, M. / Tani, Y. / Koizumi, T. / Kobayashi, S. / Yamashita, K. / Sasago, M. / Nomura, N. et al. | 1992
- 112
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Application of blind method to phase-shifting lithographyJinbo, H. / Yamashita, Y. et al. | 1992
- 114
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Repair technique for phase shifting masks using silicon-containing resistWatanabe, H. / Imoriya, T. / Todokoro, Y. / Inoue, M. et al. | 1992
- 116
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Lithography for 0.25 mu m and below using simple high-performance opticsPease, R.F.W. / Owen, G. / Hsieh, R.L. / Grenville, A. / von Bunau, R. / Maluf, N.I. et al. | 1992