Efficient random vector verification method for an embedded 32-bit RISC core (English)
- New search for: Chang-Ho Lee,
- New search for: Hoon-Mo Yang,
- New search for: Sung-Ho Kwak,
- New search for: Moon-Key Lee,
- New search for: Sanghyun Park,
- New search for: Sangyeun Cho,
- New search for: Sangwoo Kim,
- New search for: Yongchun Kim,
- New search for: Seh-Woong Jeong,
- New search for: Bong-Young Chung,
- New search for: Hyung-Lae Roh,
- New search for: Chang-Ho Lee,
- New search for: Hoon-Mo Yang,
- New search for: Sung-Ho Kwak,
- New search for: Moon-Key Lee,
- New search for: Sanghyun Park,
- New search for: Sangyeun Cho,
- New search for: Sangwoo Kim,
- New search for: Yongchun Kim,
- New search for: Seh-Woong Jeong,
- New search for: Bong-Young Chung,
- New search for: Hyung-Lae Roh,
In:
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)
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291-294
;
2000
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ISBN:
- Conference paper / Electronic Resource
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Title:Efficient random vector verification method for an embedded 32-bit RISC core
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Contributors:Chang-Ho Lee, ( author ) / Hoon-Mo Yang, ( author ) / Sung-Ho Kwak, ( author ) / Moon-Key Lee, ( author ) / Sanghyun Park, ( author ) / Sangyeun Cho, ( author ) / Sangwoo Kim, ( author ) / Yongchun Kim, ( author ) / Seh-Woong Jeong, ( author ) / Bong-Young Chung, ( author )
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Published in:
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Publisher:
- New search for: IEEE
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Publication date:2000-01-01
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Size:466612 byte
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ISBN:
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DOI:
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Type of media:Conference paper
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Type of material:Electronic Resource
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Language:English
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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A 200 MHz/90 dB gain range CMOS VGASong, W.C. / Oh, C.J. / Cho, G.H. / Jung, H.B. et al. | 2000
- 5
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A 0.35-/spl mu/m CMOS low noise VGAKyuyoung Chung, / Gunhee Han, / Sungho Kang, et al. | 2000
- 5
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A 0.35-mum CMOS Low Noise VGAChung, K. / Han, G. / Kang, S. / IEEE / Yonsei University et al. | 2000
- 9
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Design of log domain low-pass filters by MOSFET square lawGwo-Jeng Yu, / Bin-Da Liu, / Yuan Chia Hsu, / Chun-Yueh Huang, et al. | 2000
- 13
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A low-ripple switched-capacitor DC-DC up converter for low-voltage applicationsSeung-Chul Lee, / Dong-Soo Park, / Jung-Hee Song, / Myung-Whan Choi, / Seung-Hoon Lee, et al. | 2000
- 17
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New plus- and minus-voltage generators for TFT-LCD panelsHirata, M. / Suzuki, Y. / Yoshida, M. / Arayashiki, Y. / Sumiyoshi, N. / Thanachayanont, A. et al. | 2000
- 21
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A dynamic logic circuit embedded flip-flop for ASIC designHirairi, K. / Kosaka, H. / Moriki, K. / Keino, K. / Onuma, K. et al. | 2000
- 25
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New 4-transistor XOR and XNOR designsHung Tien Bui, / Al-Sheraidah, A.K. / Yuke Wang, et al. | 2000
- 29
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CSPL: a capacitor-separated pass-transistor logicYamashita, T. / Asada, K. et al. | 2000
- 33
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CMOS capacitor coupling logic (C/sup 3/L) circuitsHong-Yi Huang, / Teng-Neng Wang, et al. | 2000
- 33
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CMOS Capacitor Coupling Logic (C3L) CircuitsHuang, H.-Y. / Wang, T.-N. / IEEE / Yonsei University et al. | 2000
- 37
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The non-full voltage swing TSPC (NSTSPC) logic designKuo-Hsing Cheng, / Yung-Chong Huang, et al. | 2000
- 41
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Bi-directional current-mode multiple input maximum circuitGwo-Jeng Yu, / Bin-Da Liu, / Chun-Yueh Huang, et al. | 2000
- 45
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Design of 3.3 V 10 bit current-mode folding/interpolating CMOS A/D converter with an arithmetic functionalityJin Won Chung, / Kwang Sub Yoon, et al. | 2000
- 49
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Design of a geometric-mean generator based on switched-current techniqueSungwook Yoon, / Deukyoung Kim, / Hyunjeong Kim, / Woong Jung, / Minkyu Song, et al. | 2000
- 53
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8-mW, 1-V, 100-Msps, 6-bit A/D converter using a transconductance latched comparatorTerada, J. / Matsuya, Y. / Morisawa, F. / Kado, Y. et al. | 2000
- 57
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A 10-bit, 40Msamples/s Cascading Folding & Interpolating A/D Converter with Wide Range Error CorrectionKim, T.-h. / Sung, J.-j. / Kim, S.-h. / Joo, W. / You, S.-b. / Kim, S. / IEEE / Yonsei University et al. | 2000
- 57
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A 10-bit, 40 Msamples/s cascading folding and interpolating A/D converter with wide range error correctionTae-Hyoung Kim, / Jun-Jey Sung, / Soo-Hwan Kim, / Woong Joo, / Seung-Bin You, / Suki Kim, et al. | 2000
- 61
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A differential type CMOS phase frequency detectorChang, R.C. / Lung-Chih Kuo, et al. | 2000
- 65
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Adaptive AC/DC output buffer with reduced ground bounce and output ringingShyh-Jye Jou, / Shu-Hua Kuo, / Jui-Ta Chiu, / Lin, V. et al. | 2000
- 69
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Novel output buffer design for Universal Serial Bus applicationsHwang-Cherng Chow, / Chen-Yi Huang, et al. | 2000
- 73
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A Carry-Free 54B x 54B Multiplier using Equivalent Bit Conversion AlgorithmKim, Y. / Song, B.-S. / Grosspietsch, J. / Gillig, S. / IEEE / Yonsei University et al. | 2000
- 73
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A carry-free 54 b/spl times/54 b multiplier using equivalent bit conversion algorithmYun Kim, / Bang-Sup Song, / Grosspietsch, J. / Gillig, S. et al. | 2000
- 77
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A self-timed wave pipelined adder using data align methodByoung-Hoon Lim, / Jin-Ku Kang, et al. | 2000
- 81
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A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matchingChan-Hong Park, / Jin Wook Kim, / Beomsup Kim, et al. | 2000
- 85
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A CMOS Voltage-Controlled Oscillator With Temperature CompensatedLin, Z.-M. / Huang, K.-C. / Chen, J.-D. / Liao, M.-Y. / IEEE / Yonsei University et al. | 2000
- 85
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A CMOS voltage-controlled oscillator with temperature compensationZhi-Ming Lin, / Kuei-Chen Huang, / Jun-Da Chen, / Mei-Yuan Liao, et al. | 2000
- 87
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Design of high speed CMOS prescalerMyung-Woon Hwang, / Jong-Tae Hwang, / Gyu-Hyeong Cho, et al. | 2000
- 91
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A 2 V clock synchronizer using digital delay-locked loopChorng-Sii Hwang, / Wang-Chih Chung, / Chih-Yong Wang, / Hen-Wai Tsao, / Shen-Iuan Liu, et al. | 2000
- 95
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A 16.3-GHz 64:1 CMOS frequency dividerNogawa, M. / Ohtomo, Y. et al. | 2000
- 99
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A low-power 1.2 GHz 0.35 /spl mu/m CMOS PLLDar-Chang Juang, / De-Sheng Chen, / Jyou-Min Shyu, / Ching-Yuang Wu, et al. | 2000
- 99
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A Low-Power 1.2GHz 0.35mum CMOS PLLJuang, D.-C. / Chen, D.-S. / Shyu, J.-M. / Wu, C.-Y. / IEEE / Yonsei University et al. | 2000
- 103
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A low-complexity frame memory compression algorithm and its implementation for MPEG-2 video decoderTae Young Lee, / Yong Sik Kim, / Sungjae Jang, / Hoon Yoo, / Jechang Jeong, et al. | 2000
- 107
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A programmable sensor signal conditioning LSIMurabayashi, F. / Matsumoto, M. / Hanzawa, K. / Yamauchi, T. / Sakurai, K. / Yamada, H. / Shimada, S. / Miyazaki, A. et al. | 2000
- 111
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A novel rotational VLSI architecture based on extended elementary angle set CORDIC algorithmCheng-Shing Wu, / An-Yeu Wu, et al. | 2000
- 115
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A 1-V low power rail-to-rail analog CMOS multi-function filter with configurable capabilityYu-Cherng Hung, / Bin-Da Liu, et al. | 2000
- 119
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A novel FPGA design of a wireless block transmission channel equalizerYin-Tsung Hwang, / Jih-Cheng Han, et al. | 2000
- 119
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A Novel FPGA Design of a Wireless Block Transmission Chanel EqualizerHwang, Y.-T. / Han, J.-C. / IEEE / Yonsei University et al. | 2000
- 123
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A new VLSI design for adaptive frequency-detection based on the active oscillatorMing-Hwa Sheu, / Ho-En Liao, / Shr-Shian Yang, et al. | 2000
- 127
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A hybrid-level multi-phase charge-recycler with reduced number of external capacitors for low-power LCD column driversKwangho Yoon, et al. | 2000
- 131
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A design of contrast controller for image improvement of multi-gray scale imageHwa-Hyun Cho, / Chul-Ho Choi, / Byong-Heon Kwon, / Myung-Ryul Choi, et al. | 2000
- 135
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A smart image sensor with novel implementation of quad-tree scanNezuka, T. / Akita, J. / Ikeda, M. / Asada, K. et al. | 2000
- 139
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Optimized VLSI design for enhanced image downscalerHonam Lee, / Bonggeun Lee, / Youngho Lee, / Bongsoon Kang, et al. | 2000
- 143
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VLSI processor of parallel genetic algorithmYun-Ho Choi, / Duck jin Chung, et al. | 2000
- 147
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Analysis and implementation of interface for heterogeneous systemHwi-Sung Jung, / Moon-Key Lee, et al. | 2000
- 151
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Static-based verification of memory BIST integrationKab Joo Lee, / Seunghan Kim, / Shihyeon Park, / Youngsoo Yoo, et al. | 2000
- 155
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A 2-V CMOS 455 kHz FM/FSK demodulator using feedforward offset cancellation limiting amplifierPo-Chiun Huang, / Yi-Huei Chen, / Chien-Chih Liu, / Chorng-Kuang Wang, et al. | 2000
- 159
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3R one chip CMOS IC at 156 Mbit/sYamazaki, D. / Ide, S. / Chiba, T. / Hayakawa, A. / Rokugawa, H. / Kawai, M. et al. | 2000
- 163
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A /spl Sigma/-/spl Delta/ modulator architecture reducing intermodulation of tones near f/sub s//2 into the basebandChoi, Y.K. / Ihm, J.Y. et al. | 2000
- 163
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A Sigma-Delta Modulator Architecture Reducing Intermodulation of Tones near fs/2 into the BasebandChoi, Y. K. / Ihm, J. Y. / IEEE / Yonsei University et al. | 2000
- 167
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High-frequency intermodulation analysis of cascode amplifierJin-Su Ko, / Hyun-Seok Kim, / Bonkee Kim, / Byeong-Ha Park, et al. | 2000
- 171
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Integrated mixer designWatanabe, G. / Lau, H. / Schoepf, J. et al. | 2000
- 175
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Efficient 8-cycle DES implementationYoung Won Lim, et al. | 2000
- 179
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VLSI implementation of an OFB processor for encryption of real-time dataYoung-Chul Kim, / Kwang-Ok Kim, / Tae-Won Lee, et al. | 2000
- 183
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Hardware implementation of 128-bit symmetric cipher SEEDYoung-Ho Seo, / Jong-Hyeon Kim, / Dong-Wook Kim, et al. | 2000
- 187
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Implementation Of 1024-Bit Modular Processor for RSA CryptosystemKim, Y. S. / Kang, W. S. / Choi, J. R. / IEEE / Yonsei University et al. | 2000
- 187
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Asynchronous implementation of 1024-bit modular processor for RSA cryptosystemYoung Sae Kim, / Woo Seok Kang, / Jun Rim Choi, et al. | 2000
- 191
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Asynchronous implementation of modular exponentiation for RSA cryptographyMing-Der Shieh, / Chien-Hsing Wu, / Ming-Hwa Sheu, / Jia-Lin Sheu, / Che-Han Wu, et al. | 2000
- 195
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Design of an equalizer using the DFE structure and the MMA algorithmDae Kyo Shin, / Seung Joong Hwang, / Byoung Gak Jo, / Sunwoo, M.H. et al. | 2000
- 199
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A 1.0 Gbps clock and data recovery circuit with two-XOR phase-frequency detectorDong-Hee Kim, / Jin-Ku Kang, et al. | 2000
- 203
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A 3 V 10 b 100 MS/s digital-to-analog converter for cable modem applicationsSeung-Chul Lee, / Jin Park, / Jin-Sik Yoon, / Jung-Hee Song, / Seung-Hoon Lee, et al. | 2000
- 207
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A QPSK/16 QAM receiver chip for LMDS applicationKi Hyuk Park, / Dae Kyo Shin, / Jun Sung Lee, / Sunwoo, M.H. et al. | 2000
- 211
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A new CMOS double-upconverter with half-LO for DTV tunerWoo, S.H. / Lee, K. / Cho, G.H. et al. | 2000
- 215
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An interpolation algorithm by using the adaptive pseudomedian filterHee-Chul Kim, / Jong-Suk Chae, / Hwa-Hyun Cho, / Byong-Heon Kwon, / Myung-Ryul Choi, et al. | 2000
- 215
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An Interpolation Algorithm By Using The Adative Pseudomedian FilterKim, H.-S. / Chae, J.-S. / Cho, H.-H. / Kwon, B.-H. / Choi, M.-R. / IEEE / Yonsei University et al. | 2000
- 219
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The design of the perspective texture mapping for 3D computer graphics in rasterizer merged frame buffer technologySeung-Gi Lee, / Woo-Chan Park, / Won-Jong Lee, / Woo-Nam Jung, / Tack-Don Han, et al. | 2000
- 223
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Efficient simultaneous rounding method removing sticky-bit from critical path for floating point additionWoo-Chan Park, / Tack-Don Han, / Shin-Dug Kim, et al. | 2000
- 227
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Interface synthesis for IP based designBong-Il Park, / In-Cheol Park, / Chong-Min Kyung, et al. | 2000
- 231
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An efficient system to develop various soft IPsJong-Hong Bae, / Seong-Jun Kyung, / Mun-Won Ahn, / Seong-Sik Kim, / Ji-Soo Lim, / Wook-Jin Cha, / Jong-Oh Lee, / Ho-Kyeong Kwon, / Se-Jin Yoo, / Dong-Soo Cho, et al. | 2000
- 235
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A dual-band receiver architecture for PCS and IMT-2000Sang-Gug Lee, / Nam-Soo Kim, / Seung-Min Oh, / Jeong-Ki Choi, / Sin-Churl Kim, et al. | 2000
- 239
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A 2 GHz LC-oscillator with automatic swing control for IMT-2000 applicationRyoo, J.Y. / Cho, G.H. et al. | 2000
- 243
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Cost-effective low-power architecture of vestigial sideband W-CDMA systemSungwoo Kwon, / Jaeyoung Kwak, / Dongwook Roh, / Dongku Kim, / Moonkey Lee, et al. | 2000
- 247
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1:N interpolation FIR filter design for SSB/BPSK-DS/CDMAMyung-Soon Kim, / Dae-Ik Kim, / Jin-Gyun Chung, / Myung-Sub Lim, et al. | 2000
- 251
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A novel architecture of rake receiver for fast acquisitionJungmin Ro, / Seongjoo Lee, / Jaeseok Kim, / Iksoo Eo, / Kyungsoo Kim, et al. | 2000
- 255
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AE32000: an embedded microprocessor coreOh, H.-C. / Kim, H.-G. / Jung, H.-S. / Lee, J.-W. / Kim, B.-J. / Jung, J.-Y. / Min, B.-G. / Lim, J.-Y. / Lee, H. / Kwon, K.-H. et al. | 2000
- 255
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AE32000: An Embedded Microprocessorcor coreOh, H.-C. / Kim, H.-G. / Jung, H.-S. / Lee, J.-W. / Kim, B.-J. / Jung, J.-Y. / Min, B.-G. / Lim, J.-Y. / Lee, H. / Kwon, K.-H. et al. | 2000
- 259
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Enhancement of wafer test/package yields by oxide-capping of microlens in CMOS image sensorOh, H.S. / Hong, H.J. / Lee, J.I. / Park, S.J. / Kwon, K.K. / Hwang, J. et al. | 2000
- 265
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Proven single pass design methodology for high reliable VDSMKeun-Ok Seo, / Sancho Park, et al. | 2000
- 267
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From RTL to GDSII SP&R Technology for new Millennium ASICsIEEE / Yonsei University et al. | 2000
- 269
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Linear search algorithm for repair analysis with 4 spare row/4 spare columnHyeokman Kwon, / Joohyeong Moon, / Jinsoo Byun, / Sangwook Park, / Jinyong Chung, et al. | 2000
- 273
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An efficient implementation of BIST for floating point DSP processorJaeheung Park, / Hoon Chang, / Ohyoung Song, et al. | 2000
- 277
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Test methodology for low power SRAM's (Is Iddq test useful for low power SRAM's?)Ilseok Suh, / Hong-Sik Kim, / Sungho Kang, / Gunhee Han, et al. | 2000
- 277
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Test Methodology for Low Power SRAM'sSuh, I. / Kim, H.-s. / Kang, S. / Han, G. / IEEE / Yonsei University et al. | 2000
- 281
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Testability Features of the MDSPChoi, W. / Song, O. / Chang, H. / IEEE / Yonsei University et al. | 2000
- 281
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Testability features of the MDSP [Multimedia Fixed Point Digital Signal Processor]Wonseok Choi, / Ohyoung Song, / Hoon Chang, et al. | 2000
- 285
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CalmRISC/sup TM/-32: a 32-bit low-power MCU coreSangyeun Cho, / Sanghyun Park, / Sangwoo Kim, / Yongchun Kim, / Seh-Woong Jeong, / Bong-Young Chung, / Hyung-Lae Roh, / Chang-Ho Lee, / Hun-Mo Yang, / Sung-Ho Kwak, et al. | 2000
- 285
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CalmRISC(TM)-32: A 32-BIT Low Power MCU CoreCho, S. / Park, S. / Kim, S. / Kim, Y. / Jeong, S.-W. / Chung, B.-Y. / Roh, H.-L. / Lee, C.-H. / Yang, H.-M. / Kwak, S.-H. et al. | 2000
- 291
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Efficient random vector verification method for an embedded 32-bit RISC coreChang-Ho Lee, / Hoon-Mo Yang, / Sung-Ho Kwak, / Moon-Key Lee, / Sanghyun Park, / Sangyeun Cho, / Sangwoo Kim, / Yongchun Kim, / Seh-Woong Jeong, / Bong-Young Chung, et al. | 2000
- 295
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Testability strategy and DFT methodology of CalmRISC32Hong-Sik Kim, / Il Seok Seo, / Sungho Kang, / Gunhee Han, et al. | 2000
- 299
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A dynamic TLB management structure to support different page sizesJung-Hoon Lee, / Jang-Soo Lee, / Shin-Dug Kim, et al. | 2000
- 303
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iSAVE: a behavioral emulator for in-system algorithm verificationSeungjong Lee, / Moo-Kyung Jung, / In-Cheol Park, / Chong-Min Kyung, et al. | 2000
- 307
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Transition count based BIST for detecting multiple stuck-open faults in CMOS circuitsRahaman, H. / Das, D.K. / Bhattacharya, B.B. et al. | 2000
- 311
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Exploration of multiple ICEs for embedded microprocessor cores in an SoC chipIng-Jer Huang, / Chung-Fu Kao, et al. | 2000
- 311
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Exploration Of Multiple ICE's For Embedded Microprocessor Cores in a SoC ChipHuang, I.-J. / Kao, C.-F. / IEEE / Yonsei University et al. | 2000
- 315
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Designing built-in self-test circuits for embedded memories testSanghun Park, / Kijong Lee, / Changbum Im, / Nami Kwak, / Kihyun Kim, / Youngdoo Choi, et al. | 2000
- 319
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Design-for-testability of the FLOVADaehan Youn, / Ohyoung Song, / Hoon Chang, et al. | 2000
- 323
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The cache memory system for CalmRISC32Kil-Whan Lee, / Jang-Soo Lee, / Gi-Ho Park, / Jung-Hoon Lee, / Tack-Don Han, / Shin-Dug Kim, / Yong-Chun Kim, / Seh-Woong Jung, / Kwang-Yup Lee, et al. | 2000
- 327
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The Design and Implementation of CalmRISC32 Floating Point UnitJeong, C.-H. / Park, W.-C. / Kim, S.-W. / Han, T.-D. / IEEE / Yonsei University et al. | 2000
- 327
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The design and implementation of CalmlRISC32 floating point unitCheol-Ho Jeong, / Woo-Chan Park, / Sang-Woo Kim, / Tack-Don Han, et al. | 2000
- 331
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A hardware reduced multiplier for low power designKwang Hyun Lee, / Chong Suck Rim, et al. | 2000
- 335
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An embedded 16-bit microprocessorYoung-Ho Cha, / Chang-Su Park, / Gyeong-Yeon Cho, / Hyek-Hwan Choi, et al. | 2000
- 339
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A cost-effective 16-bit embedded flash MCU for digital multimedia applicationsMin-Do Kwon, / Seok-Ho Seo, / Il-Ki Kim, et al. | 2000
- 343
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A novel analog mirror type DLL suitable for low voltage operation with self-calibration methodAkita, H. / Eto, S. / Isobe, K. / Tsuchida, K. / Toda, H. / Seki, T. et al. | 2000
- 345
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Interconnect strategy in deep-submicron DRAM technologyJae-Kyung Wee, / Si-Hong Kim, / Yong-Jae Park, / Se-Jun Kim, / Jin-Yong Chung, et al. | 2000
- 349
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A 333 MHz, 20 mW, 18 ps resolution digital DLL using current-controlled delay with parallel variable resistor DAC (PVR-DAC)Eto, S. / Akita, H. / Isobe, K. / Tsuchida, K. / Toda, H. / Seki, T. et al. | 2000
- 351
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Long retention time of embedded DRAM macro with thin gate oxide film transistorsFukuda, R. / Miyano, S. / Namekawa, T. / Haga, R. / Wada, O. / Takeda, S. / Numata, K. / Habu, M. / Koike, H. / Takato, H. et al. | 2000
- 355
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Low voltage protection circuit for FeRAM macroHee-Bok Kang, / Hun-Woo Kye, / Duck-Ju Kim, / Je-Hoon Park, / Soo-Nam Jang, / Ji-Hwan Ryu, / Jin-Yong Chung, et al. | 2000
- 359
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A Regularly Structured Parallel Multiplier With Non-Binary-Logic Counter Circuits With Non-Binary-Logic Counter CircuitsLin, R. / IEEE / Yonsei University et al. | 2000
- 359
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A regularly structured parallel multiplier with non-binary-logic counter circuitsRong Lin, et al. | 2000
- 363
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A 4-way VLIW embedded processor and its companion chipHirose, Y. / Saito, M. / Utsumi, H. / Saruwatari, T. / Suga, A. / Sukemura, T. / Takahashi, H. / Miyake, H. / Takebe, Y. / Kimura, M. et al. | 2000
- 367
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3D graphics system with VLIW processor for geometry accelerationYoung-Wook Jeon, / Young-Su Kwon, / Yeon-Ho Im, / Jun-Hee Lee, / Sang-Joon Nam, / Byung-Woon Kim, / Chong-Min Kyung, et al. | 2000
- 371
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Building a crosstalk library for relative window methods-timing analysis that includes crosstalk delay degradationSasaki, Y. / Yano, K. et al. | 2000
- 371
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Building a Crosstalk Library for Relative Window MethodsSasaki, Y. / Yano, K. / IEEE / Yonsei University et al. | 2000
- 375
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Design of a noise-free microcontrollerHyun-Kyu Jeon, / Sang-Yoon Lee, / Dae-Keun Han, et al. | 2000
- 379
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Author index| 2000
- I
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Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)| 2000