Leading edge 3D technology for high volume manufacturing (English)
- New search for: Arkalgud, Sitaram R.
- New search for: Arkalgud, Sitaram R.
In:
2009 Symposium on VLSI Technology
;
68-69
;
2006
-
ISBN:
- Conference paper / Electronic Resource
-
Title:Leading edge 3D technology for high volume manufacturing
-
Contributors:Arkalgud, Sitaram R. ( author )
-
Published in:
-
Publisher:
- New search for: IEEE
-
Publication date:2006-06-01
-
Size:1226456 byte
-
ISBN:
-
Type of media:Conference paper
-
Type of material:Electronic Resource
-
Language:English
-
Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
-
Copyright| 2006
- 2
-
The systematic turn in cognitive neuroscienceMogi, Ken et al. | 2006
- 8
-
Device technology innovation for exascale computingChen, Tze-chiang et al. | 2006
- 14
-
Comparative study between Si (110) and (100) substrates on mobility and velocity enhancements for short-channel highly-strained PFETsMayuzumi, S. / Yamakawa, S. / Kosemura, D. / Takei, M. / Nagata, K. / Akamatsu, H. / Aamari, K. / Tateshita, Y. / Wakabayashi, H. / Tsukamoto, M. et al. | 2006
- 16
-
New experimental insight into ballisticity of transport in strained bulk MOSFETsFleury, D. / Bidal, G. / Cros, A. / Boeuf, F. / Skotnicki, T. / Ghibaudo, G. et al. | 2006
- 18
-
Comprehensive understanding of surface roughness limited mobility in unstrained- and strained-Si MOSFETs by novel characterization scheme of Si/SiO2 interface roughnessZhao, Y. / Matsumoto, H. / Sato, T. / Koyama, S. / Takenaka, M. / Takagi, S. et al. | 2006
- 20
-
Analyses and optimization of strained-SiGe on Si pMOSFETs by using full-band device simulationTakeda, H. / Kawada, M. / Takeuchi, K. / Hane, M. et al. | 2006
- 24
-
Cross-point phase change memory with 4F2 cell size driven by low-contact-resistivity poly-Si diodeSasago, Y. / Kinoshita, M. / Morikawa, T. / Kurotsuchi, K. / Hanzawa, S. / Mine, T. / Shima, A. / Fujisaki, Y. / Kume, H. / Moriya, H. et al. | 2006
- 26
-
Vertical cross-point resistance change memory for ultra-high density non-volatile memory applicationsHong Sik Yoon, / In-Gyu Baek, / Jinshi Zhao, / Hyunjun Sim, / Min Young Park, / Hansin Lee, / Gyu-Hwan Oh, / Jong Chan Shin, / In-Seok Yeo, / U-In Chung, et al. | 2006
- 28
-
NiO resistance change memory with a novel structure for 3D integration and improved confinement of conduction pathByoungil Lee, / Wong, H.-S. Philip et al. | 2006
- 30
-
Oxide-based RRAM: Uniformity improvement using a new material-oriented methodologyGao, B. / Zhang, H.W. / Yu, S. / Sun, B. / Liu, L.F. / Liu, X.Y. / Wang, Y. / Han, R.Q. / Kang, J.F. / Yu, B. et al. | 2006
- 34
-
Gate first high-k/metal gate stacks with zero SiOx interface achieving EOT=0.59nm for 16nm applicationHuang, J. / Heh, D. / Sivasubramani, P. / Kirsch, P. D. / Bersuker, G. / Gilmer, D. C. / Quevedo-Lopez, M.A. / Hussain, M. M. / Majhi, P. / Lysaght, P. et al. | 2006
- 36
-
Cost-Effective 28-nm LSTP CMOS using gate-first metal gate/high-k technologyTomimatsu, T. / Goto, Y. / Kato, H. / Amma, M. / Igarashi, M. / Kusakabe, Y. / Takeuchi, M. / Ohbayashi, S. / Sakashita, S. / Kawahara, T. et al. | 2006
- 38
-
Optimized ultra-low thermal budget process flow for advanced High-K / Metal gate first CMOS using laser-annealing technologyOrtolland, C. / Ragnarsson, L.-A. / Favia, P. / Richard, O. / Kerner, C. / Chiarella, T. / Rosseel, E. / Okuno, Y. / Akheyar, A. / Tseng, J. et al. | 2006
- 40
-
Impact of area scaling on threshold voltage lowering in La-containing high-k/metal gate NMOSFETs fabricated on (100) and (110)SiInoue, M. / Satoh, Y. / Kadoshima, M. / Sakashita, S. / Kawahara, T. / Anma, M. / Nakagawa, R. / Umeda, H. / Matsuyama, S. / Fujimoto, H. et al. | 2006
- 42
-
pFET Vt control with HfO2/TiN/poly-Si gate stack using a lateral oxygenation processCartier, E. / Steen, M. / Linder, B. P. / Ando, T. / Iijima, R. / Frank, M. / Newbury, J.S. / Kim, Y. H. / McFeely, F. R. / Copel, M. et al. | 2006
- 46
-
New insights into oxide traps characterization in gate-all-around nanowire transistors with TiN metal gates based on combined Ig-Id RTS techniqueZhang, Liangliang / Jing Zhuge, / Wang, Runsheng / Ru Huang, / Changze Liu, / Dake Wu, / Zhaoyi Kang, / Kim, Dong-Won / Donggun Park, / Yangyuan Wang, et al. | 2006
- 48
-
The first observation of shot noise characteristics in 10-nm scale MOSFETsJeon, J. / Lee, J. / Kim, J. / Park, C. H. / Lee, H. / Oh, H. / Kang, H.-K. / Park, B.-G. / Shin, H. et al. | 2006
- 50
-
Increasing threshold voltage variation due to random telegraph noise in FETs as gate lengths scale to 20 nmTega, N. / Miki, H. / Pagette, F. / Frank, D. J. / Ray, A. / Rooks, M. J. / Haensch, W. / Torii, K. et al. | 2006
- 52
-
A new observation of strain-induced slow traps in advanced CMOS technology with process-induced strain using random telegraph noise measurementLin, M. H. / Hsieh, E. R. / Chung, Steve S. / Tsai, C. H. / Liu, P. W. / Lin, Y. H. / Tsai, C. T. / Ma, G. H. et al. | 2006
- 54
-
Single-charge-based modeling of transistor characteristics fluctuations based on statistical measurement of RTN amplitudeTakeuchi, K. / Nagumo, T. / Yokogawa, S. / Imai, K. / Hayashi, Y. et al. | 2006
- 58
-
3D integration for energy efficient system designBorkar, Shekhar et al. | 2006
- 60
-
Process-design considerations for three dimensional memory integrationIyer, S.S. / Kirihata, T. / Wordeman, M.R. / Barth, J. / Hannon, R.H. / Malik, R. et al. | 2006
- 64
-
New 3D integration technology and 3D system LSIsKoyanagi, Mitsumasa et al. | 2006
- 68
-
Leading edge 3D technology for high volume manufacturingArkalgud, Sitaram R. et al. | 2006
- 70
-
TSV and 3D wafer bonding technologies for advanced stacking system and application at ITRILo, Wei-Chung / Chen, Yu-Hua / Ko, Cheng-Ta / Kao, Ming-Ger et al. | 2006
- 74
-
Vth variation and strain control of high Ge% thin SiGe channels by millisecond anneal realizing high performance pMOSFET beyond 16nm nodeLee, S.-H. / Huang, J. / Majhi, P. / Kirsch, P.D. / Min, B.-G. / Park, C.-S. / Oh, J. / Loh, W.-Y. / Kang, C.-Y. / Sassman, B. et al. | 2006
- 76
-
High quality GeO2/Ge interface formed by SPA radical oxidation and uniaxial stress engineering for high performance Ge NMOSFETsKobayashi, Masaharu / Irisawa, Toshihumi / Kope, Blanka M. / Yun Sun, / Saraswat, Krishna / Wong, H. -S. Philip / Pianetta, Piero / Nishi, Yoshio et al. | 2006
- 78
-
New approach to form EOT-scalable gate stack with strontium germanide interlayer for high-k/Ge MISFETsKamata, Yoshiki / Takashima, Akira / Kamimuta, Yuuichi / Tezuka, Tsutomu et al. | 2006
- 80
-
Physical origins of mobility enhancement of Ge pMISFETs with Si passivation layersTaoka, N. / Mizubayashi, W. / Morita, Y. / Migita, S. / Ota, H. / Takagi, S. et al. | 2006
- 82
-
Impact of EOT scaling down to 0.85nm on 70nm Ge-pFETs technology with STIMitard, J. / Shea, C. / DeJaeger, B. / Pristera, A. / Wang, G. / Houssa, M. / Eneman, G. / Hellings, G. / Wang, W.-E. / Lin, J.C. et al. | 2006
- 86
-
Rump sessions| 2006
- 90
-
High hole mobility in multiple silicon nanowire gate-all-around pMOSFETs on (110) SOIChen, Jiezhi / Saraya, Takuya / Hiramoto, Toshiro et al. | 2006
- 92
-
Gate-all-around quantum-wire field-effect transistor with Dopant Segregation at Metal-Semiconductor-Metal heterostuctureWong, Hoong-Shing / Tan, Lian-Huat / Lap Chan, / Lo, Guo-Qiang / Samudra, Ganesh / Yeo, Yee-Chia et al. | 2006
- 94
-
Sub-10 nm gate-all-around CMOS nanowire transistors on bulk Si substrateMing Li, / Yeo, Kyoung Hwan / Suk, Sung Dae / Yeoh, Yun Young / Kim, Dong-Won / Chung, Tae Young / Oh, Kyung Seok / Lee, Won-Seong et al. | 2006
- 96
-
A novel thin BOX SOI technology using bulk Si wafer for system-on-chip (SoC) applicationOh, Chang Woo / Bae, Hyun Jun / Ha, Jae Kyu / Park, Sang Jin / Park, Bok Kyung / Kim, Dong-Won / Chung, TaeYoung / Oh, Kyung Seok / Lee, Won-Seong et al. | 2006
- 100
-
Selective phase modulation of NiSi using N-ion implantation for high performance dopant-segregated source/drain n-channel MOSFETsLoh, W.-Y. / Hung, P. Y. / Coss, B. E. / Kalra, P. / Injo Ok, / Smith, Greg / Kang, C.-Y. / Lee, S.-H. / Oh, J. / Sassman, B. et al. | 2006
- 102
-
Ultimate contact resistance scaling enabled by an accurate contact resistivity extraction methodology for sub-20 nm nodeLin, Hong-Nien / Hsu, Wen-Wei / Lee, Wen-Chin / Wann, Clement H. et al. | 2006
- 104
-
CMOS band-edge schottky barrier heights using dielectric-dipole mitigated (DDM) metal/Si for source/drain contact resistance reductionCossa, Brian E. / Wei-Yip Loh, / Jungwoo Oh, / Smith, Greg / Smith, Casey / Adhikari, Hemant / Sassman, Barry / Parthasarathy, Srivatsan / Barnett, Joel / Majhi, Prashant et al. | 2006
- 106
-
Single silicide comprising Nickel-Dysprosium alloy for integration in p- and n-FinFETs with independent control of contact resistance by Aluminum implantSinha, Mantavya / Lee, Rinus T. P. / Devi, Sivasubramaniam Nandini / Lo, Guo-Qiang / Chor, Eng Fong / Yeo, Yee-Chia et al. | 2006
- 110
-
Analysis of extra VT variability sources in NMOS using Takeuchi plotTsunomura, T. / Nishida, A. / Yano, F. / Putra, A.T. / Takeuchi, K. / Inaba, S. / Kamohara, S. / Terada, K. / Mama, T. / Hiramoto, T. et al. | 2006
- 112
-
Impact of uniaxial strain on channel backscattering characteristics and drain current variation for nanoscale PMOSFETsLee, Wei / Kuo, Jack J.-Y. / Chen, Willian P.-N. / Pin Su, / Jeng, Min-Chie et al. | 2006
- 114
-
Physical understanding of Vth and Idsat variations in (110) CMOSFETsSaitoh, Masumi / Yasutake, Nobuaki / Nakabayashi, Yukio / Uchida, Ken / Numata, Toshinori et al. | 2006
- 116
-
A new methodology for evaluating VT variability considering dopant depth profilePutra, A. T. / Tsunomura, T. / Nishida, A. / Kamohara, S. / Takeuchi, K. / Inaba, S. / Terada, K. / Hiramoto, T. et al. | 2006
- 118
-
Comprehensive analysis of variability sources of FinFET characteristicsMatsukawa, T. / O'uchi, S. / Endo, K. / Ishikawa, Y. / Yamauchi, H. / Liu, Y.X. / Tsukada, J. / Sakamoto, K. / Masahara, M. et al. | 2006
- 122
-
A hybrid CMOS/magnetic tunnel junction approach for nonvolatile integrated circuitsOhno, Hideo et al. | 2006
- 124
-
Graphene nanostructures for device applicationsAppenzeller, Joerg / Yang Sui, / Chen, Zhihong et al. | 2006
- 128
-
Gate modulation of graphene contacts - on the scaling of graphene FETsChen, Zhihong / Appenzeller, Joerg et al. | 2006
- 130
-
Nonvolatile solid-electrolyte switch embedded into Cu interconnectSakamoto, T. / Tada, M. / Banno, N. / Tsuji, Y. / Saitoh, Y. / Yabe, Y. / Hada, H. / Iguchi, N. / Aono, M. et al. | 2006
- 132
-
Collective-effect state variables for post-CMOS logic applicationsChen, A. / Jacob, A. P. / Sung, C. Y. / Wang, K. L. / Khitun, A. / Porod, W. et al. | 2006
- 136
-
Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devicesKatsumata, Ryota / Kito, Masaru / Fukuzumi, Yoshiaki / Kido, Masaru / Tanaka, Hiroyasu / Komori, Yosuke / Ishiduki, Megumi / Matsunami, Junya / Fujiwara, Tomoko / Nagata, Yuzo et al. | 2006
- 138
-
Extremely scaled gate-first high-k/metal gate stack with EOT of 0.55 nm using novel interfacial layer scavenging techniques for 22nm technology node and beyondChoi, K. / Jagannathan, H. / Choi, C. / Edge, L. / Ando, T. / Frank, M. / Jamison, P. / Wang, M. / Cartier, E. / Zafar, S. et al. | 2006
- 140
-
High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm2 SRAM and ultra low-k back end with eleven levels of copperGreene, B. / Liang, Q. / Amarnath, K. / Wang, Y. / Schaeffer, J. / Cai, M. / Liang, Y. / Saroop, S. / Cheng, J. / Rotondaro, A. et al. | 2006
- 142
-
Characteristics of sub 5nm tri-gate nanowire MOSFETs with single and poly Si channels in SOI structureSuk, Sung Dae / Ming Li, / Yeoh, Yun Young / Yeo, Kyoung Hwan / Ha, Jae Kyu / Lim, Hyunseok / Park, HyunWoo / Kim, Dong-Won / Chung, TaeYoung / Oh, Kyung Seok et al. | 2006
- 146
-
Comprehensive design methodology of dopant profile to suppress gate-LER-induced threshold voltage variability in 20nm NMOSFETsFukutome, H. / Hori, Y. / Sponton, L. / Hosaka, K. / Momiyama, Y. / Satoh, S. / Gull, R. / Fichtner, W. / Sugii, T. et al. | 2006
- 148
-
Post-Fabrication self-convergence scheme for suppressing variability in SRAM cells and logic transistorsSuzuki, Makoto / Saraya, Takuya / Shimizu, Ken / Sakurai, Takayasu / Hiramoto, Toshiro et al. | 2006
- 150
-
Low voltage (Vdd∼0.6 V) SRAM operation achieved by reduced threshold voltage variability in SOTB (silicon on thin BOX)Tsuchiya, Ryuta / Sugii, Nobuyuki / Ishigaki, Takashi / Morita, Yusuke / Yoshimoto, Hiroyuki / Torii, Kazuyoshi / Kimura, Shin'ichiro et al. | 2006
- 152
-
Reduction of RTA-driven intra-die variation via model-based layout optimizationScott, J. C. / Gluschenkov, O. / Goplen, B. / Landis, H. / Nowak, E. / Clougherty, F. / Mocuta, A. / Hook, T. / Zamdmer, N. / Lai, C. W. et al. | 2006
- 156
-
Sophisticated methodology of dummy pattern generation for suppressing dislocation induced contact misalignment on flash lamp annealed eSiGe waferFujii, O. / Sanuki, T. / Oshiki, Y. / Itani, T. / Kugimiya, T. / Nakamura, N. / Tamura, M. / Sato, T. / Mizushima, I. / Yoshimura, H. et al. | 2006
- 158
-
Design of high-performance and highly reliable nMOSFETs with embedded Si:C S/D extension stressor(Si:C S/D-E)Chung, Steve S. / Hsieh, E. R. / Liu, P. W. / Chiang, W. T. / Tsai, S. H. / Tsai, T. L. / Huang, R. M. / Tsai, C. H. / Teng, W. Y. / Li, C. I. et al. | 2006
- 160
-
26 nm gate length CMOSFETs with aggressively reduced silicide position by using carbon cluster co-implanted raised source/drain extension structureYako, Koichi / Yamamoto, Toyoji / Uejima, Kazuya / Hase, Takashi / Hane, Masami et al. | 2006
- 162
-
The fabrication of low leakage junction with ultra shallow profile by the combination annealing of 10-ms low power and 2-ms high power FLAOnizawa, Takashi / Kato, Shinichi / Takayuki Aoyama, / Kazuto Ikeda, / Yuzuru Ohji, et al. | 2006
- 166
-
GeOI and SOI 3D monolithic cell integrations for high density applicationsBatude, P. / Vinet, M. / Pouydebasque, A. / Le Royer, C. / Previtali, B. / Tabone, C. / Clavelier, L. / Michaud, S. / Valentian, A. / Thomas, O. et al. | 2006
- 168
-
Scratch-free dielectric CMP slurry with 5-nm colloidal ceria abrasiveRyuzaki, D. / Hoshi, Y. / Machii, Y. / Koyama, N. / Sakurai, H. / Ashizawa, T. et al. | 2006
- 170
-
Reliability of a 300-mm-compatible 3DI technology based on hybrid Cu-adhesive wafer bondingYu, R. R. / Liu, F. / Polastre, R. J. / Chen, K.-N. / Liu, X. H. / Shi, L. / Perfecto, E. D. / Klymko, N. R. / Chace, M. S. / Shaw, T. M. et al. | 2006
- 172
-
Impact of backside Cu contamination in the 3D integration processHozawa, Kazuyuki / Kenichi Takeda, / Kazuyoshi Torii, et al. | 2006
- 176
-
Programming characteristics of the steep turn-on/off feedback FET (FBFET)Chun Wing Yeung, / Alvaro Padilla, / Tsu-Jae King Liu, / Chenming Hu, et al. | 2006
- 178
-
Germanium-source tunnel field effect transistors with record high ION/IOFFSung Hwan Kim, / Kam, Hei / Hu, Chenming / Liu, Tsu-Jae King et al. | 2006
- 180
-
Possibilities for VDD = 0.1V logic using carbon-based tunneling field effect transistorsYunfei Gao, / Low, Tony / Lundstrom, Mark et al. | 2006
- 182
-
A metallic-CNT-tolerant carbon nanotube technology using Asymmetrically-Correlated CNTs (ACCNT)Lin, Albert / Patil, Nishant / Hai Wei, / Mitra, Subhasish / Wong, H.-S. Philip et al. | 2006
- 186
-
Novel Vertical-Stacked-Array-Transistor (VSAT) for ultra-high-density and cost-effective NAND Flash memory devices and SSD (Solid State Drive)Jiyoung Kim, / Hong, Augustin J. / Sung Min Kim, / Song, Emil B. / Park, Jeung Hun / Jeonghee Han, / Siyoung Choi, / Deahyun Jang, / Joo -Tae Moon, / Wang, Kang L . et al. | 2006
- 188
-
Multi-layered Vertical Gate NAND Flash overcoming stacking limit for terabit density storageWonjoo Kim, / Sangmoo Choi, / Junghun Sung, / Taehee Lee, / Park, Chulmin / Hyoungsoo Ko, / Juhwan Jung, / Inkyong Yoo, / Park, Yoondong et al. | 2006
- 190
-
20nm-node planer MONOS cell technology for multi-level NAND Flash MemoryYaegashi, T. / Okamura, T. / Sakamoto, W. / Matsunaga, Y. / Toba, T. / Sakuma, K. / Gomikawa, K. / Komiya, K. / Nagashima, H. / Akahori, H. et al. | 2006
- 192
-
Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memoryJang, Jaehoon / Kim, Han-Soo / Cho, Wonseok / Cho, Hoosung / Jinho Kim, / Shim, Sun Il / Younggoan, / Jeong, Jae-Hun / Son, Byoung-Keun / Kim, Dong Woo et al. | 2006
- 196
-
Guiding principles toward future gate stacks given by the construction of new physical conceptsShiraishi, Kenji et al. | 2006
- 198
-
Applications of advanced transmission electron microscopy techniques in gate stack scalingStemmer, Susanne / LeBeau, James M. / Cagnon, Joel / Yoontae Hwang, / Engel-Herbert, Roman et al. | 2006
- 200
-
Charged defects reduction in gate insulator with multivalent materialsKouda, M. / Umezawa, N. / Kakushima, K. / Ahmet, P. / Shiraishi, K. / Chikyow, T. / Yamada, K. / Iwai, H. et al. | 2006
- 202
-
Correlation among crystal defects, depletion regions and junction leakage in sub-30-nm gate-length MOSFETs: Direct examinations by electron holographyIkarashi, N. / Yako, K. / Uejima, K. / Yamamoto, T. / Ikezawa, T. / Hane, M. et al. | 2006
- 204
-
A direct observation on the structure evolution of memory-switching phenomena using in-situ TEMDongkyu Cha, / Su Jin Ahn, / Park, S.Y. / Horii, H. / Kim, D. H. / Kim, Y. K. / Park, S.O. / U In Jung, / Kim, Moon J. / Jiyoung Kim, et al. | 2006
- 208
-
A scalable and highly manufacturable single metal gate/high-k CMOS integration for sub-32nm technology for LSTP applicationsPark, C. S. / Hussain, M. M. / Huang, J. / Park, C. / Tateiwa, K. / Young, C. / Park, H. K. / Cruz, M. / Gilmer, D. / Rader, K. et al. | 2006
- 210
-
A highly manufacturable 28nm CMOS low power platform technology with fully functional 64Mb SRAM using dual/tripe gate oxide processShien-Yang Wu, / Liaw, J.J. / Lin, C.Y. / Chiang, M.C. / Yang, C.K. / Cheng, J.Y. / Tsai, M.H. / Liu, M.Y. / Wu, P.H. / Chang, C.H. et al. | 2006
- 212
-
Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drainCheng, K. / Khakifirooz, A. / Kulkarni, P. / Kanakasabapathy, S. / Schmitz, S. / Reznicek, A. / Adam, T. / Zhu, Y. / Li, J. / Faltermeier, J. et al. | 2006
- 214
-
The study of mobility-tin, trade-off in deeply scaled high-k / metal gate devices and scaling design guideline for 22nm-node generationGoto, Masakazu / Kawanaka, Shigeru / Inumiya, Seiji / Kusunoki, Naoki / Saitoh, Masumi / Tatsumura, Kosuke / Kinoshita, Atsuhiro / Inaba, Satoshi / Toyoshima, Yoshiaki et al. | 2006
- 218
-
High-density and high-speed 128Mb chain FeRAM™ with SDRAM-compatible DDR2 interfaceShimojo, Yoshiro / Konno, Atsushi / Nishimura, Jun / Okada, Takayuki / Yamada, Yuki / Kitazaki, Soichiro / Furuhashi, Hironobu / Yamazaki, Soichi / Yahashi, Katsunori / Tomioka, Kazuhiro et al. | 2006
- 220
-
Parallel multi-confined (PMC) cell technology for high density MLC PRAMOh, G.H. / Park, Y.L. / Lee, J.I. / Im, D.H. / Bae, J.S. / Kim, D.H. / Ahn, D.H. / Horii, H. / Park, S.O. / Yoon, H.S. et al. | 2006
- 222
-
Performance breakthrough in NOR flash memory with dopant-segregated Schottky-barrier (DSSB) SONOS devicesChoi, Sung-Jin / Han, Jin-Woo / Sungho Kim, / Dong-Il Moon, / Moon-Gyu Jang, / Jin Su Kim, / Kwang Hee Kim, / Gi Sung Lee, / Jae Sub Oh, / Myong Ho Song, et al. | 2006
- 224
-
A novel buried-channel FinFET BE-SONOS NAND Flash with improved memory window and cycling enduranceLue, Hang-Ting / Yi-Hsuan Hsiao, / Pei-Ying Du, / Sheng-Chih Lai, / Tzu-Hsuan Hsu, / Hong, S. P. / Wu, M. T. / Hsu, F. H. / Lien, N. Z. / Chi-Pin Lu, et al. | 2006
- 228
-
SPRAM with large thermal stability for high immunity to read disturbance and long retention for high-temperature operationOno, K. / Kawahara, T. / Takemura, R. / Miura, K. / Yamanouchi, M. / Hayakawa, J. / Ito, K. / Takahashi, H. / Matsuoka, H. / Ikeda, S. et al. | 2006
- 230
-
Low-current perpendicular domain wall motion cell for scalable high-speed MRAMFukami, S. / Suzuki, T. / Nagahara, K. / Ohshima, N. / Ozaki, Y. / Saito, S. / Nebashi, R. / Sakimura, N. / Honjo, H. / Mori, K. et al. | 2006
- 234
-
Highly scalable Z-RAM with remarkably long data retention for DRAM applicationTae-Su Jang, / Joong-Sik Kim, / Sang-Min Hwang, / Young-Hoon Oh, / Kwang-Myung Rho, / Seoung-Ju Chung, / Su-Ock Chung, / Jae-Geun Oh, / Sunil Bhardwaj, / Jungtae Kwon, et al. | 2006
- 238
-
Mechanisms for low on-state current of Ge (SiGe) nMOSFETs: A comparative study on gate stack, resistance, and orientation-dependent effective massesOh, J. / Ok, I. / Kang, C.-Y. / Jamil, M. / Lee, S.-H. / Loh, W.-Y. / Huang, J. / Sassman, B. / Smith, L. / Parthasarathy, S. et al. | 2006
- 240
-
High velocity Si-nanodot : A candidate for SRAM applications at 16nm node and belowBidal, G. / Boeuf, F. / Denorme, S. / Loubet, N. / Huguenin, J.L. / Perreau, P. / Fleury, D. / Leverd, F. / Lagrasta, S. / Barnola, S. et al. | 2006
- 242
-
High mobility metal S/D III–V-On-Insulator MOSFETs on a Si substrate using direct wafer bondingYokoyama, M. / Yasuda, T. / Takagi, H. / Yamada, H. / Fukuhara, N. / Hata, M. / Sugiyama, M. / Nakano, Y. / Takenaka, M. / Takagi, S. et al. | 2006
- 244
-
Strained In0.53Ga0.47As n-MOSFETs: Performance boost with in-situ doped lattice-mismatched source/drain stressors and interface engineeringChin, Hock-Chun / Xiao Gong, / Xinke Liu, / Zhe Lin, / Yeo, Yee-Chia et al. | 2006
- 246
-
Author index| 2006
- c1
-
Frontcover| 2006
- c4
-
Backcover| 2006
- iii
-
Foreword| 2006
- iv
-
Executive committees| 2006
- vi
-
Table of contents| 2006
- xiii
-
Short ourse program| 2006
- xiv
-
Conference schedule| 2006
- xv
-
Floor map| 2006