0.18 /spl mu/m low voltage/low power RF CMOS with zero Vth analog MOSFETs made by undoped epitaxial channel technique (English)
- New search for: Ohguro, T.
- New search for: Naruse, H.
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In:
International Electron Devices Meeting. IEDM Technical Digest
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837-840
;
1997
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ISBN:
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ISSN:
- Conference paper / Electronic Resource
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Title:0.18 /spl mu/m low voltage/low power RF CMOS with zero Vth analog MOSFETs made by undoped epitaxial channel technique
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Contributors:Ohguro, T. ( author ) / Naruse, H. ( author ) / Sugaya, H. ( author ) / Morifuji, E. ( author ) / Nakamura, S. ( author ) / Yoshitomi, T. ( author ) / Morimoto, T. ( author ) / Momose, H.S. ( author ) / Katsumata, Y. ( author ) / Iwai, H. ( author )
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Published in:
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Publisher:
- New search for: IEEE
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Publication date:1997-01-01
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Size:433575 byte
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ISBN:
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ISSN:
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DOI:
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Type of media:Conference paper
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Type of material:Electronic Resource
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Language:English
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 0_2
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International Electron Devices Meeting. IEDM Technical Digest [Front Matter and Table of Contents]| 1997
- 0_25
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Author index| 1997
- 3
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Multimedia: future and impact for semiconductor technologySasaki, H. et al. | 1997
- 9
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Pushing the limits of lithography for IC productionBrunner, T. et al. | 1997
- 15
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Chip cards-the application revolutionHamann, U. et al. | 1997
- 15
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The Significance of Innovation in the Semiconductor Industry for Performance in Chip Card ApplicationsHamann, U. / IEEE; Electron Devices Society et al. | 1997
- 25
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Two-dimensional borderless contact pad technology for a 0.135 /spl mu/m/sup 2/ 4-gigabit DRAM cellKoga, H. / Kasai, N. / Tatsumi, T. / Hayashi, Y. / Saito, Y. / Nakajima, K. / Tokunaga, K. / Onoda, N. / Tokashiki, K. / Nishizawa, A. et al. | 1997
- 25
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Two-Dimensional Borderless Contact Pad Technology for a 0.135m^2 4-Gigabit DRAM CellKoga, H. / Matsuki, T. / Kasai, N. / Tatsumi, T. / IEEE; Electron Devices Society et al. | 1997
- 29
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A simple 4 G-bit DRAM technology utilizing high-aspect-ratio pillars for cell-capacitors and peripheral-vias simultaneously fabricatedNakamura, S. / Kosugi, M. / Sato, A. / Hatada, A. / Minakata, H. / Kobayashi, M. / Kurahashi, T. / Suzuki, R. / Sasaki, N. et al. | 1997
- 33
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Embedded DRAM technologiesIshiuchi, H. / Yoshida, T. / Takato, H. / Tomioka, K. / Matsuo, K. / Momose, H. / Sawada, S. / Yamazaki, K. / Maeguchi, K. et al. | 1997
- 37
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A salicide-bridged trench capacitor with a double-sacrificial-Si/sub 3/N/sub 4/-sidewall (DSS) for high-performance logic-embedded DRAMsTogo, M. / Iwao, S. / Nobusawa, H. / Hamada, M. / Yoshida, K. / Yasuzato, N. / Tanigawa, T. et al. | 1997
- 37
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A Salicide-Bridged Trench Capacitor with a Double-Sacrificial-Si~3N~4-Side-wall(DSS) for High Performance Logic-Embedded DRAMsTogo, M. / Iwao, S. / Nobusawa, H. / Hamada, M. / IEEE; Electron Devices Society et al. | 1997
- 41
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Low temperature metal-based cell integration technology for gigabit and embedded DRAMsYoshida, M. / Kumauchi, T. / Kawakita, K. / Ohashi, N. / Enomoto, H. / Umezawa, T. / Yamamoto, N. / Asano, I. / Tadaki, Y. et al. | 1997
- 45
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Trade-offs in the integration of high performance devices with trench capacitor DRAMCrowder, S. / Stiffler, S. / Parries, P. / Bronner, G. / Nesbit, L. / Wille, W. / Powell, M. / Ray, A. / Chen, B. / Davari, B. et al. | 1997
- 51
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2-GHz Si power MOSFET technologyYoshida, I. et al. | 1997
- 55
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Novel substrate contact structure for high-Q silicon-integrated spiral inductorsBurghartz, J.N. / Ruehli, A.E. / Jenkins, K.A. / Soyuer, M. / Nguyen-Ngoc, D. et al. | 1997
- 59
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High Q microwave inductors in CMOS double-metal technology and its substrate bias effects for 2 GHz RF ICs applicationMin Park, / Cheon Soo Kim, / Jong Moon Park, / Hyun Kyu Yu, / Kee Soo Nam, et al. | 1997
- 63
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Extremely high-Q tunable inductor for Si-based RF integrated circuit applicationsPehlke, D.R. / Burstein, A. / Chang, M.F. et al. | 1997
- 67
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Monolithic high-performance three-dimensional coil inductors for wireless communication applicationsYoung, D.J. / Malba, V. / Ou, J.-J. / Bernhardt, A.F. / Boser, B.E. et al. | 1997
- 73
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Ultra-thin gate dielectrics: they break down, but do they fail?Weir, B.E. / Silverman, P.J. / Monroe, D. / Krisch, K.S. / Alam, M.A. / Alers, G.B. / Sorsch, T.W. / Timp, G.L. / Baumann, F. / Liu, C.T. et al. | 1997
- 77
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Thickness and polarity dependence of intrinsic breakdown of ultra-thin reoxidized-nitride for DRAM technology applicationsWu, E. / Hwang, C. / Vollertsen, R. / Shen, H. / Kleinhenz, R. / Radens, C. / Strong, A. et al. | 1997
- 81
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Investigations of hot-carrier-induced breakdown of thin oxidesKamakura, Y. / Utsunomiya, H. / Tomita, T. / Umeda, K. / Taniguchi, K. et al. | 1997
- 85
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Intrinsic and stress-induced traps in the direct tunneling current of 2.3-3.8 nm oxides and unified characterization methodologies of sub-3 nm oxidesLiu, C.T. / Ghetti, A. / Ma, Y. / Alers, G. / Chang, C.P. / Cheung, K.P. / Colonell, J.I. / Lai, W.Y.C. / Pai, C.S. / Liu, R. et al. | 1997
- 85
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Intrinsic and Stress-Induced Traps in the Direct Tunneling Current of 2.3-3.8 nm Oxides and Unified Characterization Methodologies for Sub-30 nm OxidesLiu, C. T. / Ghetti, A. / Ma, Y. / Alers, G. / IEEE; Electron Devices Society et al. | 1997
- 89
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Characterization of various stress-induced oxide traps in MOSFET's by using a novel transient current techniqueTahui Wang, / Chiang, L.P. / Zous, N.K. / Chang, T.E. / Huang, C. et al. | 1997
- 93
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High-temperature reliability behavior of SSI-flash E/sup 2/PROM devicesDe Blauwe, J. / Wellekens, D. / Groeseneken, G. / Haspeslagh, L. / Van Houdt, J. / Deferm, L. / Maes, H.E. et al. | 1997
- 93
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High-Temperature Reliability Behavior of SSI-Flash E^2PROM DevicesDeBlauwe, J. / Wellekens, D. / Groeseneken, G. / Haspeslagh, L. / IEEE; Electron Devices Society et al. | 1997
- 99
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A High-Performance 0.1m CMOS with Elevated Salicide Using Novel Si-SEG ProcessWakabayashi, H. / Yamamoto, T. / Tatsumi, T. / Tokunaga, K. / IEEE; Electron Devices Society et al. | 1997
- 99
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A high-performance 0.1 /spl mu/m CMOS with elevated salicide using novel Si-SEG processWakabayashi, H. / Yamamoto, T. / Tatsumi, T. / Tokunaga, K. / Tamura, T. / Mogami, T. / Kunio, T. et al. | 1997
- 103
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Low resistance Ti or Co salicided raised source/drain transistors for sub-0.13 /spl mu/m CMOS technologiesChao, C.-P. / Violette, K.E. / Unnikrishnan, S. / Nandakumar, M. / Wise, R.L. / Kittl, J.A. / Hong, Q.-Z. / Chen, I.-C. et al. | 1997
- 103
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Low Resistance Ti or Co Salicided Raised Source/Drain Transistors for Sub-0.13m CMOS TechnologiesChao, C. / Violette, K. / Unnikrishnan, S. / Nandakumar, M. / IEEE; Electron Devices Society et al. | 1997
- 107
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CoSi~2 with Low Diode Leakage and Low Sheet Resistance of 0.065m Gate LengthHong, Q. Z. / Shiau, W. T. / Yang, H. / Kittl, J. / IEEE; Electron Devices Society et al. | 1997
- 107
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CoSi/sub 2/ with low diode leakage and low sheet resistance at 0.065 /spl mu/m gate lengthHong, Q.Z. / Shiau, W.T. / Yang, H. / Kittl, J.A. / Chao, C.P. / Tsai, H.L. / Krishnan, S. / Chen, I.C. / Havemann, R.H. et al. | 1997
- 111
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Novel One-Step RTP Ti SALICIDE Process with Low Sheet Resistance 0.06 m Gates and High Drive CurrentKittl, J. / Hong, Q. Z. / Rodder, M. / Breedijk, T. / IEEE; Electron Devices Society et al. | 1997
- 111
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Novel one-step RTP Ti salicide process with low sheet resistance 0.06 mu m gates and high drive currentKittl, J.A. / Hong, Qi-Zhong / Rodder, M. / Breedijk, T. et al. | 1997
- 111
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Novel one-step RTP Ti salicide process with low sheet resistance 0.06 /spl mu/m gates and high drive currentKittl, J.A. / Qi-Zhong Hong, / Rodder, M. / Breedijk, T. et al. | 1997
- 115
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Temperature and current effects on small-geometry-contact resistanceBanerjee, K. / Dixit, G. / Chenming Hu, et al. | 1997
- 119
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Low-Resistivity Noble Integrated Clustered Electrode (NICE) WSix Polycide and its Application to a Deep Sub-Quarter Micron CMOSByun, J. S. / Park, J. S. / Lee, B. H. / Sohn, D. K. / IEEE; Electron Devices Society et al. | 1997
- 119
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Low-resistivity noble integrated clustered electrode (NICE) WSi/sub x/ polycide and its application to a deep sub-quarter micron CMOSJeong Soo Byun, / Ji-Soo Park, / Byung Hak Lee, / Dong-Kyun Sohn, / Jin Won Park, / Jae Jeong Kim, / Jeong Mo Hwang, et al. | 1997
- 125
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Hierarchical interconnect modelingChiprout, E. et al. | 1997
- 129
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Automated extraction of capacitances and electrostatic forces in MEMS and ULSI interconnects from the mask layoutBachtold, M. / Taschini, S. / Korvink, J.G. / Baltes, H. et al. | 1997
- 133
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A simulation methodology for assessing the impact of spatial/pattern dependent interconnect parameter variation on circuit performanceStine, B.E. / Mehrotra, V. / Boning, D.S. / Chung, J.E. / Ciplickas, D.J. et al. | 1997
- 137
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Modeling of pattern-dependent on-chip interconnect geometry variation for deep-submicron process and design technologyNakagawa, O.S. / Oh, S.-Y. / Ray, G. et al. | 1997
- 141
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Spice simulation of 0.18 /spl mu/m CMOS ring oscillators using physical models for capacitance and series resistanceBiesemans, S. / Kubicek, S. / De Meyer, K. et al. | 1997
- 141
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Spice Simulation of 0.18m CMOS Ringoscillators Using Physical Models for Capacitance and Series ResistanceBiesemans, S. / Kubicek, S. / De Meyer, K. / IEEE; Electron Devices Society et al. | 1997
- 145
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New Method for Verification of Analytical Device Models Using Transistor Parameter FluctuationsKuehn, C. / Marksteiner, S. / Kopley, T. / Weber, W. / IEEE; Electron Devices Society et al. | 1997
- 145
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New method for verification of analytical device models using transistor parameter fluctuations [MOSFETs]Kuhn, C. / Marksteiner, S. / Kopley, T.E. / Weber, W. et al. | 1997
- 149
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An application of process synthesis methodology for first-pass fabrication success of high-performance deep-submicron CMOSSaxena, S. / Burch, R. / Vasanth, K. / Rao, S. / Fernando, C. / Davis, J. / Mozumder, P.K. et al. | 1997
- 155
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Fabrication of Single Electron Memory on Atomically Flat -Al~2O~3 Substrate made by ATM Nano-Oxidation ProcessMatsumoto, K. / Gotoh, Y. / Shirakashi, J. / Maeda, T. / IEEE; Electron Devices Society et al. | 1997
- 155
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Fabrication of single electron memory on atomically flat /spl alpha/-Al/sub 2/O/sub 3/ substrate made by AFM nano-oxidation processMatsumoto, K. / Gotoh, Y. / Shirakashi, J. / Maeda, T. / Harris, J.S. et al. | 1997
- 159
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Single Electron Charging of Sn Nanocrystals in Thin SiO~2 Film Formed by Low Energy Ion ImplantationNakajima, A. / Futatsugi, T. / Horiguchi, N. / Nakao, H. / IEEE; Electron Devices Society et al. | 1997
- 159
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Single electron charging of Sn nanocrystals in thin SiO/sub 2/ film formed by low energy ion implantationNakajima, A. / Futatsugi, T. / Horiguchi, N. / Nakao, H. / Yokoyama, N. et al. | 1997
- 163
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Silicon double-island single-electron deviceFujiwara, A. / Takahashi, Y. / Yamazaki, K. / Namatsu, H. / Nagase, M. / Kurihara, K. / Murase, K. et al. | 1997
- 167
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Room temperature silicon single-electron quantum-dot transistor switchLei Zhuang, / Lingjie Guo, / Chou, S.Y. et al. | 1997
- 171
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Verify: key to the stable single-electron-memory operationIshii, T. / Yano, K. / Sano, T. / Mine, T. / Murai, F. / Seki, K. et al. | 1997
- 175
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Room temperature Nb/Nb oxide-based single-electron transistorsShirakashi, J.-I. / Matsumoto, K. / Miura, N. / Konagai, M. et al. | 1997
- 179
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PLED-planar localised electron devicesNakazato, K. / Piotrowicz, P.J.A. / Hasko, D.G. / Ahmed, H. / Itoh, K. et al. | 1997
- 185
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A 1/3" Progressive Scan 1280(H) X 960(V) FT-CCD for Digital Still Camera ApplicationsBosiers, J. / Boersma, Y. / Kleimann, A. / Verbugt, D. / IEEE; Electron Devices Society et al. | 1997
- 185
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A 1/3" progressive scan 1280(H)/spl times/960(V) FT-CCD for digital still camera applicationsBosiers, J.T. / Kleimann, A.C. / Verbugt, D.W. / Peek, H.L. / van der Sijde, A.G. et al. | 1997
- 189
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Frame transfer area array sensor with vertical antiblooming and novel readout for enhanced performanceKiik, M.J. / Flood, C.J. / Weale, G.P. / Gareth Ingram, S. et al. | 1997
- 193
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Characterization of surface- and buried-channel detection transistors for CCD on-chip amplifiersCenten, P.G. / Roks, E. et al. | 1997
- 197
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a-Si:H Schottky diode direct detection pixel for large area X-ray imagingAflatooni, K. / Nathan, A. / Hornsey, R. / Cunningham, I.A. / Chamberlain, S.G. et al. | 1997
- 201
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CMOS image sensors-recent advances and device scaling considerationsHon-Sum Philip Wong, et al. | 1997
- 205
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Noise performance of a color CMOS photogate image sensorBlanksby, A.J. / Loinaz, M.J. / Inglis, D.A. / Ackland, B.D. et al. | 1997
- 209
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TFA image sensors: from the one transistor cell to a locally adaptive high dynamic range sensorSchneider, B. / Fischer, H. / Benthien, S. / Keller, H. / Lule, T. / Rieve, P. / Sommer, M. / Schulte, J. / Bohm, M. et al. | 1997
- 215
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CMOS devices below 0.1 mu m: how high will performance go?Yuan Taur / Nowak, E.J. et al. | 1997
- 215
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CMOS devices below 0.1 /spl mu/m: how high will performance go?Yuan Taur, / Nowak, E.J. et al. | 1997
- 215
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CMOS Devices Below 0.1m: How High Will Performance Go?Taur, Y. / Nowak, E. / IEEE; Electron Devices Society et al. | 1997
- 219
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Subband structure engineering for performance enhancement of Si MOSFETsTakagi, S. / Koga, J. / Toriumi, A. et al. | 1997
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A 0.10 mu m gate length CMOS technology with 30 AA gate dielectric for 1.0 V-1.5 V applicationsRodder, M. / Hanratty, M. / Rogers, D. / Laaksonen, T. / Hu, J.C. / Murtaza, S. / Chao, C.P. / Hattangady, S. / Aur, S. / Amerasekera, A. et al. | 1997
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A 0.10 /spl mu/m gate length CMOS technology with 30 /spl Aring/ gate dielectric for 1.0 V-1.5 V applicationsRodder, M. / Hanratty, M. / Rogers, D. / Laaksonen, T. / Hu, J.C. / Murtaza, S. / Chao, C.-P. / Hattangady, S. / Aur, S. / Amerasekera, A. et al. | 1997
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A 0.10m Gate Length CMOS Technology with 30A Gate Dielectric for 1.0V-1.5V ApplicationsRodder, M. / Hanratty, M. / Rogers, D. / Laaksonen, T. / IEEE; Electron Devices Society et al. | 1997
- 227
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TED Control Technology for Suppression of Reverse Narrow Channel Effect in 0.1m MOS DevicesOno, A. / Ueno, R. / Sakai, I. / IEEE; Electron Devices Society et al. | 1997
- 227
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TED control technology for suppression of reverse narrow channel effect in 0.1 /spl mu/m MOS devicesOno, A. / Ueno, R. / Sakai, I. et al. | 1997
- 231
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Anomalous short channel effects in Indium implanted nMOSFETsBouillon, P. / Gwoziecki, R. / Skotnicki, T. et al. | 1997
- 235
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Increase of Parasitic Resistance of p MOSFETs Due to Nitrogen Atoms Incorporation into Silicon Substrate by N~2O-Oxynitride Gate Dielectrics ProcessTakayanagi-Takagi, M. / Yoshimura, H. / Toyoshima, Y. / IEEE; Electron Devices Society et al. | 1997
- 235
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Increase of parasitic resistance of p-MOSFETs due to nitrogen atoms incorporation into silicon substrate by N/sub 2/O-oxynitride gate dielectrics processTakayanagi-Takagi, M. / Yoshimura, H. / Toyoshima, Y. et al. | 1997
- 239
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Sub-10-ps gate delay by reducing the current crowding effect at an extensionHisamoto, D. / Umeda, K. / Ohnishi, K. / Yugami, J. / Ushiyama, M. / Shiba, T. et al. | 1997
- 245
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A novel BST storage capacitor node technology using platinum electrodes for Gbit DRAMsKhamankar, R.B. / Kressley, M.A. / Visokay, M.R. / Moise, T. / Xing, G. / Nemoto, S. / Fang, S.J. / Wilson, A.M. / Gaynor, J.F. / Hurd, T.Q. et al. | 1997
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Integration of (Ba,Sr)TiO~3 Capacitor with Platinum Electrodes Having SiO~2 SpacerLee, B. T. / Lee, K. H. / Hwang, C. S. / Kim, W. D. / IEEE; Electron Devices Society et al. | 1997
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Integration of (Ba,Sr)TiO/sub 3/ capacitor with platinum electrodes having SiO/sub 2/ spacerByoung Taek Lee, / Ki Hoon Lee, / Cheol Seong Hwang, / Wan Don Kim, / Hideki Horii, / Hyoun-Woo Kim, / Hag-Ju Cho, / Chang Seek Kang, / Ju Hyuck Chung, / Sang In Lee, et al. | 1997
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Effect of Bottom Electrode Materials on the Electrical and Reliability Characteristics of (Ba,Sr)TiO~3 CapacitorsSun, S. C. / Tsai, M. S. / IEEE; Electron Devices Society et al. | 1997
- 253
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The electrical and reliability effect of bottom electrode materials characteristics of (Ba,Sr)TiO/sub 3/ capacitorsSun, S.C. / Tsai, M.S. et al. | 1997
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Epitaxial (Ba,Sr)TiO~3 Capacitors with Extremely High Dielectric Constant for DRAM ApplicationsFukushima, N. / Abe, K. / Izuha, M. / Schimizu, T. / IEEE; Electron Devices Society et al. | 1997
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Epitaxial (Ba,Sr)TiO/sub 3/ capacitors with extremely high dielectric constant for DRAM applicationsFukushima, N. / Abe, K. / Izuha, M. / Schimizu, T. / Kawakubo, T. et al. | 1997
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Impact of time dependent dielectric breakdown and stress induced leakage current on the reliability of (Ba,Sr)TiO/sub 3/ thin film capacitors for Gbit-scale DRAMsYamamichi, S. / Park, D. / Hu, C. et al. | 1997
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Impact of Time Dependent Dielectric Breakdown and Stress Induced Leakage Current on the Reliability of (Ba,Sr)TiO~3, Thin Film Capacitors for Gbit-Scale DRAMsYamamichi, S. / Yamamichi, A. / Park, D. / Hu, C. / IEEE; Electron Devices Society et al. | 1997
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Single layer nitride capacitor dielectric film and high concentration doping technology for 1 Gb/4 Gb trench-type DRAMsSaida, S. / Sato, T. / Mizushima, I. / Ozawa, Y. / Tsunashima, Y. et al. | 1997
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A novel high-density 5F/sup 2/ NAND STI cell technology suitable for 256 Mbit and 1 Gbit flash memoriesShimizu, K. / Narita, K. / Kamiya, E. / Takeuchi, Y. / Yaegashi, T. / Aritome, S. / Watanabe, T. et al. | 1997
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A Novel High-Density 5F^2 NAND STI Cell Technology Suitable for 256Mbit and 1Gbit Flash MemoriesShimizu, K. / Narita, K. / Watanabe, H. / Kamiya, E. / IEEE; Electron Devices Society et al. | 1997
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A 0.24m^2 Cell Process with 0.18m Width Isolation and 3-D Interpoly Dielectric Films for 1-Gb Flash MemoriesKobayashi, T. / Matsuzaki, N. / Sato, A. / Katayama, A. / IEEE; Electron Devices Society et al. | 1997
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A 0.24-/spl mu/m/sup 2/ cell process with 0.18-/spl mu/m width isolation and 3-D interpoly dielectric films for 1-Gb flash memoriesKobayashi, T. / Sato, A. / Katayama, A. / Kurata, H. / Miura, A. / Mine, T. / Goto, Y. / Morimoto, T. / Kume, H. / Kure, T. et al. | 1997
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Secondary Electron flash-a high performance, low power flash technology for 0.35 /spl mu/m and belowBude, J.D. / Mastrapasqua, M. / Pinto, M.R. / Gregor, R.W. / Kelley, P.J. / Kohler, R.A. / Leung, C.W. / Ma, Y. / McPartland, R.J. / Roy, P.K. et al. | 1997
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Secondary Electron Flash-A High Performance, Low Power Flash Technology for 0.35m and BelowBude, J. / Mastrapasqua, M. / Pinto, M. / Gregor, R. / IEEE; Electron Devices Society et al. | 1997
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A triple polysilicon stacked flash memory cell with wordline self-boosting programmingJung Dal Choi, / Dong Gi Lee, / Dong Jun Kim, / Seong Soon Cho, / Hong Soo Kim, / Chul Ho Shin, / Sung Tae Ahn, et al. | 1997
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Novel self-convergent programming scheme for multi-level p-channel flash memoryShih-Jye Shen, / Ching-Song Yang, / Hsu, C.C.-H. / Chang, S.-D.T. / Rodjy, N. / Wang, A.C. et al. | 1997
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A novel isolation-scaling technology for NAND EEPROMs with the minimized program disturbanceSatoh, S. / Hagiwara, H. / Tanzawa, T. / Takeuchi, K. / Shirota, R. et al. | 1997
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Performance and reliability evaluations of p-channel flash memories with different programming schemesChung, S.S. / Kuo, S.N. / Yih, C.M. / Chao, T.S. et al. | 1997
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Device simulation for RF applicationsDutton, R.W. / Troyanovsky, B. / Yu, Z. / Arnborg, T. / Rotella, F. / Ma, G. / Sato-Iwanaga, J. et al. | 1997
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Device Simulation for RF ApplicationDutton, R. / Troyanovsky, B. / Yu, Z. / Arnborg, T. / IEEE; Electron Devices Society et al. | 1997
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Low noise FET design for wireless communicationsFranca-Neto, L.M. / Mao, E. / Harris, J.S. et al. | 1997
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RF MOSFET modeling accounting for distributed substrate and channel resistances with emphasis on the BSIM3v3 SPICE modelLiu, W. / Gharpurey, R. / Chang, M.C. / Erdogan, U. / Aggarwal, R. / Mattia, J.P. et al. | 1997
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R.F. MOSFET Modeling Accounting for Distributed Substrate and Channel Reistances with Emphasis on the BSIM3v3 SPICE ModelLiu, W. / Gharpurey, R. / Chang, M. C. / Erdogan, U. / IEEE; Electron Devices Society et al. | 1997
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Accurate drain conductance modeling for distortion analysis in MOSFETsvan Langevelde, R. / Klaassen, F.M. et al. | 1997
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RF Noise Modelling of 0.25m CMOS and Low Power LNAsVanoppen, R. / DeMaaijer, L. / Klaasen, D. / Tiemeijer, L. / IEEE; Electron Devices Society et al. | 1997
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RF noise modelling of 0.25 /spl mu/m CMOS and low power LNAsVanoppen, R.R.J. / de Maaijer, L.M.F. / Klaassen, D.B.M. / Tiemeijer, L.F. et al. | 1997
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A new approach to the physics-based noise analysis of semiconductor devices operating in large signal, (quasi) periodic regimeBonani, F. / Donati Guerrieri, S. / Ghione, G. / Pirola, M. et al. | 1997
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Experimental results and simulation of substrate noise coupling via planar spiral inductor in RF ICsPun, A. / Yeung, T. / Lau, J. / Clement, F.J.R. / Su, D. et al. | 1997
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Polymeric integrated circuits and light-emitting diodesde Leeuw, D.M. / Blom, P.W.M. / Hart, C.M. / Mutsaers, C.M.J. / Drury, C.J. / Matters, M. / Termeer, H. et al. | 1997
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Organic Polymer Devices and DisplaysDe Leeuw, D. M. / Blom, P. W. M. / Hart, C. M. / Mutsaers, C. M. J. / IEEE; Electron Devices Society et al. | 1997
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Neural microelectronicsOhmi, T. et al. | 1997
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Optical interconnect technologies for Si ULSIMiller, D.A.B. et al. | 1997
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A new concept for high voltage MCCT with no J-FET resistance by using a very thin waferIwamuro, N. / Iwaana, T. / Harada, Y. / Onozawa, Y. / Seki, Y. et al. | 1997
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Reverse channel floating base emitter switched thyristor (RFB-EST)Xu, S. / Constapel, R. / Silber, D. / Sin, J.K.O. et al. | 1997
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A trench lateral power MOSFET using self-aligned trench bottom contact holesFujishima, N. / Salama, C.A.T. et al. | 1997
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A 1 million-cell 2.0-m/spl Omega/ 30-V TrenchFET utilizing 32 Mcell/in/sup 2/ density with distributed voltage clampingWilliams, R.K. / Grabowski, W. / Darwish, M. / Chang, M. / Yilmaz, H. / Owyang, K. et al. | 1997
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A 1 Million Cell 2.0 m 30-V TrenchFET Utilizing 32 Mcell/in^2 Density with Distributed Voltage ClampingWilliams, R. K. / Grabowski, W. / Darwish, M. / Chang, M. / IEEE; Electron Devices Society et al. | 1997
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16-60V Rated LDMOS Show Advanced Performance in an 0.72m Evolution BiCMOS Power TechnologyTsai, C. Y. / Efland, T. / Pendharkar, S. / Mitros, J. / IEEE; Electron Devices Society et al. | 1997
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16-60 V rated LDMOS show advanced performance in a 0.72 /spl mu/m evolution BiCMOS power technologyTsai, C.-Y. / Efland, T. / Pendharkar, S. / Mitros, J. / Tessmer, A. / Smith, J. / Erdeljac, J. / Hutter, L. et al. | 1997
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Hot-carrier reliability in submicrometer LDMOS transistorsVersari, R. / Pieracci, A. / Manzini, S. / Contiero, C. / Ricco, B. et al. | 1997
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Lateral DMOS design for ESD robustnessDuvvury, C. / Carvajal, F. / Jones, C. / Briggs, D. et al. | 1997
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Edge and surface emitting quantum dot lasersBimberg, D. / Ledentsov, N.N. / Grundmann, M. / Heinrichsdorff, F. / Ustinov, V.M. / Alferov, Zh.I. / Lott, J.A. et al. | 1997
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DC, Modulation and Gain-Switched Characteristics of Self-Organized In~0~.~4Ga~0~.~6As/GaAs Quantum Dot Room Temperature LasersKlotzkin, D. / Kamath, K. / Jambunathan, R. / Bhattacharya, R. / IEEE; Electron Devices Society et al. | 1997
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DC, modulation, and gain-switched characteristics of self-organized In/sub 0.4/Ga/sub 0.6/As/GaAs quantum dot room temperature lasersKlotzkin, D. / Jambunathan, R. / Kamath, K. / Bhattacharya, P. et al. | 1997
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Electron leakage and the excess voltage at p-P heterojunctions in InGaAsP/InP lasersFlynn, E.J. / Ackerman, D.A. et al. | 1997
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Estimation of the /spl Gamma/-X crossover composition in disordered (Al/sub x/Ga/sub 1-x/)/sub 0.5/In/sub 0.5/P using n-i-n diodesMorrison, A.P. / Lambkin, J.D. / Valster, A. et al. | 1997
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Estimation of the -X Crossover Composition in Disordered (Al~xGa~1~-~x)~0~.~5In~0~.~5P Using n-i-n DiodesMorrison, A. / Lambkin, J. / Van der Poel, C. / Valster, A. / IEEE; Electron Devices Society et al. | 1997
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Short Wavelength Light Emitting Diodes in Al~0~.~4Ga~0~.~6P/GaP Quantum WellsGerhold, M. / Kamath, K. / Bhattacharya, P. / IEEE; Electron Devices Society et al. | 1997
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Short wavelength light emitting diodes in Al/sub 0.4/Ga/sub 0.6/P/GaP quantum wellsGerhold, M. / Kamath, K. / Bhattacharya, P. et al. | 1997
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220 K continuous-wave operation of AlGaAs/GaAs multi-quantum well vertical-cavity surface-emitting laser on Si substrateEgawa, T. / Nakanishi, N. / Jimbo, T. / Umeno, M. et al. | 1997
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SOI floating-body, device and circuit issuesGautier, J. / Pelella, M.M. / Fossum, J.G. et al. | 1997
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Design Methodology for Minimizing Hysteretic V~T-Variation in Partially-Depleted SOI CMOSWei, A. / Antoniadis, D. / IEEE; Electron Devices Society et al. | 1997
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Design methodology for minimizing hysteretic V/sub T/-variation in partially-depleted SOI CMOSWei, A. / Antoniadis, D.A. et al. | 1997
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A 7.9/5.5 psec room/low temperature SOI CMOSAssaderaghi, F. / Rausch, W. / Ajmera, A. / Leobandung, E. / Schepis, D. / Wagner, L. / Wann, H.-J. / Bolam, R. / Yee, D. / Davari, B. et al. | 1997
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A compact Schottky body contact technology for SOI transistorsSleight, J. / Mistry, K. et al. | 1997
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Fmax enhancement of dynamic threshold-voltage MOSFET (DTMOS) under ultra-low supply voltageTanaka, T. / Momiyama, Y. / Sugii, T. et al. | 1997
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Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channelWong, H.-S.P. / Chan, K.K. / Taur, Y. et al. | 1997
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Process charging in ULSI: mechanisms, impact and solutionsMcVittie, J.P. et al. | 1997
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Impact of plasma-charging damage polarity on MOSFET noiseCheung, K.P. / Martin, S. / Misra, D. / Steiner, K. / Colonell, J.I. / Chang, C.P. / Lai, W.Y.C. / Liu, C.T. / Liu, R. / Pai, C.S. et al. | 1997
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Reliability of thin gate oxide under plasma charging caused by antenna topography-dependent electron shading effectNoguchi, K. / Tokashiki, K. / Horiuchi, T. / Miyamoto, H. et al. | 1997
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Assessment of charge-induced damage to ultra-thin gate MOSFETsKrishnan, S. / Rangan, S. / Hattangady, S. / Xing, G. / Brennan, K. / Rodder, M. / Ashok, S. et al. | 1997
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Degradation of deep sub-micron isolation by vacuum ultraviolet radiation from low temperature back end plasma-assisted processesAshburn, S.P. / Krishnan, S. / Dixit, G.A. / Taylor, K. / Breedijk, T. / Chen, I.-C. / Goodwin, M.W. / Esquivel, A.L. et al. | 1997
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A study of hot-carrier degradation in n- and p-MOSFETs with ultra-thin gate oxides in the direct-tunneling regimeMomose, H.S. / Nakamura, S.-I. / Ohguro, T. / Yoshitomi, T. / Morifuji, E. / Morimoto, T. / Katsumata, Y. / Iwai, H. et al. | 1997
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A comparison of TiN processes for CVD W/TiN gate electrode on 3 nm gate oxideYang, H. / Brown, G.A. / Hu, J.C. / Lu, J.P. / Kraft, R. / Rotondaro, A.L.P. / Hattangady, S.V. / Chen, I.-C. / Luttmer, J.D. / Chapman, R.A. et al. | 1997
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Ultra thin (<3 nm) high quality nitride/oxide stack gate dielectrics fabricated by in-situ rapid thermal processingKim, B.Y. / Luan, H.F. / Kwong, D.L. et al. | 1997
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Boron-enhanced-diffusion of boron: The limiting factor for ultra-shallow junctionsAgarwal, A. / Eaglesham, D.J. / Gossmann, H.-J. / Pelaz, L. / Herner, S.B. / Jacobson, D.C. / Haynes, T.E. / Erokhin, Y. / Simonton, R. et al. | 1997
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A High Performance 50 nm PMOSFET using Decaborane (B~1~0H~1~4) Ion Implantation and 2-Step Activation Annealing ProcessGoto, K. / Matsuo, J. / Tada, Y. / Tanaka, T. / IEEE; Electron Devices Society et al. | 1997
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A high performance 50 nm PMOSFET using decaborane (B/sub 10/H/sub 14/) ion implantation and 2-step activation annealing processGoto, K.-I. / Matsuo, J. / Tada, Y. / Tanaka, T. / Momiyama, Y. / Sugii, T. / Yamada, I. et al. | 1997
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Shallow source/drain extensions for pMOSFETs with high activation and low process damage fabricated by plasma dopingTakase, M. / Yamashita, K. / Hori, A. / Mizuno, B. et al. | 1997
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A Raised Source/Drain Technology Using In-situ P-doped SiGe and B-doped Si for 0.1-m CMOS ULSIsUchino, T. / Shiba, T. / Ohnishi, K. / Miyauchi, A. / IEEE; Electron Devices Society et al. | 1997
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A raised source/drain technology using in-situ P-doped SiGe and B-doped Si for 0.1-/spl mu/m CMOS ULSIsUchino, T. / Shiba, T. / Ohnishi, K. / Miyauchi, A. / Nakata, M. / Inoue, Y. / Suzuki, T. et al. | 1997
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Practical Application of 2-D Optical Proximity Corrections for Enhanced Performance of 0.25 m Random Logic DevicesChuang, H. / Gilbert, P. / Grobmann, W. / Kling, M. / IEEE; Electron Devices Society et al. | 1997
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Practical applications of 2-D optical proximity corrections for enhanced performance of 0.25 /spl mu/m random logic devicesChuang, H. / Gilbert, P. / Grobman, W. / Kling, M. / Lucas, K. / Reich, K. / Roman, B. / Travis, E. / Tsui, P. / Vuong, T. et al. | 1997
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Modeling of ultra-low energy boron implantation in siliconHobler, G. / Vuong, H.-H. / Bevk, J. / Agarwal, A. / Gossmann, H.-J. / Jacobson, D.C. / Foad, M. / Murrell, A. / Erokhin, Y. et al. | 1997
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A physics-based modeling approach for the simulation of anomalous boron diffusion and clustering behaviorsLilak, A.D. / Earles, S.K. / Jones, K.S. / Law, M.E. / Giles, M.D. et al. | 1997
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Experiments and modeling of boron segregation in As implanted Si during annealingChang, R.D. / Choi, P.S. / Wristers, D. / Kwong, D.L. et al. | 1997
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Damage Calibration Concept and Novel B Cluster Reaction Model for B Transient Enhanced Diffusion over Thermal Process Range from 600C (839 h) to 1100C (5 s) with Various Ion Implantation Doses and EnergiesSuzuki, K. / Miyashita, T. / Tada, Y. / Hoefler, A. / IEEE; Electron Devices Society et al. | 1997
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Damage calibration concept and novel B cluster reaction model for B transient enhanced diffusion over thermal process range from 600/spl deg/C (839 h) to 1100/spl deg/C (5 s) with various ion implantation doses and energiesSuzuki, K. / Miyashita, T. / Tada, Y. / Hoefler, A. / Strecker, N. / Fichtner, W. et al. | 1997
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A new clustering model for runaway boron pile-up effectOrlowski, M. et al. | 1997
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Simulation of Transient Enhanced Diffusion Using Computantionally Efficient ModelsYu, S. / Kennel, H. / Giles, M. / Packan, P. / IEEE; Electron Devices Society et al. | 1997
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Simulation of transient enhanced diffusion using computationally efficient modelsYu, S.S. / Kennel, H.W. / Giles, M.D. / Packan, P.A. et al. | 1997
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A simple polysilicon TFT technology for display systems on glassSin, K.O. et al. | 1997
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Suppressed Short-Channel Effects and Improved Stability in Polysilicon Thin Film Transistors with Very Thin ECR N~2O-Plasma Gate OxideLee, J. W. / Lee, N. I. / Hur, S. H. / Han, C. H. / IEEE; Electron Devices Society et al. | 1997
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Suppressed short-channel effects and improved stability in polysilicon thin film transistors with very thin ECR N/sub 2/O-plasma gate oxideJin-Woo Lee, / Nae-In Lee, / Sung-Hoi Hur, / Chul-Hi Han, et al. | 1997
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A novel self-aligned gate-overlapped LDD poly-Si TFT with high reliability and performanceHatano, M. / Akimoto, H. / Sakai, T. et al. | 1997
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Analysis of threshold voltage shift caused by bias stress in low temperature poly-Si TFTsInoue, S. / Ohshima, H. / Shimoda, T. et al. | 1997
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Advances in amorphous silicon technology for LCDsTsukada, T. et al. | 1997
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Thin film transistors for foldable displaysMa, E.Y. / Theiss, S.D. / Lu, M.H. / Wu, C.C. / Wagner, S. et al. | 1997
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Pentacene thin film transistors and inverter circuitsKlauk, H. / Yen-Yi Lin, / Gundlach, D.J. / Jackson, T.N. et al. | 1997
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Oxide based compound semiconductor electronicsMishra, U.K. / Parikh, P. / Chavarkar, P. / Yen, J. / Champlain, J. / Thibeault, B. / Reese, H. / Song Stone Shi, / Hu, E. / Lijie Zhu, et al. | 1997
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Dual material gate field effect transistor (DMGFET)Wei Long, / Chin, K.K. et al. | 1997
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On-state breakdown in power HEMTs: measurements and modelingSomerville, M.H. / Blanchard, R. / del Alamo, J.A. / Duh, G. / Chao, P.C. et al. | 1997
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On-State Breakdown in High-Power HEMTs: Measurements and ModelingSomerville, M. / Blanchard, R. / Del Alamo, J. / Duh, G. / IEEE; Electron Devices Society et al. | 1997
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A GaAs power FET with zero-temperature-coefficientTanaka, T. / Furukawa, H. / Ueda, D. et al. | 1997
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High performance 0.25 /spl mu/m gate-length doped-channel AlGaN/GaN heterostructure field effect transistors grown on p-type SiC substratesPing, A.T. / Chen, Q. / Yang, J.W. / Asif Khan, M. / Adesida, I. et al. | 1997
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High-Performance 0.25 m Gate-Length Doped-Channel AlGaN/GaN Heterostructure Field Effect Transistors Grown on p-Type SiC SubstratesPing, A. T. / Chen, Q. / Yang, J. W. / Khan, M. A. / IEEE; Electron Devices Society et al. | 1997
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Novel high power AlGaN/GaN HFETs on SiC substratesGaska, R. / Yang, J. / Osinsky, A. / Asif Khan, M. / Shur, M.S. et al. | 1997
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High performance and large area flip-chip bonded AlGaN/GaN MODFETsThibeault, B.J. / Keller, B.P. / Fini, P. / Mishra, U.K. / Nguyen, C. / Nguyen, N.X. / Le, M. et al. | 1997
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1 Giga bit SOI DRAM with fully bulk compatible process and body-contacted SOI MOSFET structureYo-Hwan Koh, / Min-Rok Oh, / Jong-Wook Lee, / Ji-Woon Yang, / Won-Chang Lee, / Chan-Kwang Park, / Jae-Beom Park, / Yeon-Cheol Heo, / Kwang-Myung Rho, / Byung-Cheol Lee, et al. | 1997
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A 2.0 V, 0.35 /spl mu/m partially depleted SOI-CMOS technologyMistry, K. / Grula, G. / Sleight, J. / Stephany, R. / Flatley, R. / Skerry, P. et al. | 1997
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A. 2.0V, 0.35m Partially Depleted SOI-CMOS TechnologyMistry, K. / Grula, G. / Sleight, J. / Bair, L. / IEEE; Electron Devices Society et al. | 1997
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A 0.25 /spl mu/m CMOS SOI technology and its application to 4 Mb SRAMSchepis, D.J. / Assaderaghi, F. / Yee, D.S. / Rausch, W. / Ajmera, A.C. / Leobandung, E. / Flaker, R. / Sadana, D. / Hovel, H.J. / Kebede, T. et al. | 1997
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A 0.25m CMOS SOI Technology and its Application to 4 Mb SRAMSchepis, D. / Assaderaghi, F. / Yee, D. / Rausch, W. / IEEE; Electron Devices Society et al. | 1997
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Scalability of partially depleted SOI technology for sub-0.25 /spl mu/m logic applicationsChau, R. / Arghavani, R. / Alavi, M. / Douglas, D. / Green, R. / Tyagi, S. / Xu, J. / Packan, P. / Yu, S. / Chunlin Liang, et al. | 1997
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Scalability of Partially Deplected SOI Technology for Sub-0.25m Logic ApplicationsChau, R. / Alavi, M. / Arghavani, R. / Douglas, D. / IEEE; Electron Devices Society et al. | 1997
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Highly-reliable ferroelectric memory technology with bismuth-layer structured thin films (Y-1 family)Fujii, E. / Otsuki, T. / Judai, Y. / Shimada, Y. / Azuma, M. / Uemoto, Y. / Nagano, Y. / Nasu, T. / Izutsu, Y. / Matsuda, A. et al. | 1997
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Preparation of SrBi/sub 2/Ta/sub 2/O/sub 9/ thin films with ultra-high resistance to annealing in hydrogen atmosphere for ferroelectric memoriesKanehara, T. / Koiwa, I. / Okada, Y. / Ashikaga, K. / Katoh, H. / Kaifu, K. et al. | 1997
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Preparation of SrBi~2Ta~O~9 Thin Films with Ultra-High Resistance to Annealing in Hydrogen Atmosphere for Ferroelectric MemoriesKanehara, T. / Koiwa, I. / Okada, Y. / Ashikaga, K. / IEEE; Electron Devices Society et al. | 1997
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Crystal-Orientation Controlled PZT FeRAM-Capacitors Using RF Magnetron Sputtering with 12" cap phi Single TargetInoue, N. / Maejima, Y. / Hayashi, Y. / IEEE; Electron Devices Society et al. | 1997
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Crystal-orientation controlled PZT FeRAM-capacitors using RF magnetron sputtering with 12"/spl phi/ single targetInoue, N. / Maejima, Y. / Hayashi, Y. et al. | 1997
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A high stability electrode technology for stacked SrBi/sub 2/Ta/sub 2/O/sub 9/ capacitors applicable to advanced ferroelectric memoryKudo, J. / Ito, Y. / Mitarai, S. / Ogata, N. / Yamazaki, S. / Urashima, H. / Okutoh, A. / Nagata, M. / Ishihara, K. et al. | 1997
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A High Stability Electrode Technology for Stacked SrBi~2Ta~2O~9 Capacitors Applicable to Advanced Ferroelectric MemoryKudo, J. / Ito, Y. / Mitarai, S. / Ogata, N. / IEEE; Electron Devices Society et al. | 1997
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Advanced 0.5m FRAM Device Technology with Fully Compatibility of Half-Micron CMOS Logic DeviceYamazaki, T. / Inoue, K. I. / Miyazawa, H. / Nakamura, M. / IEEE; Electron Devices Society et al. | 1997
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Advanced 0.5 /spl mu/m FRAM device technology with full compatibility of half-micron CMOS logic deviceYamazaki, T. / Inoue, K.-i. / Miyazawa, H. / Nakamura, M. / Sashida, N. / Satomi, R. / Kerry, A. / Katoh, Y. / Noshiro, H. / Takai, K. et al. | 1997
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Ultra-Thin EBL (Encapsulating Barrier Layer) for Ferroelectric CapacitorPark, I. S. / Kim, Y. K. / Lee, S. M. / Chung, J. H. / IEEE; Electron Devices Society et al. | 1997
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Ultra-thin EBL (encapsulated barrier layer) for ferroelectric capacitorIn Seon park, / Yeong Kwan Kim, / Sang Min Lee, / Ju Hyuck Chung, / Sang Bom Kang, / Chang Soo Park, / Cha Young Yoo, / Sang In Lee, / Moon Yong Lee, et al. | 1997
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SrBi~2Ta~2O~9 Thin Film Capacitor Model Including Polarization Reversal Response for Nanosecond Range Circuit Simulation of Ferroelectric Nonvolatile MemoryTakeo, M. / Azuma, M. / Hirano, H. / Asari, K. / IEEE; Electron Devices Society et al. | 1997
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SrBi/sub 2/TaO/sub 9/ thin film capacitor model including polarization reversal response for nanosecond range circuit simulation of ferroelectric nonvolatile memoryTakeo, M. / Azuma, M. / Hirano, H. / Asari, K. / Moriwaki, N. / Otsuki, T. / Tatsuuma, K. et al. | 1997
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Flat-band voltage shifts in p-MOS devices caused by carrier activation in p/sup +/-polycrystalline silicon and boron penetrationAoyama, T. / Suzuki, K. / Tashiro, H. / Tada, Y. / Arimoto, H. et al. | 1997
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Flat-Band Voltage Shifts in P-MOS Devices Caused by Carrier Activation in P^+-Polycrystalline Silicon and Boron PenetrationAoyama, T. / Suzuki, K. / Tashiro, H. / Tada, Y. / IEEE; Electron Devices Society et al. | 1997
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Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistorsTuinhout, H.P. / Montree, A.H. / Schmitz, J. / Stolk, P.A. et al. | 1997
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Gate Electrode Microstructure Having Stacked Large-Grain Poly-Si with Ultra-Thin SiO~x Interlayer for Reliability in Sub-Micrometer CMOSIto, H. / Sasaki, M. / Kimizuka, N. / Uwasawa, K. / IEEE; Electron Devices Society et al. | 1997
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Gate electrode microstructure having stacked large-grain poly-Si with ultra-thin SiO/sub x/ interlayer for reliability in sub-micrometer CMOSIto, H. / Sasaki, M. / Kimizuka, N. / Uwasawa, K. / Ito, T. / Goto, Y. / Tsuboi, A. / Watanuki, S. / Ueda, T. / Horiuchi, T. et al. | 1997
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Performance and reliability assessment of dual-gate CMOS devices with gate oxide grown on nitrogen implanted Si substratesChen, Y.Y. / Liu, I.M. / Gardner, M. / Fulford, J. / Kwong, D.L. et al. | 1997
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Electrical characteristics and reliability of sub-3 nm gate oxides grown on nitrogen implanted silicon substratesCrowder, S. / Hargrove, M. / Wu, E. / Lo, S.H. / Guarin, F. / Crabbe, E. / Su, L. et al. | 1997
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Application of JVD nitride gate dielectric to a 0.35 micron CMOS process for reduction of gate leakage current and boron penetrationTseng, H.-H. / Tsui, P.G.Y. / Tobin, P.J. / Mogab, J. / Khare, M. / Wang, X.W. / Ma, T.P. / Hegde, R. / Hobbs, C. / Veteran, J. et al. | 1997
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High Performance 20 NO Oxynitride for Gate Dielectric in Deep Sub-Quarter Micron CMOS TechnologyMaiti, B. / Tobin, P. / Misra, V. / Hegde, R. / IEEE; Electron Devices Society et al. | 1997
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High performance 20 /spl Aring/ NO oxynitride for gate dielectric in deep subquarter micron CMOS technologyMaiti, B. / Tobin, P.J. / Misra, V. / Hegde, R.I. / Reid, K.G. / Gelatos, C. et al. | 1997
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A Shallow Trench Isolation for Sub-0,13m CMOS TechnologiesNandakumar, N. / Sridhar, S. / Nag, S. / Mei, P. / IEEE; Electron Devices Society et al. | 1997
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A shallow trench isolation for sub-0.13 /spl mu/m CMOS technologiesNandakumar, M. / Sridhar, S. / Nag, S. / Mei, P. / Rogers, D. / Hanratty, M. / Amerasekera, A. / Chen, I.-C. et al. | 1997
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A Highly Manufacturable Corner Rounding Solution for 0.18m Shallow Trench IsolationChang, C. P. / Pai, C. S. / Baumann, F. H. / Liu, C. T. / IEEE; Electron Devices Society et al. | 1997
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A highly manufacturable corner rounding solution for 0.18 /spl mu/m shallow trench isolationChang, C.P. / Pai, C.S. / Baumann, F.H. / Liu, C.T. / Rafferty, C.S. / Pinto, M.R. / Lloyd, E.J. / Bude, M. / Klemens, F.P. / Miner, J.F. et al. | 1997
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Corner field effect of the CMP oxide recess in shallow trench isolation technology for high density flash memoriesShum, D.P. / Higman, J.M. / Khazhinsky, M.G. / Wu, K.Y. / Soolin Kao, / Burnett, J.D. / Swift, C.T. et al. | 1997
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Stress minimization in deep sub-micron full CMOS devices by using an optimized combination of the trench filling CVD oxidesPark, M.H. / Hong, S.H. / Hong, S.J. / Park, T. / Song, S. / Park, J.H. / Kim, H.S. / Shin, Y.G. / Kang, H.K. / Lee, M.Y. et al. | 1997
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Highly reliable double well in thin p/sup -/ on p/sup +/ epitaxial wafer for logic-embedded DRAMYamashita, T. / Komori, S. / Horita, K. / Kawasaki, Y. / Inoue, Y. / Nishimura, T. et al. | 1997
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Highly Reliable Double Well in Thin-p on p^+ Epitaxial Wafer for Logic Embedded DRAMYamashita, T. / Komori, S. / Horita, K. / Kawasaki, Y. / IEEE; Electron Devices Society et al. | 1997
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Suppression of reverse short channel effect by high energy implantationChaudhrya, S. / Rafferty, C.S. / Nagy, W.J. / Chyan, Y.F. / Carroll, M.S. / Chen, A.S. / Lee, K.H. et al. | 1997
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Suppression of Reverse and Short Channel Effect by High Energy ImplantationChaudhry, S. / Rafferty, C. / Nagy, W. / Chyan, Y. / IEEE; Electron Devices Society et al. | 1997
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Inverse modeling of MOSFETs using I-V characteristics in the subthreshold regionLee, Z.K. / McIlrath, M.B. / Antoniadis, D.A. et al. | 1997
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An advanced MOSFET design approach and a calibration methodology using inverse modeling that accurately predicts device characteristicsDas, A. / Newmark, D. / Clejan, I. / Foisy, M. / Sharma, M. / Venkatesan, S. / Veeraraghavan, S. / Misra, V. / Gadepally, B. / Parrillo, L. et al. | 1997
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Junction Delineation of 0.15m MOS Devices Using Scanning Capacitance MicroscopyKleiman, R. N. / O'Malley, M. L. / Baumann, F. H. / Garno, J. P. / IEEE; Electron Devices Society et al. | 1997
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-
Junction delineation of 0.15 /spl mu/m MOS devices using scanning capacitance microscopyKleiman, R.N. / O'Malley, M.L. / Baumann, F.H. / Garno, J.P. / Timp, G.L. et al. | 1997
- 695
-
Impact of nitrogen implant prior to the gate oxide growth on transient enhanced diffusionKamgar, A. / Vuong, H.-H. / Liu, C.T. / Rafferty, C.S. / Clemens, J.T. et al. | 1997
- 699
-
Diffusion Mechanism Study of Arsenic in SiO~2, Using Oxygen Isotope ^1^8O as a Component Element of Matrix SiO~2Tsunashima, Y. / Aoki, N. / IEEE; Electron Devices Society et al. | 1997
- 699
-
Diffusion mechanism study of arsenic in SiO/sub 2/ using oxygen isotope /sup 18/O as a component element of matrix SiO/sub 2/Tsunashima, Y. / Aoki, N. et al. | 1997
- 703
-
Oxygen Vacancy with Large Lattice Distortion as Origin of Leakage Currents in SiO~2Yokozawa, A. / Oshiyama, A. / Miyamoto, Y. / Kumashiro, S. / IEEE; Electron Devices Society et al. | 1997
- 703
-
Oxygen vacancy with large lattice distortion as an origin of leakage currents in SiO/sub 2/Yokozawa, A. / Oshiyama, A. / Miyamoto, Y. / Kumashiro, S. et al. | 1997
- 709
-
A novel vertical current limiter fabricated with a deep trench forming technology for highly reliable field emitter arraysTakemura, H. / Tomihari, Y. / Furutake, N. / Matsuno, F. / Yoshiki, M. / Takada, N. / Okamoto, A. / Miyano, S. et al. | 1997
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-
Enhanced Electron Emission and Its Stability from Gates Mo-Polycide Field EmittersUh, H. S. / Park, B. G. / Lee, J. D. / IEEE; Electron Devices Society et al. | 1997
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-
Enhanced electron emission and its stability from gated Mo-polycide field emittersHyung Soo Uh, / Byung Gook Park, / Jong Duk Lee, et al. | 1997
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-
Uniform, stable and high integrated field emitter arrays for high performance displays and vacuum microelectronic switching devicesNakamoto, M. / Hasegawa, T. / Fukuda, K. et al. | 1997
- 721
-
Electron gun design for traveling wave tubes (TWTs) using a field emitter array (FEA) cathodeImura, H. / Tsuida, S. / Takahasi, M. / Okamoto, A. / Makishima, H. / Miyano, S. et al. | 1997
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-
Electron Gun Design for Traveling Wave Tubes (TWTs) Using a Field Emitter Array (FEA) CathodesImura, H. / Tsuida, S. / Takahashi, M. / Okamoto, A. / IEEE; Electron Devices Society et al. | 1997
- 725
-
Increased emission current from MIM cathodes through the use of a multilayer top electrodeKusunoki, T. / Suzuki, M. et al. | 1997
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-
Non-thermionic cathodes-solid state electron emitters based on GaN and LaB/sub 6/Akinwande, A.I. / Horning, R.D. / Ruden, P.P. / Arch, D.K. / Johnson, B.R. / Heil, B.G. / King, J.M. et al. | 1997
- 729
-
Non-Thermionic Cathodes-Solid State Electron Emitters Based on GaN and LAB~6Akinwande, A. / Horning, R. / Ruden, P. / Arch, D. / IEEE; Electron Devices Society et al. | 1997
- 733
-
Sputtered thin film boron nitride cold emitters on metal substratesPryor, E.W. / Lihua Li, / Busta, H.H. et al. | 1997
- 739
-
InGaP/GaAs HBT's with high-speed and low-current operation fabricated using WSi/Ti as the base electrode and burying SiO/sub 2/ in the extrinsic collectorOka, T. / Hirata, K. / Ouchi, L.K. / Uchiyama, H. / Mochizuki, K. / Nakamura, T. et al. | 1997
- 739
-
InGaP/GaAs HBTs with High-Speed and Low-Current Operation Fabricated Using WSi/Ti as the Base Electrode and Burying SiO~2 in the Extrinsic CollectorOka, T. / Hirata, K. / Ouchi, K. / Uchiyama, H. / IEEE; Electron Devices Society et al. | 1997
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-
A 50 GHz feedback amplifier with AlInAs/GaInAs transferred-substrate HBTAgarwal, B. / Lee, Q. / Pullela, R. / Guthrie, J. / Samoska, L. / Rodwell, M.J.W. et al. | 1997
- 747
-
Novel InP/InGaAs D-HBTs with selective multisteps MOCVD regrowth techniques for high-speed applicationNomura, T. / Ohkubo, M. / Sekiguchi, T. / Ninomiya, T. et al. | 1997
- 751
-
High-speed, low-power InSb transistorsAshley, T. / Dean, A.B. / Elliott, C.T. / Jefferies, R. / Khaleque, F. / Phillips, T.J. et al. | 1997
- 755
-
Unipolar complementary bistable memories using gate-controlled negative differential resistance in a 2D-2D quantum tunneling transistorSimmons, J.A. / Blount, M.A. / Moon, J.S. / Baca, W.E. / Reno, J.L. / Hafich, M.J. et al. | 1997
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-
Low-frequency noise and performance of GaN p-n junction photodetectorsKuksenkov, D.V. / Temkin, H. / Osinsky, A. / Gaska, R. / Khan, M.A. et al. | 1997
- 765
-
Process technologies for advanced metallization and interconnect systemsSun, S.C. et al. | 1997
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A high performance 1.8 V, 0.20 /spl mu/m CMOS technology with copper metallizationVenkatesan, S. / Gelatos, A.V. / Smith, B. / Islam, R. / Cope, J. / Wilson, B. / Tuttle, D. / Cardwell, R. / Anderson, S. / Angyal, M. et al. | 1997
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-
A High Performance 1.8 V, 0.2m CMOS Technology with Copper MetallizationVenkatesan, S. / Gelatos, A. V. / Misra, V. / Islam, R. / IEEE; Electron Devices Society et al. | 1997
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-
Full Copper Wiring in a sub-0.25m CMOS ULSI TechnologyEdelstein, D. / Heindenrich, J. / Goldblatt, R. / Cote, W. / IEEE; Electron Devices Society et al. | 1997
- 773
-
Full copper wiring in a sub-0.25 mu m CMOS ULSI technologyEdelstein, D. / Heidenreich, J. / Goldblatt, R. / Cote, W. / Uzoh, C. / Lustig, N. / Roper, P. / McDevitt, T. / Motsiff, W. / Simon, A. et al. | 1997
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-
Full copper wiring in a sub-0.25 /spl mu/m CMOS ULSI technologyEdelstein, D. / Heidenreich, J. / Goldblatt, R. / Cote, W. / Uzoh, C. / Lustig, N. / Roper, P. / McDevitt, T. / Motsiff, W. / Simon, A. et al. | 1997
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A degradation-free Cu/HSQ damascene technology using metal mask patterning and post-CMP cleaning by electrolytic ionized waterAoki, H. / Yamasaki, S. / Usami, T. / Tsuchiya, Y. / Ito, N. / Onodera, T. / Hayashi, Y. / Ueno, K. / Gomi, H. / Aoto, N. et al. | 1997
- 781
-
Dual-Damascene Interconnects with 0.28m Vias Using In-Situ Copper Doped Aluminum Chemical Vapor DepositionSugai, K. / Chikaki, S. I. / Nakajima, T. / Kikkawa, T. / IEEE; Electron Devices Society et al. | 1997
- 781
-
Dual-damascene interconnects with 0.28 /spl mu/m vias using in situ copper doped aluminum chemical vapor depositionSugai, K. / Chikaki, S. / Nakajima, T. / Kikkawa, T. et al. | 1997
- 785
-
A highly reliable self-planarizing low-k intermetal dielectric for sub-quarter micron interconnectsMatsuura, M. / Tottori, I. / Goto, K. / Maekawa, K. / Mashiko, Y. / Hirayama, M. et al. | 1997
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130-GHz f/sub T/ SiGe HBT technologyOda, K. / Ohue, E. / Tanabe, M. / Shimamotot, H. / Onai, T. / Washio, K. et al. | 1997
- 791
-
130-GHz f~T SiGe HBT TechnologyOda, K. / Ohue, E. / Tanabe, M. / Shimamoto, H. / IEEE; Electron Devices Society et al. | 1997
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-
A selective-epitaxial SiGe HBT with SMI electrodes featuring 9.3-ps ECL-gate delayWashio, K. / Ohue, E. / Tanabe, M. / Shimamoto, H. / Onai, T. et al. | 1997
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-
Large-Signal Performance of High-CEOBV Graded Epi-Base SiGe HBTs at Wireless FrequenciesGreenberg, D. / River, M. / Girard, P. / Bergeault, E. / IEEE; Electron Devices Society et al. | 1997
- 799
-
Large-signal performance of high-BV/sub CEO/ graded epi-base SiGe HBTs at wireless frequenciesGreenberg, D.R. / Rivier, M. / Girard, P. / Bergeault, E. / Moniz, J. / Ahlgren, D. / Freeman, G. / Subbanna, S. / Jeng, S.J. / Stein, K. et al. | 1997
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-
The effect of carbon incorporation on SiGe heterobipolar transistor performance and process marginOsten, H.J. / Lippert, G. / Knoll, D. / Barth, R. / Heinemann, B. / Rucker, H. / Schley, P. et al. | 1997
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-
A. 54GHz fmax Implanted Base 0.35m Single-Polysilicon Bipolar TechnologyNiel, S. / Rozeau, O. / Ailloud, L. / Hernandez, C. / IEEE; Electron Devices Society et al. | 1997
- 807
-
A 54 GHz f/sub max/ implanted base 0.35 /spl mu/m single-polysilicon bipolar technologyNiel, S. / Rozeau, O. / Ailloud, L. / Hernandez, C. / Llinares, P. / Kirtsch, J. / Monroy, A. / de Pontcharra, J. / Auvert, G. / Blanchard, B. et al. | 1997
- 811
-
Simulation, fabrication and characterization of high performance planar-doped-barrier sub 100 nm channel MOSFETsRamgopal Rao, V. / Hansch, W. / Eisele, I. et al. | 1997
- 815
-
Hole confinement and its impact on low-frequency noise in SiGe pFETs on sapphireMathew, S.J. / Niu, G. / Dubbelday, W.B. / Cressler, J.D. / Ott, J.A. / Chu, J.O. / Mooney, P.M. / Kavanagh, K.L. / Meyerson, B.S. / Lagnado, I. et al. | 1997
- 821
-
Sub-100 nm gate length metal gate NMOS transistors fabricated by a replacement gate processChatterjee, A. / Chapman, R.A. / Dixit, G. / Kuehne, J. / Hattangady, S. / Yang, H. / Brown, G.A. / Aggarwal, R. / Erdogan, U. / He, Q. et al. | 1997
- 825
-
Feasibility of using W/TiN as metal gate for conventional 0.13 mu m CMOS technology and beyondHu, J.C. / Yang, H. / Kraft, R. / Rotondaro, A.L.P. / Hattangady, S. / Lee, W.W. / Chapman, R.A. / Chao, C.P. / Chatterjee, A. / Hanratty, M. et al. | 1997
- 825
-
Feasibility of using W/TiN as metal gate for conventional 0.13 /spl mu/m CMOS technology and beyondHu, J.C. / Yang, H. / Kraft, R. / Rotondaro, A.L.P. / Hattangady, S. / Lee, W.W. / Chapman, R.A. / Chao, C.-P. / Chatterjee, A. / Hanratty, M. et al. | 1997
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-
Feasibility of Using W/TiN as Metal-Gate for Conventional 0.13m CMOS Techology and BeyondHu, J. C. / Yang, H. / Kraft, R. / Rotondaro, A. / IEEE; Electron Devices Society et al. | 1997
- 829
-
Gate-workfunction engineering using poly-(Si,Ge) for high-performance 0.18 /spl mu/m CMOS technologyPonomarev, Y.V. / Salm, C. / Schmitz, J. / Woerlee, P.H. / Stolk, P.A. / Gravesteijn, D.J. et al. | 1997
- 829
-
Gate-Workfunction Engineering Using Poly-(Si,Ge) for High-Performance O.181m CMOS TechnologyPonomarev, Y. / Salm, C. / Schmitz, J. / Woerlee, P. / IEEE; Electron Devices Society et al. | 1997
- 833
-
Single Gate 0.15m CMOS Devices Fabricated Using RTCVD In-Situ Boron Doped Si~1~-~xGe~x GatesLi, V. Z.-Q. / Mirabedini, M. / Kuehn, R. / Wortman, J. / IEEE; Electron Devices Society et al. | 1997
- 833
-
Single gate 0.15 mu m CMOS devices fabricated using RTCVD in-situ boron doped Si1-xGex gatesLi, V.Z.Q. / Mirabedini, M.R. / Kuehn, R.T. / Wortman, J.J. / Öztürk, M.C. et al. | 1997
- 833
-
Single gate 0.15 /spl mu/m CMOS devices fabricated using RTCVD in-situ boron doped Si/sub 1-x/Ge/sub x/ gatesLi, V.Z.-Q. / Mirabedini, M.R. / Kuehn, R.T. / Wortman, J.J. / Ozturk, M.C. et al. | 1997
- 837
-
0.18 mu m low voltage/low power RF CMOS with zero Vth analog MOSFETs made by undoped epitaxial channel techniqueOhguro, T. / Naruse, H. / Sugaya, H. / Morifuji, E. / Nakamura, S. / Yoshitomi, T. / Morimoto, T. / Momose, H.S. / Katsumata, Y. / Iwai, H. et al. | 1997
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-
O.18m Low Voltage/Low Power RF CMOS with Zero Vth Analog MOSFETs Made by Undoped Epitaxial Channel TechniqueOhguro, T. / Naruse, H. / Sugaya, H. / Morifuji, E. / IEEE; Electron Devices Society et al. | 1997
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-
0.18 /spl mu/m low voltage/low power RF CMOS with zero Vth analog MOSFETs made by undoped epitaxial channel techniqueOhguro, T. / Naruse, H. / Sugaya, H. / Morifuji, E. / Nakamura, S. / Yoshitomi, T. / Morimoto, T. / Momose, H.S. / Katsumata, Y. / Iwai, H. et al. | 1997
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-
Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuationTakeuchi, K. / Tatsumi, T. / Furukawa, A. et al. | 1997
- 847
-
A 2.9m^2 Embedded SRAM Cell with Co-Salicide Direct-Strap Technology for 0.18m High Performance CMOS LogicNoda, K. / Matsui, K. / Inoue, K. / Itani, T. / IEEE; Electron Devices Society et al. | 1997
- 847
-
A 2.9 /spl mu/m/sup 2/ embedded SRAM cell with co-salicide direct-strap technology for 0.18 /spl mu/m high performance CMOS logicNoda, K. / Matsui, K. / Inoue, K. / Itani, T. / Iwasaki, H. / Urabe, K. / Miyamoto, H. / Tokashiki, K. / Kawamoto, H. / Satoh, M. et al. | 1997
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-
A fully planarized 6-level-metal CMOS technology for 0.25-0.18 micron foundry manufacturingLin, T. / Chen, C. / Hsu, S.Y. / Tsai, M.J. / Yew, T.R. / Chou, J.W. / Haung, K.T. / Wu, J.Y. / Ku, Y.C. / Liu, C.C. et al. | 1997
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-
A PROM element based on salicide agglomeration of poly fuses in a CMOS logic processAlavi, M. / Bohr, M. / Hicks, J. / Denham, M. / Cassens, A. / Douglas, D. / Tsai, M.-C. et al. | 1997
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-
Low-voltage and high-speed operation for high-density SRAMs by BBC cellMaki, Y. / Honda, H. / Morimoto, R. / Sato, H. / Nagaoka, H. / Wada, T. / Arita, Y. / Tsutsumi, K. / Miyoshi, H. et al. | 1997
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-
A high density 1T/2C cell with Vcc/2 reference level for high stable FeRAMsTanabe, N. / Kobayashi, S. / Hada, H. / Kunio, T. et al. | 1997
- 869
-
Physical oxide thickness extraction and verification using quantum mechanical simulationBowen, C. / Fernando, C.L. / Klimeck, G. / Chatterjee, A. / Blanks, D. / Lake, R. / Hu, J. / Davis, J. / Kulkarni, M. / Hattangady, S. et al. | 1997
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-
Physical Oxide Thickness Extraction and Verification Using Quantum Mechanical SimulatonBowen, C. / Fernando, C. / Klimeck, G. / Chatterjee, A. / IEEE; Electron Devices Society et al. | 1997
- 873
-
Assessment of quantum yield experiments via full band Monte Carlo simulationsGhetti, A. / Alam, M.A. / Bude, J. / Venturi, F. et al. | 1997
- 877
-
Monte Carlo study of velocity overshoot in switching a 0.1-micron CMOS inverterLaux, S.E. / Fischetti, M.V. et al. | 1997
- 881
-
A comprehensive SiGe Monte Carlo model for transient 2D simulations of HBTsGraf, P. / Bufler, F.M. / Meinerzhagen, B. / Jungemann, C. et al. | 1997
- 881
-
A Comprehensive SiGe Monte Carlo Model for Transient 2D Simulation of HBTsGraf, P. / Bufler, F. M. / Meinerzhagen, B. / IEEE; Electron Devices Society et al. | 1997
- 885
-
A unified substrate current model for weak and strong impact ionization in sub-0.25 /spl mu/m NMOS devicesRamaswamy, S. / Amerasekera, A. / Chang, M.-C. et al. | 1997
- 885
-
A Unified Substrate Current Model for Weak and Strong Impact Ionization in Sub-0.25m NMOS DevicesRamaswamy, S. / Amersekera, A. / Chang, M. C. / IEEE; Electron Devices Society et al. | 1997
- 891
-
A vertical cavity longwave infrared SiGe/Si photodetector using a buried silicide mirrorCarline, R.T. / Nayar, V. / Robbins, D.J. / Stanaway, M.B. et al. | 1997
- 895
-
Single-chip CMOS anemometerMayer, F. / Haberli, A. / Jacobs, H. / Ofner, G. / Paul, O. / Baltes, H. et al. | 1997
- 899
-
Micromachined accelerometer with no proof massLeung, A.M. / Jones, J. / Czyzewska, E. / Chen, J. / Pascal, M. et al. | 1997
- 903
-
Multi-layer enhancement to polysilicon surface-micromachining technologySniegowski, J.J. / Rodgers, M.S. et al. | 1997
- 907
-
High sensitivity CMOS microfluxgate sensorSchneider, M. / Kawahito, S. / Tadokoro, Y. / Baltes, H. et al. | 1997
- 907
-
High Sensitivity CMOS MicroFluxgage SensorSchneider, M. / Kawahito, S. / Tadokoro, Y. / Baltes, H. / IEEE; Electron Devices Society et al. | 1997
- 911
-
Double-Hall sensor with self-compensated offsetSteiner, R. / Schneider, M. / Baltes, H. et al. | 1997
- 915
-
CCD based pH imaging sensorMimura, S. / Sawada, K. / Tomita, K. / Nakanishi, T. / Tanabe, H. / Ando, T. et al. | 1997
- 921
-
An ultra low-power RF bipolar technology on glassDekker, R. / Baltus, P. / van Deurzen, M. / Einden, W.v.d. / Maas, H. / Wagemans, A. et al. | 1997
- 924
-
A 3-D single-electron-memory cell structure with 2F/sup 2/ per bitIshii, T. / Yano, K. / Sano, T. / Mine, T. / Murai, F. / Kure, T. / Seki, K. et al. | 1997
- 924
-
A 3-D Single-Electron-Memory Cell Structure with 2F^2 per bitIshii, T. / Yano, K. / Sano, T. / Mine, T. / IEEE; Electron Devices Society et al. | 1997
- 927
-
A 0.6m CMOS Pinned Photodiode Color Imager TechnologyGuidash, R. / Lee, T. H. / Lee, P. P. K. / Sackett, D. / IEEE; Electron Devices Society et al. | 1997
- 927
-
A 0.6 /spl mu/m CMOS pinned photodiode color imager technologyGuidash, R.M. / Lee, T.-H. / Lee, P.P.K. / Sackett, D.H. / Drowley, C.I. / Swenson, M.S. / Arbaugh, L. / Hollstein, R. / Shapiro, F. / Domer, S. et al. | 1997
- 930
-
Low leakage, ultra-thin gate oxides for extremely high performance sub-100 nm nMOSFETsTimp, G. / Agarwal, A. / Baumann, F.H. / Boone, T. / Buonanno, M. / Cirelli, R. / Donnelly, V. / Foad, M. / Grant, D. / Green, M. et al. | 1997
- 933
-
Multi-generation device fabrication by ArF lithographyMori, S. / Morisawa, T. / Matsuzawa, N. / Kaimoto, Y. / Endo, M. / Matsuo, T. / Takahashi, M. / Naito, T. / Naruse, Y. / Takechi, S. et al. | 1997
- 936
-
Damascene integration of copper and ultra-low-k xerogel for high performance interconnectsZielinski, E.M. / Russell, S.W. / List, R.S. / Wilson, A.M. / Jin, C. / Newton, K.J. / Lu, J.P. / Hurd, T. / Hsu, W.Y. / Cordasco, V. et al. | 1997
- 939
-
Hole mobility improvement in silicon-on-insulator and bulk silicon transistors using local strainTiwari, S. / Fischetti, M.V. / Mooney, P.M. / Welser, J.J. et al. | 1997
- 942
-
Novel gain cell with ferroelectric coplanar capacitor for high-density nonvolatile random-access memoryAoki, M. / Takauchi, H. / Tamura, H. et al. | 1997