A case study of hardware and software synthesis in ForSyDe (English)
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- New search for: Zhonghai Lu,
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In:
15th International Symposium on System Synthesis, 2002.
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86-91
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2002
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ISBN:
- Conference paper / Electronic Resource
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Title:A case study of hardware and software synthesis in ForSyDe
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Contributors:
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Published in:
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Publisher:
- New search for: IEEE
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Publication date:2002-01-01
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Size:452776 byte
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ISBN:
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DOI:
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Type of media:Conference paper
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Type of material:Electronic Resource
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Language:English
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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Mobile, Broadband, Ubiquitous, and the Information RenaissanceOhboshi, K. / Association for Computing Machinery et al. | 2002
- 2
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A Trimaran based framework for exploring the design space of VLIW ASIPs with coarse grain functional unitsMiddha, B. / Raj, V. / Gangwar, A. / Kumar, A. / Balakrishnan, M. / Ienne, P. et al. | 2002
- 8
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Tuning of loop cache architectures to programs in embedded system designCotterell, S. / Vahid, F. et al. | 2002
- 14
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Combined functional partitioning and communication speed selection for networked voltage-scalable processorsJinfeng Liu, / Chou, P.H. / Bagherzadeh, N. et al. | 2002
- 20
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Optimal message-passing for data coherency in distributed architectureJunyu Peng, / Gajski, D. et al. | 2002
- 26
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Unifying memory and processor wrapper architecture in multiprocessor SoC designGharsalli, F. / Lyonnard, D. / Meftali, A. / Rousseau, F. / Jerraya, A.A. et al. | 2002
- 32
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An accelerated datapath width optimization scheme for area reduction of embedded systemsUddin, M.M. / Cao, Y. / Yasuura, H. et al. | 2002
- 38
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Datapath merging and interconnection sharing for reconfigurable architecturesMoreano, N. / Araujo, G. / Zhining Huang, / Malik, S. et al. | 2002
- 44
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A run-time word-level reconfigurable coarse-grain functional unit for a VLIW processorBusa, N.G. / Sala, C.R. et al. | 2002
- 50
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Energy/power estimation of regular processor arraysDerrien, S. / Rajopadhye, S. et al. | 2002
- 56
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Controller estimation for FPGA target architectures during high-level synthesisMenn, C. / Bringmann, O. / Rosenstiel, W. et al. | 2002
- 62
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System-level modeling of a network switch SoCPaul, J.M. / Andrews, C.P. / Cassidy, A.S. / Thomas, D.E. et al. | 2002
- 68
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Multiprocessor mapping of process networks: a JPEG decoding case studyde Kock, E.A. et al. | 2002
- 74
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System-level design of IEEE1394 bus segment bridgeYamamoto, H. / Chikamura, K. / Shigiya, A. / Tsujino, K. / Izumi, T. / Onoye, T. / Nakamura, Y. et al. | 2002
- 80
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Security-driven exploration of cryptography in DSP coresGebotys, C.H. et al. | 2002
- 86
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A case study of hardware and software synthesis in ForSyDeZhonghai Lu, / Sander, I. / Jantsch, A. et al. | 2002
- 92
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An adaptive low-power transmission scheme for on-chip networksWorm, F. / Ienne, P. / Thiran, P. / de micheli, G. et al. | 2002
- 101
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CMP on SoC: architect's viewSakai, S. et al. | 2002
- 103
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Design experience of a chip multiprocessor Merlot and expectation to functional verificationMatsushita, S. et al. | 2002
- 109
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OpenMP: parallel programming API for shared memory multiprocessors and on-chip multiprocessorsSato, M. et al. | 2002
- 112
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Managing dynamic concurrent tasks in embedded real-time multimedia systemsPeng Yang, / Marchal, P. / Chun Wong, / Himpe, S. / Catthoor, F. / David, P. / Vounckx, J. / Lauwereins, R. et al. | 2002
- 120
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A design space exploration framework for reduced bit-width Instruction Set architecture (rISA) designHalambi, A. / Shrivastava, A. / Biswas, P. / Dutt, N. / Nicolau, A. et al. | 2002
- 126
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Timing analysis of embedded software for speculative processorsMitra, T. / Roychoudhury, A. / Xianfeng Li, et al. | 2002
- 132
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Modeling assembly instruction timing in superscalar architecturesBeltrame, G. / Brandolese, C. / Fornaciari, W. / Salice, F. / Sciuto, D. / Trianni, V. et al. | 2002
- 138
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Code compression for VLIW processors using variable-to-fixed codingYuan Xie, / Wolf, W. / Lekatsas, H. et al. | 2002
- 144
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Optimal code size reduction for software-pipelined and unfolded loopsQingfeng Zhuge, / Bin Xiao, / Zili Shao, / Sha, E.H.-M. / Chantana Chantrapornchai, et al. | 2002
- 150
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The formal execution semantics of SpecCMueller, W. / Domer, R. / Gerstlauer, A. et al. | 2002
- 156
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Formal verification in a component-based reuse methodologyKarlsson, D. / Eles, P. / Zebo Peng, et al. | 2002
- 162
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Validation in a component-based design flow for multicore SoCsNicolescu, G. / Sungjoo Yoo, / Bouchhima, A. / Jerraya, A.A. et al. | 2002
- 168
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Efficient simulation of synthesis-oriented system level designsSavoiu, N. / Shukla, S.K. / Gupta, R.K. et al. | 2002
- 174
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Virtual synchronization for fast distributed cosimulation of dataflow task graphsDohyung Kim, / Chan-Eun Rhee, / Youngmin Yi, / Sungchan Kim, / Hyunguk Jung, / Soonhoi Ha, et al. | 2002
- 180
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A new performance evaluation approach for system level design space explorationJoshi, C.P. / Kumar, A. / Balakrishnan, M. et al. | 2002
- 186
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A visual approach to validating system level designsKlose, J. / Kropf, T. / Ruf, J. et al. | 2002
- 192
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Special session: security on SoCGebotys, C. / Yasuura, H. / Torla, M. / Ravi, S. / Takagi, N. et al. | 2002
- 195
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Securing wireless data: system architecture challengesRavi, S. / Raghunathan, A. / Potlapally, N. et al. | 2002
- 201
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Data memory design considering effective bitwidth for low-energy embedded systemsCao, Y. / Tomiyama, H. / Okuma, T. / Yasuura, H. et al. | 2002
- 207
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Efficient power reduction techniques for time multiplexed address busesMamidipaka, M. / Dutt, N. / Hirschberg, D. et al. | 2002
- 213
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Reducing energy consumption by dynamic copying of instructions onto onchip memorySteinke, S. / Grunwald, N. / Wehmeyer, L. / Banakar, R. / Balakrishnan, M. / Marwedel, P. et al. | 2002
- 219
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Low-power data memory communication for application-specific embedded processorsPetrov, P. / Orailoglu, A. et al. | 2002
- 225
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System level power-performance trade-offs in embedded systems using voltage and frequency scaling of off-chip buses and memoryPuttaswamy, K. / Kyu-Won Choi, / Jun Cheol Park, / Mooney, V.J. / Chatterjee, A. / Ellervee, P. et al. | 2002
- 231
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System-level abstraction semanticsGerstlauer, A. / Gajski, D.D. et al. | 2002
- 237
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A symbolic approach for the combined solution of scheduling and allocationCabodi, G. / Lazarescu, M. / Lavagno, L. / Nocco, S. / Passerone, C. / Quer, S. et al. | 2002
- 243
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Round-robin Arbiter Design and GenerationShin, E.S. / Mooney, V.J. / Riley, G.F. et al. | 2002
- 249
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An object-oriented design process for system-on-chip using UMLQiang Zhu, / Matsuda, A. / Kuwamura, S. / Nakata, T. / Shoji, M. et al. | 2002
- 255
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Improving embedded system design by means of HW-SW compilation on reconfigurable coprocessorsMoya, J.M. / Rincon, F. / Moya, F. / Lopez, J.C. et al. | 2002
- 261
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Dynamic common sub-expression elimination during scheduling in high-level synthesisGupta, S. / Reshadi, M. / Savoiu, N. / Duff, N. / Gupta, R. / Nicolau, A. et al. | 2002
- 267
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Author index| 2002
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15th International Symposium on System Synthesis (IEEE Cat. No.02EX631)| 2002