3D-carrier Profiling and Parasitic Resistance Analysis in Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors (English)
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In:
2019 IEEE International Electron Devices Meeting (IEDM)
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11.3.1-11.3.4
;
2019
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ISBN:
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ISSN:
- Conference paper / Electronic Resource
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Title:3D-carrier Profiling and Parasitic Resistance Analysis in Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors
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Contributors:Eyben, P. ( author ) / Machillot, J. ( author ) / Kim, M. ( author ) / Miyashita, T. ( author ) / Yoshida, N. ( author ) / Bender, H. ( author ) / Richard, O. ( author ) / Paredis, K. ( author ) / Wouters, L. ( author ) / Mitard, J. ( author )
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Published in:2019 IEEE International Electron Devices Meeting (IEDM) ; 11.3.1-11.3.4
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Publisher:
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Publication date:2019-12-01
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Size:1913773 byte
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ISBN:
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ISSN:
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DOI:
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Type of media:Conference paper
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Type of material:Electronic Resource
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Language:English
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1.1.1
-
Process and Packaging Innovations for Moore’s Law Continuation and BeyondChau, Robert et al. | 2019
- 1.2.1
-
Continued Scaling in Semiconductor Manufacturing Enabled by Advances in Lithographyden Brink, Martin van et al. | 2019
- 1.3.1
-
Future of Non-Volatile Memory -From Storage to Computing-Ishimaru, K. et al. | 2019
- 2.1.1
-
Demonstration of a Reliable 1 Gb Standalone Spin-Transfer Torque MRAM For Industrial ApplicationsAggarwal, S. / Nagel, K. / Shimon, G. / Sun, J. J. / Andre, T. / Alam, S. M. / Almasi, H. / DeHerrera, M. / Hughes, B. / Ikegawa, S. et al. | 2019
- 2.2.1
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1Gbit High Density Embedded STT-MRAM in 28nm FDSOI TechnologyLee, K. / Kim, W. J. / Lee, J. H. / Bae, B. J. / Park, J. H. / Kim, I. H. / Seo, B. Y. / Han, S. H. / Ji, Y. / Jung, H. T. et al. | 2019
- 2.3.1
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Manufacturable 22nm FD-SOI Embedded MRAM Technology for Industrial-grade MCU and IOT ApplicationsNaik, V. B. / Lim, J. H. / Lee, T. Y. / Neo, W. P. / Dixit, H. / K, S. / Goh, L. C. / Ling, T. / Hwang, J. / Zeng, D. et al. | 2019
- 2.4.1
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2 MB Array-Level Demonstration of STT-MRAM Process and Performance Towards L4 Cache ApplicationsAlzate, J.G. / Hentges, P. / Jahan, R. / Littlejohn, A. / Mainuddin, M. / Ouellette, D. / Pellegren, J. / Pramanik, T. / Puls, C. / Quintero, P. et al. | 2019
- 2.5.1
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A novel integration of STT-MRAM for on-chip hybrid memory by utilizing non-volatility modulationPark, J.-H. / Kwon, S. / Bae, B.-J. / Kim, I. / Ji, N. / Lee, K. / Shin, H. / Han, S. H. / Hwang, S. / Jeong, D. et al. | 2019
- 2.6.1
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Spin-transfer torque MRAM with reliable 2 ns writing for last level cache applicationsHu, G. / Kim, D. / Kim, J. / Kothandaraman, C. / Lauer, G. / Lee, H K / Marchack, N. / Reuter, M. / Robertazzi, R. P. / Sun, J. Z. et al. | 2019
- 2.7.1
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22nm STT-MRAM for Reflow and Automotive Uses with High Yield, Reliability, and Magnetic Immunity and with Performance and Shielding OptionsGallagher, W.J. / Lee, George / Shih, Yi-Chun / Lee, Chia-Fu / Lee, Po-Hao / Wang, Roger / Shen, Kuei- Hung / Wu, J. J. / Wang, Wayne / Chuang, Harry et al. | 2019
- 3.1.1
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Monolithic 3D BEOL FinFET switch arrays using location-controlled-grain technique in voltage regulator with better FOM than 2D regulatorsHsieh, Ping-Yi / Huang, Chien-Chi / Tai, Ming-Chi / Lo, Wei-Chung / Shen, Chang-Hong / Shieh, Jia-Min / Chang, Da-Chiang / Chen, Kuan-Neng / Yeh, Wen-Kuan / Hu, Chenming et al. | 2019
- 3.2.1
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3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nmOota, Masashi / Hodo, Ryota / Ikeda, Takayuki / Yamazaki, Shunpei / Ando, Yoshinori / Tsuda, Kazuki / Koshida, Tatsuki / Oshita, Satoru / Suzuki, Akio / Fukushima, Kunihiro et al. | 2019
- 3.3.1
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Monolithic 3D SRAM-CIM Macro Fabricated with BEOL Gate-All-Around MOSFETsHsueh, Fu-Kuo / Huang, Wen-Hsien / Li, Kai-Shin / Wu, Chien-Ting / Lin, Kun-Lin / Chen, Kun-Ming / Huang, Guo-Wei / Chang, Meng-Fan / Hu, Chenming / Yeh, Wen-Kuan et al. | 2019
- 3.4.1
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Inter-tier Dynamic Coupling and RF Crosstalk in 3D Sequential IntegrationSideris, P. / Andrieu, F. / Colinge, J-P. / Ghibaudo, G. / Theodorou, C. / Lugo-Alvarez, J. / Batude, P. / Brunet, L. / Acosta-Alba, P. / Kerdiles, S. et al. | 2019
- 3.5.1
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BEOL Compatible 15-nm Channel Length Ultrathin Indium-Tin-Oxide Transistors with Ion = 970 μA/μm and On/off Ratio Near 1011 at Vds = 0.5 VLi, Shengman / Tian, Mengchuan / Gu, Chengru / Wang, Runsheng / Wang, Mengfei / Xiong, Xiong / Li, Xuefei / Huang, Ru / Wu, Yanqing et al. | 2019
- 4.1.1
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1200 V Multi-Channel Power Devices with 2.8 Ω•mm ON-ResistanceMa, Jun / Erine, Catherine / Zhu, Minghua / Luca, Nela / Xiang, Peng / Cheng, Kai / Matioli, Elison et al. | 2019
- 4.2.1
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Impact Ionization Coefficients in GaN Measured by Above- and Sub-Eg Illuminations for p−/n+ JunctionMaeda, Takuya / Narita, Tetsuo / Yamada, Shinji / Kachi, Tetsu / Kimoto, Tsunenobu / Horita, Masahiro / Suda, Jun et al. | 2019
- 4.3.1
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Investigation of nBTI degradation on GaN-on-Si E-mode MOSc-HEMTViey, A.G. / Gaillard, F. / Modica, R. / Iucolano, F. / Meneghini, M. / Zanoni, E. / Meneghesso, G. / Ghibaudo, G. / Vandendaele, W. / Jaud, M.-A. et al. | 2019
- 4.4.1
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GaN-on-SOI: Monolithically Integrated All-GaN ICs for Power ConversionLi, X. / Stoffels, S. / Bakeroot, B. / Wellekens, D. / Vanhove, B. / Cosnier, T. / Langer, R. / Marcon, D. / Groeseneken, G. / Decoutere, S. et al. | 2019
- 4.5.1
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GaN/AlN Schottky-gate p-channel HFETs with InGaN contacts and 100 mA/mm on-currentBader, S. J. / Chaudhuri, R. / Hickman, A. / Nomoto, K. / Bharadwaj, S. / Then, H. W. / Xing, H. G. / Jena, D. et al. | 2019
- 4.6.1
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First Demonstration of a Self-Aligned GaN p-FETChowdhury, Nadim / Xie, Qingyun / Yuan, Mengyang / Rajput, Nitul S. / Xiang, Peng / Cheng, Kai / Then, Han Wui / Palacios, Tomas et al. | 2019
- 5.1.1
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Reverse tip sample scanning for precise and high-throughput electrical characterization of advanced nodesCelano, U. / Paredis, K. / Vandervorst, W. / der Heide, P. van / Hantschel, T. / Boehme, T. / Kanniainen, A. / Wouters, L. / Bender, H. / Bosman, N. et al. | 2019
- 5.2.1
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Hot-Spot Thermal Sensor Design in FinFETsLiu, S. L. / Horng, J. J. / kundu, Amit / Lien, B. S. / Lee, C. H. / Chen, Y. H. / Kuo, Chester / Peng, Y. C. / Chen, Mark et al. | 2019
- 5.3.1
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Characterizing Electromigration Effects in a 16nm FinFET Process Using a Circuit Based Test VehiclePande, N. / Zhou, C. / Lin, MH / Fung, R. / Wong, R. / Wen, S. / Kim, C. H. et al. | 2019
- 5.4.1
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Humidity Penetration Impact on Integrated Circuit Performance and ReliabilityStellari, Franco / Cabral, Cyril / Song, Peilin / Laibowitz, Robert et al. | 2019
- 5.5.1
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Non-Planarization Cu-Cu Direct Bonding and Gang Bonding with Low Temperature and Short Duration in Ambient AtmosphereChou, Tzu-Chieh / Yang, Kai-Ming / Li, Jian-Chen / Yu, Ting-Yang / Chung, Ying-Ting / Ko, Cheng-Ta / Chen, Yu-Hua / Tseng, Tzyy-Jang / Chen, Kuan-Neng et al. | 2019
- 6.1.1
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Reducing the Impact of Phase-Change Memory Conductance Drift on the Inference of large-scale Hardware Neural NetworksAmbrogio, S. / Kumar, A. / Chen, A. / Burr, G. W. / Gallot, M. / Spoon, K. / Tsai, H. / Mackin, C. / Wesson, M. / Kariyappa, S. et al. | 2019
- 6.2.1
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Performance Maximization of In-Memory Reinforcement Learning with Variability-Controlled Hf1-xZrxO2 Ferroelectric Tunnel JunctionsOta, K. / Deguchi, J. / Fujii, S. / Saitoh, M. / Yamaguchi, M. / Berdan, R. / Marukame, T. / Nishi, Y. / Matsuo, K. / Takahashi, K. et al. | 2019
- 6.3.1
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Sub-nA Low-Current HZO Ferroelectric Tunnel Junction for High-Performance and Accurate Deep Learning AccelerationWu, Tzu-Yun / Chang, Tian-Sheuan / Lee, Heng-Yuan / Sheu, Shyh-Shyuan / Lo, Wei-Chung / Hou, Tuo-Hung / Huang, Hsin-Hui / Chu, Yueh-Hua / Chang, Chih-Cheng / Wu, Ming-Hung et al. | 2019
- 6.4.1
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Capacitor-less Stochastic Leaky-FeFET Neuron of Both Excitatory and Inhibitory Connections for SNN with Reduced Hardware CostLuo, Jin / Wu, Si / Huang, Qianqian / Huang, Ru / Yu, Liutao / Liu, Tianyi / Yang, Mengxuan / Fu, Zhiyuan / Liang, Zhongxin / Chen, Liang et al. | 2019
- 6.5.1
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Complementary Graphene-Ferroelectric Transistors (C-GFTs) as Synapses with Modulatable Plasticity for Supervised LearningZhou, Yue / Xu, Nuo / Gao, Bin / Chen, Yangyang / Dong, Boyi / Li, Yi / He, Yuhui / Miao, Xiang Shui et al. | 2019
- 6.6.1
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A Novel Scalable Energy-Efficient Synaptic Device: Crossbar Ferroelectric Semiconductor JunctionSi, M. / Ye, P. D. / Luo, Y. / Chung, W. / Bae, H. / Zheng, D. / Li, J. / Qin, J. / Qiu, G. / Yu, S. et al. | 2019
- 6.7.1
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Experimental Demonstration of Conversion-Based SNNs with 1T1R Mott Neurons for Neuromorphic InferenceZhang, Xumeng / Yang, J. Joshua / Liu, Qi / Liu, Ming / Wang, Zhongrui / Song, Wenhao / Midya, Rivu / Zhuo, Ye / Wang, Rui / Rao, Mingyi et al. | 2019
- 7.1.1
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Hysteresis-free negative capacitance in the multi-domain scenario for logic applicationsGomez, J. / Dutta, S. / Ni, K. / Smith, J.A. / Grisafe, B. / Khan, A. / Datta, S. et al. | 2019
- 7.2.1
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Revised analysis of negative capacitance in ferroelectric-insulator capacitors: analytical and numerical results, physical insight, comparison to experimentsRollo, T. / Blanchini, F. / Giordano, G. / Specogna, R. / Esseni, D. et al. | 2019
- 7.3.1
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Electrostatic Integrity in Negative-Capacitance FETs – A Subthreshold Modeling ApproachSu, Pin / You, Wei-Xiang et al. | 2019
- 7.4.1
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Equivalent Oxide Thickness (EOT) Scaling With Hafnium Zirconium Oxide High-κ Dielectric Near Morphotropic Phase BoundaryNi, Kai / Saha, Atanu / Chakraborty, Wriddhi / Ye, Huacheng / Grisafe, Benjamin / Smith, Jeffrey / Rayner, G. Bruce / Gupta, Sumeet / Datta, Suman et al. | 2019
- 7.5.1
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Surface potential-Based Compact Model for Negative Capacitance FETs Compatible for Logic Circuit: with Time Dependence and Multidomain InteractionZhao, Ying / Li, Ling / Peng, Yue / Li, Quan / Yang, Guanhua / Chuai, Xichen / Li, Qiang / Han, Genquan / Liu, Ming et al. | 2019
- 8.1.1
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14nm FinFET process technology platform for over 100M pixel density and ultra low power 3D Stack CMOS Image SensorYu, Donghee / Choi, Jong-Won / Jung, Sangil / Kwon, Minho / Ha, Il-Seon / Kim, Chaesung / Cho, Sanghyun / Lim, Seunghyun / Kim, Won-Woong / Kim, Moo-Young et al. | 2019
- 8.2.1
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High Performance Gigahertz Flexible Radio Frequency Transistors with Extreme Bending ConditionsWang, Mengfei / Huang, Ru / Wu, Yanqing / Tian, Mengchuan / Zhang, Zhenfeng / Li, Shengman / Wang, Runsheng / Gu, Chengru / Shan, Xiaoyu / Xiong, Xiong et al. | 2019
- 8.3.1
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A Novel Structural Design Serving as a Stress Relief Layer for Flexible LTPS TFTsWang, Yu-Xuan / Chang, Ting-Chang / Huang, Shin-Ping / Tai, Mao-Chou / Zheng, Yu-Zhe / Wu, Chia-Chuan / Sze, Simon et al. | 2019
- 8.4.1
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Self-Aligned Elevated-Metal Metal-Oxide Thin-Film Transistors for Displays and Flexible ElectronicsXia, Zhihe / Lu, Lei / Li, Jiapeng / Kwok, Hoi-Sing / Wong, Man et al. | 2019
- 8.5.1
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Flexible, active-matrix flat-panel image sensor for low dose X-ray detection enabled by integration of perovskite photodiode and oxide thin film transistorZou, Taoyu / Chen, Changdong / Xiang, Ben / Wang, Ya / Liu, Chuan / Zhang, Shengdong / Zhou, Hang et al. | 2019
- 9.1.1
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First demonstration of III-V HBTs on 300 mm Si substrates using nano-ridge engineeringVais, A. / Alcotte, R. / Ingels, M. / Wambacq, P. / Parvais, B. / Langer, R. / Kunert, B. / Waldron, N. / Collaert, N. / Witters, L. et al. | 2019
- 9.2.1
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Millimeter-wave InP Device Technologies for Ultra-high Speed Wireless Communications toward Beyond 5GHamada, H. / Nosaka, H. / Tsutsumi, T. / Sugiyama, H. / Matsuzaki, H. / Song, H.-J. / Itami, G. / Fujimura, T. / Abdo, I. / Okada, K. et al. | 2019
- 9.3.1
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Impact Ionization Control in 50 nm Low-Noise High-Speed InP HEMTs with InAs Channel InsetsRuiz, Diego C. / Saranovac, Tamara / Han, Daxin / Ostinelli, Olivier / Bolognesi, C.R. et al. | 2019
- 9.4.1
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Weyl Semi-Metal-Based High-Frequency AmplifiersToniato, A. / Gotsmann, B. / Lind, E. / Zota, C. B. et al. | 2019
- 9.5.1
-
Non-volatile RF and mm-wave Switches Based on Monolayer hBNKim, Myungsoo / Pallecchi, Emiliano / Ge, Ruijing / Wu, Xiaohan / Avramovic, Vanessa / Okada, Etienne / Lee, Jack C. / Happy, Henri / Akinwande, Deji et al. | 2019
- 9.6.1
-
Non-Reciprocal Acoustoelectric Amplification in Germanium-Based Lamb Wave Delay LinesHakim, F. / Ramezani, M. / Rassay, S. / Tabrizian, R. et al. | 2019
- 10.1.1
-
The Neuropixels probe: A CMOS based integrated microsystems platform for neuroscience and brain-computer interfacesDutta, B. / Trautmann, E. M. / Welkenhuysen, M. / Shenoy, K. V. / Andrei, A. / Harris, T. D. / Lopez, C. M. / O'Callahan, J. / Putzeys, J. / Raducanu, B. C. et al. | 2019
- 10.2.1
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Microfabricated bioelectronic systems for prevention, diagnostics and treatment of neurological disordersSchiavone, Giuseppe / Fallegger, Florian / Schonle, Philipp / Huang, Qiuting / Lacour, Stephanie P. et al. | 2019
- 10.3.1
-
Haptics-Led Innovation for Coming SocietyOhnishi, K. / Nozaki, T. / Saito, Y. / Shimono, T. / Mizoguchi, T. et al. | 2019
- 10.4.1
-
Challenges in the Development of Wearable Human Machine Interface SystemsO'Flynn, Brendan / Sanchez-Torres, Javier / Tedesco, Salvatore / Walsh, Michael et al. | 2019
- 10.5.1
-
Intelligent Vision Systems – Bringing Human-Machine Interface to AR/VRLiu, Chiao / Berkovich, Andrew / Chen, Song / Reyserhove, Hans / Sarwar, Syed Shakib / Tsai, Tsung-Hsun et al. | 2019
- 10.6.1
-
Low-Latency Interactive Sensing for Machine VisionPark, Paul K. J. / Soloveichik, Evgeny / Ryu, Hyunsurk Eric / Seok Kim, Jun- / Shin, Chang- Woo / Lee, Hyunku / Liu, Weiheng / Wang, Qiang / Roh, Yohan / Kim, Jeonghan et al. | 2019
- 10.7.1
-
High-speed Image Processing Devices and Its ApplicationsIshikawa, Masatoshi et al. | 2019
- 11.1.1
-
Vertical Nanowire and Nanosheet FETs: Device Features, Novel Schemes for Improved Process Control and Enhanced Mobility, Potential for Faster & More Energy Efficient CircuitsVeloso, A. / Hikavyy, A. / Loo, R. / Paraschiv, V. / Chan, B. T. / Radisic, D. / Li, W. / Versluijs, J. J. / Teugels, L. / Sebaai, F. et al. | 2019
- 11.2.1
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Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power ApplicationsBao, R. / Vega, R. / Pancharatnam, S. / Jamison, P. / Wang, M. / Loubet, N. / Basker, V. / Dechene, D. / Guo, D. / Haran, B. et al. | 2019
- 11.3.1
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3D-carrier Profiling and Parasitic Resistance Analysis in Vertically Stacked Gate-All-Around Si Nanowire CMOS TransistorsEyben, P. / Machillot, J. / Kim, M. / Miyashita, T. / Yoshida, N. / Bender, H. / Richard, O. / Paredis, K. / Wouters, L. / Mitard, J. et al. | 2019
- 11.4.1
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A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet DevicesLoubet, N. / Devarajan, T. / Zhang, J. / Miao, X. / Sankar, M. / Breton, M. / Chao, R. / Greene, A. / Yu, L. / Frougier, J. et al. | 2019
- 11.5.1
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Imaging, Modeling and Engineering of Strain in Gate-All-Around Nanosheet TransitorsReboh, S. / Boureau, V. / Yamashita, T. / Faynot, O. / Coquand, R. / Loubet, N. / Bernier, N. / Augendre, E. / Chao, R. / Li, J. et al. | 2019
- 11.6.1
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Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance ApplicationsZhang, J. / Pancharatnam, S. / Adams, C. / Wu, H. / Zhou, H. / Shen, T. / Xie, R. / Sankarapandian, M. / Wang, J. / Watanabe, K. et al. | 2019
- 11.7.1
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First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC ApplicationsChang, S.-W. / Li, J.-H. / Huang, M.-K. / Huang, Y.-C. / Huang, S.-T. / Wang, H.-C. / Huang, Y.-J. / Wang, J.-Y. / Yu, L. - W / Huang, Y.-F. et al. | 2019
- 12.1.1
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Modeling Needs for Power Semiconductor Devices and Power Electronics SystemsKotecha, Ramchandra / Moreno, Gilberto / Mather, Barry / Narumanchi, Sreekant et al. | 2019
- 12.2.1
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Progress in Si IGBT Technology – as an ongoing Competition with WBG Power DevicesLaska, T. et al. | 2019
- 12.3.1
-
Dynamic Avalanche Free Design in 1.2kV Si-IGBTs for Ultra High Current Density OperationLuo, Peng / Ekkanath Madathil, Sankara Narayanan / Nishizawa, Shin-ichi / Saito, Wataru et al. | 2019
- 12.4.1
-
Single and multi-fin normally-off Ga2O3 vertical transistors with a breakdown voltage over 2.6 kVLi, W. / Nomoto, K. / Hu, Z. / Nakamura, T. / Jena, D. / Xing, H. G. et al. | 2019
- 12.5.1
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First Demonstration of Waferscale Heterogeneous Integration of Ga2O3 MOSFETs on SiC and Si Substrates by Ion-Cutting ProcessXu, Wenhui / Zhang, Yuhao / Hao, Yue / Wang, Xi / Wang, Yibo / You, Tiangui / Ou, Xin / Han, Genquan / Hu, Haodong / Zhang, Shibin et al. | 2019
- 13.1.1
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Challenges in Radio Frequency and Mixed-Signal Circuit ReliabilityReddy, V. / Martin, S. / Benaissa, K. / Chancellor, C. / Bhatia, K. / Srinivasan, V. / Rentala, V. / Krishnan, S. / Ondrusek, J. et al. | 2019
- 13.2.1
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Telemetry for System ReliabilityKwasnick, Robert / Gartler, Hermann / Boelter, Josh / Holm, John / Surisetty, Sheela / Im, Chansik / Polasam, Praveen / Zonensain, Oren et al. | 2019
- 13.3.1
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Enabling Prognostics of Robust Design with Interpretable Machine LearningSarkar, Jay / Peterson, Cory et al. | 2019
- 13.4.1
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Security and reliability – friend or foeVerbauwhede, I. / Chuang, K.-H. et al. | 2019
- 13.5.1
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Designing Secure Cryptographic CircuitsHomma, N. et al. | 2019
- 13.6.1
-
Leveraging Circuit Reliability Effects for Designing Robust and Secure Physical Unclonable FunctionsKim, M. / Park, G. / Chiu, P. / Kim, C. H. et al. | 2019
- 13.7.1
-
Custom CMOS and Post-CMOS Crossbar Circuits for Resource-Constrained Hardware Security PrimitivesYang, Kaiyuan et al. | 2019
- 14.1.1
-
Programmable Linear RAM: A New Flash Memory-based Memristor for Artificial Synapses and Its Application to Speech Recognition SystemGao, Shifan / Hu, Jian / Xiao, Jun / Zhang, Bo / Lee, Choonghyun / Zhao, Yi / Kong, Weiran / Yang, Guangjun / Qiu, Xiang / Yang, Chun et al. | 2019
- 14.2.1
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On-Chip Trainable 1.4M 6T2R PCM Synaptic Array with 1.6K Stochastic LIF Neurons for Spiking RBMIshii, M. / Shin, U. / Hosokawa, K. / BrightSky, M. / Haensch, W. / Kim, S. / Lewis, S. / Okazaki, A. / Okazawa, J. / Ito, M. et al. | 2019
- 14.3.1
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Fully Integrated Spiking Neural Network with Analog Neurons and RRAM SynapsesValentian, A. / Rummens, F. / Vianello, E. / Mesquida, T. / de Boissac, C. Lecat-Mathieu / Bichler, O. / Reita, C. et al. | 2019
- 14.4.1
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A Deep Neural Network Accelerator Based on Tiled RRAM ArchitectureWang, Qiwen / Wang, Xinxin / Lee, Seung Hwan / Meng, Fan-Hsuan / Lu, Wei D. et al. | 2019
- 14.5.1
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On Designing Efficient and Reliable Nonvolatile Memory-Based Computing-In-Memory AcceleratorsYan, Bonan / Liu, Mengyun / Chen, Yiran / Chakrabarty, Krishnendu / Li, Hai et al. | 2019
- 14.6.1
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Bayesian Neural Network Realization by Exploiting Inherent Stochastic Characteristics of Analog RRAMLin, Yudeng / Hu, Xiaobo Sharon / Qian, He / Wu, Huaqiang / Zhang, Qingtian / Tang, Jianshi / Gao, Bin / Li, Chongxuan / Yao, Peng / Liu, Zhengwu et al. | 2019
- 14.7.1
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An Analog Neuro-Optimizer with Adaptable Annealing Based on 64×64 0T1R Crossbar CircuitMahmoodi, M. R. / Kim, H. / Fahimi, Z. / Nili, H. / Sedov, L. / Polishchuk, V. / Strukov, D. B. et al. | 2019
- 14.8.1
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A High-Speed and High-Reliability TRNG Based on Analog RRAM for IoT Security ApplicationLin, Bohan / Gao, Bin / Pang, Yachuan / Yao, Peng / Wu, Dong / He, Hu / Tang, Jianshi / Qian, He / Wu, Huaqiang et al. | 2019
- 15.1.1
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Material perspectives of HfO2-based ferroelectric films for device applicationsToriumi, Akira / Xu, Lun / Mori, Yuki / Tian, Xuan / Lomenzo, Patrick D. / Mulaosmanovic, Halid / Materano, Monica / Mikolajick, Thomas / Schroeder, Uwe et al. | 2019
- 15.2.1
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First Direct Measurement of Sub-Nanosecond Polarization Switching in Ferroelectric Hafnium Zirconium OxideLyu, X. / Si, M. / Shrestha, P. R. / Cheung, K. P. / Ye, P. D. et al. | 2019
- 15.3.1
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3D Scalable, Wake-up Free, and Highly Reliable FRAM Technology with Stress-Engineered HfZrOxLin, Y. D. / Sheu, S. S. / Hou, T. H. / Lo, W. C. / Lee, M. H. / Chang, M. F. / King, Y. C. / Lin, C. J. / Lee, H. Y. / Tang, Y. T. et al. | 2019
- 15.4.1
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Impact of Homogeneously Dispersed Al Nanoclusters by Si-monolayer Insertion into Hf0.5Zr0.5O2 Film on FeFET Memory Array with Tight Threshold Voltage DistributionMaekawa, K. / Yamashita, T. / Yamaguchi, T. / Ohara, T. / Amo, A. / Tsukuda, E. / Sonoda, K. / Yanagita, H. / Inoue, M. / Matsuura, M. et al. | 2019
- 15.5.1
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Next Generation Ferroelectric Memories enabled by Hafnium OxideMikolajick, T. / Slesazeck, S. / Schroeder, U. / Lomenzo, P. D. / Breyer, E. T. / Mulaosmanovic, H. / Hoffmann, M. / Mittmann, T. / Mehmood, F. / Max, B. et al. | 2019
- 15.6.1
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Impact of Charge trapping on Imprint and its Recovery in HfO2 based FeFETHigashi, Y. / Di Piazza, L. / Suzuki, M. / Linten, D. / Van Houdt, J. / Ronchi, N. / Kaczer, B. / Banerjee, K. / McMitchell, S. R. C. / O'Sullivan, B. J. et al. | 2019
- 15.7.1
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Demonstration of BEOL-compatible ferroelectric Hf0.5Zr0.5O2 scaled FeRAM co-integrated with 130nm CMOS for embedded NVM applicationsFrancois, T. / Pellissier, C. / Slesazeck, S. / Havel, V. / Richter, C. / Makosiej, A. / Giraud, B. / Breyer, E. T. / Materano, M. / Chiquet, P. et al. | 2019
- 16.1.1
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Nanophotonics contributions to state-of-the-art CMOS Image SensorsYokogawa, Sozo et al. | 2019
- 16.2.1
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A 0.8 µm Smart Dual Conversion Gain Pixel for 64 Megapixels CMOS Image Sensor with 12k e- Full-Well Capacitance and Low Dark NoisePark, Donghyuk / Joo, Woong / Lee, Yunki / Nah, Seungjoo / Jeong, Heegeun / Kim, Bumsuk / Jung, Sangil / Lee, Jesuk / Kim, Yitae / Moon, Chang-Rok et al. | 2019
- 16.3.1
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A 1/2inch 48M All PDAF CMOS Image Sensor Using 0.8µm Quad Bayer Coding 2×2OCL with 1.0lux Minimum AF Illuminance LevelOkawa, T. / Ogasahara, T. / Kitano, Y. / Tatani, K. / Ooki, S. / Yamajo, H. / Kawada, M. / Tachi, M. / Goi, K. / Yamasaki, T. et al. | 2019
- 16.4.1
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A 2.2μm stacked back side illuminated voltage domain global shutter CMOS image sensorPark, Geunsook / Grant, Lindsay A. / Hsuing, Alan Chih-Wei / Mabuchi, Keiji / Yao, Jingming / Lin, Zhiqiang / Venezia, Vincent C. / Yu, Tongtong / Yang, Yu-Shen / Dai, Tiejun et al. | 2019
- 16.5.1
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A Highly Reliable Back Side Illuminated Pixel against Plasma Induced DamageSacchettini, Y. / Carrere, J.-P. / Doyen, C. / Duru, R. / Courouble, K. / Ricq, S. / Goiffon, V. / Magnan, P. et al. | 2019
- 16.6.1
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Three-layer Stacked Color Image Sensor With 2.0-μm Pixel Size Using Organic Photoconductive FilmTogashi, H. / Yagi, I. / Murata, M. / Kuribayashi, M. / Koga, F. / Yamaguchi, T. / Oike, Y. / Ezaki, T. / Hirayama, T. / Watanabe, T. et al. | 2019
- 16.7.1
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High-definition Visible-SWIR InGaAs Image Sensor using Cu-Cu Bonding of III-V to Silicon Wafer.Manda, S. / Zaizen, Y. / Hirano, T. / Iwamoto, H. / Matsumoto, R. / Saito, S. / Maruyama, S. / Minari, H. / Takachi, T. / Fujii, N. et al. | 2019
- 17.1.1
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Deep Submicron III-N HEMTs – Technological Development and ReliabilityQuay, R. / Dammann, M. / Kemmer, T. / Bruckner, P. / Cwiklinski, M. / Schwantuschke, D. / Krause, S. / Leone, S. / Mikulla, M. et al. | 2019
- 17.2.1
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CMOS-compatible GaN-based devices on 200mm-Si for RF applications: Integration and PerformancePeralagu, U. / De Jaeger, B. / Fleetwood, D. M. / Wambacq, P. / Zhao, M. / Parvais, B. / Waldron, N. / Collaert, N. / Alian, A. / Putcha, V. et al. | 2019
- 17.3.1
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3D heterogeneous integration of high performance high-K metal gate GaN NMOS and Si PMOS transistors on 300mm high-resistivity Si substrate for energy-efficient and compact power delivery, RF (5G and beyond) and SoC applicationsThen, Han Wui / Huang, C. Y. / Krist, B. / Jun, K. / Lin, K. / Nidhi, N. / Michaelos, T. / Mueller, B. / Paul, R. / Peck, J. et al. | 2019
- 17.4.1
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High-Power-Density AlGaN/GaN Technology for 100-V Operation at L-Band FrequenciesKrause, S. / Bruckner, P. / Dammann, M. / Quay, R. et al. | 2019
- 17.5.1
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GaN-based Periodic High-Q RF Acoustic Resonator with Integrated HEMTGokhale, Vikrant J. / Downey, Brian P. / Katzer, D. Scott / Ruppalt, Laura B. / Meyer, David J. et al. | 2019
- 17.6.1
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452 MHz Bandwidth, High Rejection 5.6 GHz UNII XBAW Coexistence Filters Using Doped AlN-on-SiliconShen, Y. / Patel, P. / Vetury, R. / Shealy, J.B. et al. | 2019
- 18.1.1
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Minimally invasive medical catheter with highly flexible FDSOI-based integrated circuitsKim, Seung-Yoon / Bong, Jae Hoon / Kyung Kim, Mi / Hwang, Wan Sik / Lee, Hyunjoo J. / Song, Byeong-Wook / Kim, Il-Kwon / Cho, Byung Jin et al. | 2019
- 18.2.1
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Highly Sensitive Silicon Slip Sensing Imager for Forceps Grippers Used under Low Friction ConditionAndo, K. / Yamamoto, T. / Maeda, Y. / Terao, K. / Shimokawa, F. / Fujiwara, M. / Takao, H. et al. | 2019
- 18.3.1
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Neural interfaces based on flexible graphene transistors: A new tool for electrophysiologyGuimera-Brunet, A. / Schaefer, N. / Barbero, A. / Godignon, P. / Rius, G. / Del Corro, E. / Bousquet, J. / Hebert, C. / Wykes, R. / Sanchez-Vives, M. V. et al. | 2019
- 18.4.1
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Design and fabrication of CMOS-based neural probes for large-scale electrophysiologyLopez, C. M. / Andrei, A. / Wang, S. / Van Hoof, R. / Severi, S. / Van Helleputte, N. et al. | 2019
- 18.5.1
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Solution Processed Highly Uniform and Reliable Low Voltage Organic FETs and Facile Packaging for Handheld Multi-ion SensingHuang, Y. / Guo, X. / Song, Y. / Tang, Y. / Liu, Z. / Han, L. / Zhang, Q. / Ouyang, B. / Tang, W. / Feng, L. et al. | 2019
- 18.6.1
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BioFET Technology: Aggressively Scaled pMOS FinFET as BiosensorMartens, K. / Vos, R. / Stakenborg, T. / Lagae, L. / Heyns, M. / Severi, S. / Roy, W. Van / Santermans, S. / Gupta, M. / Hellings, G. et al. | 2019
- 18.7.1
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Nanopore Digital Counting of Amplicons for Ultrasensitive Electronic DNA DetectionTang, Zifan / Choi, Gihoon / Nouri, Reza / Guan, Weihua et al. | 2019
- 19.1.1
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Buried Power Rails and Back-side Power Grids: Arm® CPU Power Delivery Network Design Beyond 5nmPrasad, Divya / Spessot, Alessio / Debacker, Peter / Verkest, Diederik / Kulkarni, Jaydeep / Cline, Brian / Sinha, Saurabh / Teja Nibhanupudi, S. S. / Das, Shidhartha / Zografos, Odysseas et al. | 2019
- 19.2.1
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Monolithic Heterogeneous Integration of BEOL Power Gating Transistors of Carbon Nanotube Networks with FEOL Si Ring Oscillator CircuitsCheng, Chao-Ching / Li, Lain-Jong / Wong, H.-S. Philip / Lu, Chun-Chieh / Chao, Tsu-Ang / Chou, Ang-Sheng / Chiang, Hung-Li / Chen, Tzu-Chiang / Gao, Tianqi / Zhao, Jianwen et al. | 2019
- 19.3.1
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Three-Layer BEOL Process Integration with Supervia and Self-Aligned-Block Options for the 3 nm NodeVega-Gonzalez, V. / Bekaert, J. / Kesters, E. / Le, Q. T. / Lorant, C. / Varela P., O. / Teugels, L. / Heylen, N. / El-Mekki, Z. / van der Veen, M. et al. | 2019
- 19.4.1
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Heterogeneous Integration Using Omni-Directional Interconnect PackagingElsherbini, A. A. / Liff, S. M. / Swan, J. M. et al. | 2019
- 19.5.1
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Integrated Deep Trench Capacitor in Si Interposer for CoWoS Heterogeneous IntegrationHou, S.Y. / Wu, C.H. / Yu, Douglas / Hsia, H. / Tsai, C.H. / Ting, K.C. / Yu, T.H. / Lee, Y.W. / Chen, F.C. / Chiou, W.C. et al. | 2019
- 19.6.1
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Foveros: 3D Integration and the use of Face-to-Face Chip Stacking for Logic DevicesIngerly, D. B. / Enamul, K. / Gomes, W. / Jones, D. / Kolluru, K. C. / Kandas, A. / Kim, G.-S. / Ma, H. / Pantuso, D. / Petersburg, C.F. et al. | 2019
- 20.1.1
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Suppression of Bipolar Degradation in 4H-SiC Power Devices by Carrier Lifetime ControlTsuchida, H. / Murata, K. / Tawara, T. / Miyazato, M. / Miyazawa, T. / Maeda, K. et al. | 2019
- 20.2.1
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Low Von 17kV SiC IGBT assisted n-MOS ThyristorMatsunaga, S. / Mizushima, T. / Takenaka, K. / Kiuchi, Y. / Koyama, A. / Yonezawa, Y. / Okumura, H. et al. | 2019
- 20.3.1
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Experimental Investigation and Improvement of Channel Mobility in 4H-SiC Trench MOSFETsKutsuki, K. / Kagoshima, E. / Onishi, T. / Saito, J. / Soejima, N. / Watanabe, Y. et al. | 2019
- 20.4.1
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Improvement in the Channel Performance and NBTI of SiC-MOSFETs by Oxygen DopingNoguchi, M. / Iwamatsu, T. / Amishiro, H. / Watanabe, H. / Kita, K. / Miura, N. et al. | 2019
- 20.5.1
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Physical Modeling of Bias Temperature Instabilities in SiC MOSFETsSchleich, C. / Berens, J. / Rzepa, G. / Pobegen, G. / Rescher, G. / Tyaginov, S. / Grasser, T. / Waltl, M. et al. | 2019
- 21.1.1
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Addressing reliability challenges in advance nodes for commercial and automotive applicationNigam, T. / Paliwoda, P. / Wang, X. / Kerber, A. et al. | 2019
- 21.2.1
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A physics-aware compact modeling framework for transistor aging in the entire bias spaceWu, Zhicheng / Linten, Dimitri / Kaczer, Ben / Franco, Jacopo / Roussel, Philippe J. / Tyaginov, Stanislav / Trujen, Brecht / Vandemale, Michiel / Hellings, Geert / Collaert, Nadine et al. | 2019
- 21.3.1
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Understanding and Physical Modeling Superior Hot-Carrier Reliability of Ge pNWFETsTyaginov, S. / Grill, A. / De Keersgieter, A. / Eneman, G. / Linten, D. / Kaczer, B. / El-Sayed, A.-M. / Makarov, A. / Chasin, A. / Arimura, H. et al. | 2019
- 21.4.1
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New insight into MOS gate stack formations on Ge and SiGe from thermodynamics, reaction kinetics and nanoscale engineeringToriumi, Akira / Nishimura, Tomonori et al. | 2019
- 21.5.1
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Novel Concept of the Transistor Variation Directed Toward the Circuit Implementation of Physical Unclonable Function (PUF) and True-random-number Generator (TRNG)Xiao, Y. / Hsieh, E. R. / Chung, Steve S. / Chen, T. R / Huang, S. A. / Chen, T. J. / Cheng, Osbert et al. | 2019
- 21.6.1
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Physical Insights on Steep Slope FEFETs including Nucleation-Propagation and Charge TrappingXiang, Y. / Verhulst, A. S. / Parvais, B. / Horiguchi, N. / Groeseneken, G. / Houdt, J. Van / Bardon, M. Garcia / Alam, Md Nur K. / Thesberg, M. / Kaczer, B. et al. | 2019
- 22.1.1
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Design Considerations for Efficient Deep Neural Networks on Processing-in-Memory AcceleratorsYang, Tien-Ju / Sze, Vivienne et al. | 2019
- 22.2.1
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Towards 10000TOPS/W DNN Inference with Analog in-Memory Computing – A Circuit Blueprint, Device Options and RequirementsCosemans, S. / Verhoef, B. / Doevenspeck, J. / Papistas, I. A. / Catthoor, F. / Debacker, P. / Mallik, A. / Verkest, D. et al. | 2019
- 22.3.1
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The marriage of training and inference for scaled deep learning analog hardwareGokmen, Tayfun / Rasch, Malte J. / Haensch, Wilfried et al. | 2019
- 22.4.1
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Can in-memory/analog accelerators be a silver bullet for energy-efficient inference?Deguchi, J. / Miyashita, D. / Maki, A. / Sasaki, S. / Nakata, K. / Tachibana, F. et al. | 2019
- 22.5.1
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AI Edge Devices Using Computing-In-Memory and Processing-In-Sensor: From System to DeviceHsu, Tzu-Hsiang / Chiu, Yen-Cheng / Wei, Wei-Chen / Lo, Yun-Chen / Lo, Chung-Chuan / Liu, Ren-Shuo / Tang, Kea-Tiong / Chang, Meng-Fan / Hsieh, Chih-Cheng et al. | 2019
- 22.6.1
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Hybrid Analog-Digital Learning with Differential RRAM SynapsesHirtzlin, T. / Bocquet, M. / Ernoult, M. / Klein, J. - O. / Nowak, E. / Vianello, E. / Portal, J. - M. / Querlioz, D. et al. | 2019
- 22.7.1
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Active Memristor Neurons for Neuromorphic ComputingYi, Wei / Tsang, Kenneth K. / Lam, Stephen K. / Bai, Xiwei / Crowell, Jack A. / Flores, Elias A. et al. | 2019
- 22.8.1
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Towards Large-Scale Photonic Neural-Network AcceleratorsHamerly, R. / Sludds, A. / Bernstein, L. / Prabhu, M. / Roques-Carmes, C. / Carolan, J. / Yamamoto, Y. / Soljacic, M. / Englund, D. et al. | 2019
- 23.1.1
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Importance of Interconnects: A Technology-System-Level Design PerspectiveLiang, J. / Todri-Sanial, A. et al. | 2019
- 23.2.1
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Ultra-scaled MOCVD MoS2 MOSFETs with 42nm contact pitch and 250µA/µm drain currentSmets, Quentin / Groven, Benjamin / Caymax, Matty / Radu, Iuliana / Arutchelvan, Goutham / Jussot, Julien / Verreck, Devin / Asselberghs, Inge / Mehta, Ankit Nalin / Gaur, Abhinav et al. | 2019
- 23.3.1
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Highly Area-Efficient Low-Power SRAM Cell with 2 Transistors and 2 ResistorsLi, Jiayi / Zhou, Peng / Li, Jingyu / Ding, Yi / Liu, Chunsen / Hou, Xiang / Chen, Huawei / Xiong, Yan / Zhang, David Wei / Chai, Yang et al. | 2019
- 23.4.1
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Area-Selective-CVD Technology Enabled Top-Gated and Scalable 2D-Heterojunction Transistors with Dynamically Tunable Schottky BarrierYeh, Chao-Hui / Cao, Wei / Pal, Arnab / Parto, Kamyar / Banerjee, Kaustav et al. | 2019
- 23.5.1
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Transient Negative Capacitance of Silicon-doped HfO2 in MFMIS and MFIS structures: experimental insights for hysteresis-free steep slope NC FETsGastaldi, C. / Saeidi, A. / Cavalieri, M. / Stolichnov, I. / Muralt, P. / Ionescu, A. M. et al. | 2019
- 23.6.1
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Bi-directional Sub-60mV/dec, Hysteresis-Free, Reducing Onset Voltage and High Speed Response of Ferroelectric-AntiFerroelectric Hf0.25Zr0.75O2 Negative Capacitance FETsLee, M. H. / Lin, Y.-Y. / Yang, Y.-J. / Hsieh, F.-C. / Chang, S. T. / Liao, M.-H. / Li, K.-S. / Liu, C. W. / Chen, K.-T. / Liao, C.-Y. et al. | 2019
- 23.7.1
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Direct Observation of Interface Charge Behaviors in FeFET by Quasi-Static Split C-V and Hall Techniques: Revealing FeFET OperationToprasertpong, K. / Takenaka, M. / Takagi, S. et al. | 2019
- 24.1.1
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First–Principles Parameter–Free Modeling of n– and p–FET Hot–Carrier DegradationJech, M. / Tyaginov, S. / Kaczer, B. / Franco, J. / Jabs, D. / Jungemann, C. / Waltl, M. / Grasser, T. et al. | 2019
- 24.2.1
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Computational Study of Spin Injection in 2D MaterialsPal, Arnab / Parto, Kamyar / Agashiwala, Kunjesh / Cao, Wei / Banerjee, Kaustav et al. | 2019
- 24.3.1
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Ab Initio Simulation of Advanced Materials and Devices: Current ChallengesBlaise, P. et al. | 2019
- 24.4.1
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Ab initio mobility of single-layer MoS2 and WS2: comparison to experiments and impact on the device characteristicsLee, Y. / Fiore, S. / Luisier, M. et al. | 2019
- 24.5.1
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Piezoelectric hetero-junction tunnel FET with staggered gap at off-state and broken gap at on-stateLong, Yuxiong / Wen, Hong-Yu / Yang, Shenyuan / Huang, Jun Z. / Jiang, Xiangwei et al. | 2019
- 24.6.1
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Large-scale ab initio quantum transport simulation of nanosized copper interconnects: the effects of defects and quantum interferencesYe, Meng / Jiang, Xiangwei / Li, Shu-Shen / Wang, Lin-Wang et al. | 2019
- 25.1.1
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RF Performance of a Fully Integrated 3D Sequential TechnologyGarros, X. / Lacord, J. / Triantopoulos, K. / Andrieu, F. / Ghibaudo, G. / Gaillard, F. / Lugo-Alvarez, J. / Brunet, L. / Youcef, R. Nait / Batude, P. et al. | 2019
- 25.2.1
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Record high-performance RF devices in an advanced FDSOI process enabling integrated Watt-level power amplifiers for WiFi and 5G applicationsDinh, T. V. / Raucoules-aime, M. / Toso, S. Dal / Ghidini, C. / Hovens, B. W. C. / Vroubel, M. / Brunets, I. / Tuinhout, H. P. / Tiemeijer, L.T.F. / Wils, N. et al. | 2019
- 25.3.1
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Fabrication and Characterization of Millimeter Wave 3D InFO Dipole Antenna Array Integrated with CMOS Front-end CircuitsTsai, C. H. / Wu, T. L. / Liu, C. S. / Wang, C. T. / Yu, Doug C. H. / Hsu, C. W. / Kao, K. Y. / Tang, T. C. / Lu, C. L. / Wu, K. C. et al. | 2019
- 25.4.1
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Implementation of High Power RF Devices with Hybrid Workfunction and OxideThickness in 22nm Low-Power FinFET TechnologyLee, H.-J. / Sell, B. / Zhang, Y. / Morarka, S. / Rami, S. / Yu, Q. / Weiss, M. / Liu, G. / Armstrong, M. / Su, C. - Y. et al. | 2019
- 25.5.1
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A Very Robust and Reliable 2.7GHz +31dBm Si RFSOI Transistor for Power Amplifier SolutionsGarros, X. / Cacho, F. / Vincent, E. / Granger, E. / Gaillard, F. / Knopik, V. / Revil, N. / Divay, A. / Cluzel, J. / Lugo, J. et al. | 2019
- 26.1.1
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Millimeter scale thin film batteries for integrated high energy density storageOukassi, S. / Salot, R. / Bazin, A. / Secouard, C. / Chevalier, I. / Poncet, S. / Poulet, S. / Boissel, J-M. / Geffraye, F. / Brun, J. et al. | 2019
- 26.2.1
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Beyond Electrolytic Capacitor: High Frequency On-chip Micro Supercapacitor with Large Capacitance DensityXu, Sixing / Xia, Fan / Wang, Xiaohong et al. | 2019
- 26.3.1
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Device engineering for diamond quantum sensorsHatano, M. / Iwasaki, T. et al. | 2019
- 26.4.1
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Efficient Integration of Si FET-type Gas Sensors and Barometric Pressure Sensors on the Same SubstrateJang, Dongkyu / Lee, Jong-Ho / Jung, Gyuweon / Jeong, Yujeong / Hong, Yoonki / Hong, Seongbin / Shin, Wonjun / Chang, Ki Soo / Jeong, Chan Bae / Park, Byung-Gook et al. | 2019
- 26.5.1
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A large-area curved pyroelectric fingerprint sensorMainguet, JF. / Kronemeijer, A. J. / Gelinck, G. H. / Pouet, M. / Fourre, J.-Y. / Sinopoli, S. / Emanuele, U. / Fritsch, L. / Jimenez, J. Liu / Karlsson, J. et al. | 2019
- 26.6.1
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Ultrasensitive Flexible Strain Sensor based on Two-Dimensional InSe for Human Motion SurveillanceChen, Li / Liang, Dan / Yu, Zhigen / Li, Sifan / Feng, Xuewei / Li, Bochang / Li, Yesheng / Zhang, Yong-Wei / Ang, Kah-Wee et al. | 2019
- 28.1.1
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3D Semicircular Flash Memory Cell: Novel Split-Gate Technology to Boost Bit DensityFujiwara, M. / Ishikawa, T. / Arayashiki, Y. / Hirayama, K. / Koyama, Y. / Kashiyama, S. / Cai, W. / Goki, Y. / Sawa, K. / Ikeno, D. et al. | 2019
- 28.2.1
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A Novel Double-Density Hemi-Cylindrical (HC) Structure to Produce More than Double Memory Density Enhancement for 3D NAND FlashLue, Hang-Ting / Jiang, Yu-Wei / Hung, Min-Feng / Su, Yan-Ru / Liang, Li-Yang / Hu, Chih-Wei / Chiu, Chia-Jung / Wang, Keh-Chung / Lu, Chih-Yuan / Yeh, Teng-Hao et al. | 2019
- 28.3.1
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Metal-Assisted Solid-Phase Crystallization Process for Vertical Monocrystalline Si Channel in 3D Flash MemoryMiyagawa, Hidenori / Fujiwara, Makoto / Mitani, Yuichiro / Obu, Tomoyuki / Aochi, Hideaki / Kusai, Haruka / Takaishi, Riichiro / Kawai, Tomoya / Kamimuta, Yuuichi / Murakami, Toshiya et al. | 2019
- 28.4.1
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A Fully Integrated Low Voltage DRAM with Thermally Stable Gate-first High-k Metal Gate ProcessJang, Sung Ho / Yamada, Satoru / Lee, Kyupil / Lim, Junhee / Han, Joon / Jang, Juyeon / Yeo, Jaehyun / Lee, Chanmin / Baek, Sungkweon / Lee, Jaehoon et al. | 2019
- 28.5.1
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First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400°C thermal tolerance by canted SOT structure and its advanced patterning/SOT channel technologyHonjo, H. / Yoshiduka, T. / Noguchi, Y. / Yasuhira, M. / Tamakoshi, A. / Natsui, M. / Ma, Y. / Koike, H. / Takahashi, Y. / Furuya, K. et al. | 2019
- 28.6.1
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Field-Free Switching of Perpendicular Magnetization through Voltage-Gated Spin-Orbit TorquePeng, S. Z. / Lu, J. Q. / Li, W. X. / Wang, L. Z. / Zhang, H. / Li, X. / Wang, K. L. / Zhao, W. S. et al. | 2019
- 28.7.1
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A Multilevel FeFET Memory Device based on Laminated HSO and HZO Ferroelectric Layers for High-Density StorageAli, T. / Olivo, R. / Lederer, M. / Hoffmann, R. / Steinke, P. / Zimmermann, K. / Muhle, U. / Seidel, K. / Muller, J. / Polakowski, P. et al. | 2019
- 28.8.1
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A Novel Ferroelectric Superlattice Based Multi-Level Cell Non-Volatile MemoryNi, Kai / Smith, Jeffrey / Ye, Huacheng / Grisafe, Benjamin / Rayner, G. Bruce / Kummel, Andrew / Datta, Suman et al. | 2019
- 29.1.1
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Strain and surface orientation engineering in extremely-thin body Ge and SiGe-on-insulator MOSFETs fabricated by Ge condensationJo, K. - W. / Lim, C.- M. / Kim, W. - K. / Toprasertpong, K. / Takenaka, M. / Takagi, S. et al. | 2019
- 29.2.1
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Ge oxide scavenging and gate stack nitridation for strained Si0.7Ge0.3 pFinFETs enabling 35% higher mobility than SiArimura, H. / Mitard, J. / Demuynck, S. / Horiguchi, N. / Wostyn, K. / Ragnarsson, L.-A. / Capogreco, E. / Chasin, A. / Conard, T. / Brus, S. et al. | 2019
- 29.3.1
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First Vertically Stacked Tensily Strained Ge0.98Si0.02 nGAAFETs with No Parasitic Channel and LG = 40 nm Featuring Record ION = 48 μA at VOV=VDS=0.5V and Record Gm,max(μS/μm)/SSSAT(mV/dec) = 8.3 at VDS=0.5VTu, Chien-Te / Huang, Yu-Shiang / Lu, Fang-Liang / Liu, Hsiao-Hsuan / Lin, Chung-Yi / Liu, Yi-Chun / Liu, C. W. et al. | 2019
- 29.4.1
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Enabling Sub-5nm CMOS Technology Scaling Thinner and Taller!Ryckaert, J. / Baert, R. / Verkest, D. / Na, M. H. / Weckx, P. / Jang, D. / Schuddinck, P. / Chehab, B. / Patli, S. / Sarkar, S. et al. | 2019
- 29.5.1
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First Stacked Ge0.88Sn0.12 pGAAFETs with Cap, LG=4Onm, Compressive Strain of 3.3%, and High S/D Doping by CVD Epitaxy Featuring Record ION of 58µA at VOV=VDS= -0.5V, Record Gm,max of 172µS at VDS= -0.5V, and Low NoiseHuang, Yu-Shiang / Tsai, Chung-En / Tu, Chien-Te / Ye, Hung-Yu / Liu, Yi-Chun / Lu, Fang-Liang / Liu, C. W. et al. | 2019
- 29.6.1
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First Demonstration of Vertical Ge0.92Sn0.08/Ge and Ge GAA Nanowire nMOSFETs with Low SS of 66 mV/dec and Small DIBL of 35 mV/VLiu, Mingshan / Scholz, Stefan / Mertens, Konstantin / Bae, Jin Hee / Hartmann, Jean-Michel / Knoch, Joachim / Buca, Dan / Zhao, Qing-Tai et al. | 2019
- 29.7.1
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300mm Heterogeneous 3D Integration of Record Performance Layer Transfer Germanium PMOS with Silicon NMOS for Low Power High Performance Logic ApplicationsRachmady, W. / Jun, K. / Krist, B. / Metz, M. / Michaelos, T. / Mueller, B. / Oni, A. A. / Paul, R. / Phan, A. / Sears, P. et al. | 2019
- 30.1.1
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Ultra-Low Power Physical Unclonable Function with Nonlinear Fixed-Resistance Crossbar CircuitsMahmoodi, M. R. / Nili, H. / Fahimi, Z. / Larimian, S. / Kim, H. / Strukov, D. et al. | 2019
- 30.2.1
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Formation of High Reliability Hydrogen-free MONOS Cells Using Deuterated AmmoniaNoguchi, Masaki / Abe, Junko / Ogawa, Yoshihiro / Nakagawa, Seiji / Miyajima, Hideshi / Isogai, Tatsunori / Yamashita, Hiroyuki / Sawa, Keiichi / Fujitsuka, Ryota / Yamanaka, Takanori et al. | 2019
- 30.3.1
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Filamentary Statistical Evolution from Nano-Conducting Path to Switching-Filament for Oxide-RRAM in Memory ApplicationsWu, Ernest / Ando, Takashi / Kim, Youngseok / Muralidhar, Ramachandran / Cartier, Eduard / Jamison, Paul / Wang, Miaomiao / Narayanan, Vijay et al. | 2019
- 30.4.1
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Pushing On-chip Memories Beyond Reliability Boundaries in Micropower Machine Learning ApplicationsMauro, Alfio Di / Conti, Francesco / Schiavone, Pasquale Davide / Rossi, Davide / Benini, Luca et al. | 2019
- 30.5.1
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OxRAM for embedded solutions on advanced node: scaling perspectives considering statistical reliability and design constraintsSandrini, J. / Barlas, M. / Nodin, J. F. / Billoint, O. / Molas, G. / Fournel, R. / Nowak, E. / Gaillard, F. / Cagli, C. / Grenouillet, L. et al. | 2019
- 31.1.1
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Manufacturing low dissipation superconducting quantum processorsNersisyan, Ani / Sete, Eyob A. / Stanwyck, Sam / Bestwick, Andrew / Reagor, Matthew / Poletto, Stefano / Alidoust, Nasser / Manenti, Riccardo / Renzas, Russ / Bui, Cat-Vu et al. | 2019
- 31.2.1
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Scalable Quantum Computing Infrastructure Based on Superconducting ElectronicsMukhanov, O. / Plourde, B. L. T. / Opremcak, A. / Liu, C.-H. / McDermott, R. / Kirichenko, A. / Howington, C. / Walter, J. / Hutchings, M. / Vernik, I. et al. | 2019
- 31.3.1
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Silicon Hard-Stop Spacers for 3D Integration of Superconducting QubitsNiedzielski, Bethany M. / Yoder, Jonilyn L. / Ruth-Yost, Donna / Oliver, William D. / Kim, David K. / Schwartz, Mollie E. / Rosenberg, Danna / Calusine, Greg / Das, Rabi / Melville, Alexander J. et al. | 2019
- 31.4.1
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A sparse spin qubit array with integrated control electronicsBoter, J. M. / Dehollain, J. P. / van Dijk, J. P. G. / Hensgens, T. / Versluis, R. / Clarke, J. S. / Veldhorst, M. / Sebastiano, F. / Vandersypen, L. M. K. et al. | 2019
- 31.5.1
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High Volume Electrical Characterization of Semiconductor QubitsPillarisetty, R. / Kashani, N. / Keys, P. / Kotlyar, R. / Luthi, F. / Michalak, D. / Millard, K. / Roberts, J. / Torres, J. / Zietz, O. et al. | 2019
- 31.6.1
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Qubit read-out in Semiconductor quantum processors: challenges and perspectivesMeunier, T. / Casse, M. / Hutin, L. / Jacquinot, H. / Pillonet, G. / Rambal, N. / Thonnart, Y. / Amisse, A. / Apra, A. / Bourdet, L. et al. | 2019
- 31.7.1
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Challenges in Scaling-up the Control Interface of a Quantum ComputerReilly, D. J. et al. | 2019
- 31.8.1
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III-V-on-CMOS Devices and Circuits: Opportunities in Quantum InfrastructureZota, C. B. / Morf, T. / Muller, P. / Convertino, C. / Filipp, S. / Riess, W. / Czornomaz, L. et al. | 2019
- 32.1.1
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Quantitative 3-D Model to Explain Large Single Trap Charge Variability in Vertical NAND MemoryVerreck, D. / Furnemont, A. / Arreghini, A. / Bastos, J.P. / Schanovsky, F. / Mitterbauer, F. / Kernstock, C. / Karner, M. / Degraeve, R. / den bosch, G. Van et al. | 2019
- 32.2.1
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A Comprehensive Modeling Framework for Ferroelectric Tunnel JunctionsHuang, Hsin-Hui / Wu, Tzu-Yun / Chu, Yueh-Hua / Wu, Ming-Hung / Hsu, Chien-Hua / Lee, Heng-Yuan / Sheu, Shyh-Shyuan / Lo, Wei-Chung / Hou, Tuo-Hung et al. | 2019
- 32.3.1
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Modeling of switching speed and retention time in volatile resistive switching memory by ionic drift and diffusionWang, Wei / Covi, Erika / Lin, Yu-Hsuan / Ambrosi, Elia / Ielmini, Daniele et al. | 2019
- 32.4.1
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A Physics-based Model of RRAM Probabilistic Switching for Generating Stable and Accurate Stochastic Bit-streamsZhao, Yudi / Shen, Wensheng / Huang, Peng / Xu, Weijie / Fan, Mengqi / Liu, Xiaoyan / Kang, Jinfeng et al. | 2019
- 32.5.1
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DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device TechnologiesPeng, Xiaochen / Huang, Shanshi / Luo, Yandong / Sun, Xiaoyu / Yu, Shimeng et al. | 2019
- 33.1.1
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A Silicon Photonics Technology for 400 Gbit/s ApplicationsBoeuf, F. / Monfray, S. / Jan, S. / Deglise, C. / Manouvrier, J. R. / Durand, C. / Simbula, A. / Goguet, D. / Bar, P. / Ristoiu, D. et al. | 2019
- 33.2.1
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Silicon nitride waveguide coupled 67+ GHz Ge photodiode for non-SOI PIC and ePIC platformsLischke, S. / Fraschke, M. / Richter, H. / Kruger, A. / Saarow, U. / Heinrich, P. / Winzer, G. / Schulz, K. / Kulse, P. / Trusch, A. et al. | 2019
- 33.3.1
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High-performance hybrid silicon and lithium niobate Mach–Zehnder modulators for over 100 Gbit/sCai, Xinlun et al. | 2019
- 33.4.1
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Integrated DFB Laser Diode and High-efficiency Mach-Zehnder Modulator using Membrane III-V Semiconductors on Si Photonics PlatformHiraki, T. / Aihara, T. / Fujii, T. / Takeda, K. / Kakitsuka, T. / Tsuchizawa, T. / Matsuo, S. et al. | 2019
- 33.5.1
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2D-3D integration of high-κ dielectric with 2D heterostructures for opto-electronic applicationsTerres, B. / Koppens, F. H. L. / Agarwal, H. / Orsini, L. / Montanaro, A. / Sorianello, V. / van Thourhout, D. / Watanabe, K. / Taniguchi, T. / Romagnoli, M. et al. | 2019
- 33.6.1
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First Demonstration of Waveguide-Integrated Black Phosphorus Electro-Optic Modulator for Mid-Infrared Beyond 4 μmHuang, Li / Dong, Bowei / Ma, Yiming / Lee, Chengkuo / Ang, Kah-Wee et al. | 2019
- 34.1.1
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Phase Change NEMS RelayBest, J. T. / Masud, M. A. / de Boer, M. P. / Piazza, G. et al. | 2019
- 34.2.1
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Ultra-Low-Voltage Operation of MEM Relays for Cryogenic Logic ApplicationsHu, Xiaoer / Almeida, Sergio F. / Alice Ye, Zhixin / Liu, Tsu-Jae King et al. | 2019
- 34.3.1
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Monolithic 180nm CMOS Controlled GHz Ultrasonic Impedance Sensing and ImagingAbdelmejeed, Mamdouh / Ravi, Adarsh / Liu, Yutong / Kuo, Justin / Sharma, Jaibir / Merugu, Srinivas / Singh, Navab / Lal, Amit et al. | 2019
- 34.4.1
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MEMS Resonant Microphone Array for Lung Sound ClassificationLiu, Hai / Liu, Song / Shkel, Anton A. / Tang, Yongkui / Kim, Eun Sok et al. | 2019
- 34.5.1
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Extremely High Q AlN Lamb Wave Resonators Implemented by Weighted ElectrodesGao, A. / Zou, J. et al. | 2019
- 34.6.1
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Galfenol-Ti-Diamond Multilayer MEMS Resonator for Magnetic Sensor Working up to 773 KZhang, Z. / Sang, L. / Wu, H. / Huang, J. / Wang, L. / Koizumi, S. / Kodie, Y. / Liao, M. et al. | 2019
- 35.1.1
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Composition Optimization and Device Understanding of Si-Ge-As-Te Ovonic Threshold Switch Selector with Excellent EnduranceGarbin, D. / Pakala, M. / Cockburn, A. / Detavernier, C. / Delhougne, R. / Goux, L. / Kar, G. S. / Devulder, W. / Degraeve, R. / Donadio, G. L. et al. | 2019
- 35.2.1
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Endurance improvement of more than five orders in GexSe1-x OTS selectors by using a novel refreshing program schemeHatem, F. / Zhang, J. F. / Marsland, J. / Freitas, P. / Goux, L. / Kar, G. S. / Chai, Z. / Zhang, W. / Fantini, A. / Degraeve, R. et al. | 2019
- 35.3.1
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Reliability and Variability of 1S1R OxRAM-OTS for High Density Crossbar IntegrationRobayo, D. Alfaro / Deleruyelle, D. / Vianello, E. / Castellani, N. / Ciampolini, L. / Giraud, B. / Cagli, C. / Ghibaudo, G. / Nowak, E. / Molas, G. et al. | 2019
- 35.4.1
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Learning with Resistive Switching Neural NetworksRao, Mingyi / Xia, Qiangfei / Yang, J. Joshua / Wang, Zhongrui / Li, Can / Jiang, Hao / Midya, Rivu / Lin, Peng / Belkin, Daniel / Song, Wenhao et al. | 2019
- 35.5.1
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Novel 1T2R1T RRAM-based Ternary Content Addressable Memory for Large Scale Pattern RecognitionLy, D. R. B. / Nowak, E. / Vianello, E. / Noel, J-P. / Giraud, B. / Royer, P. / Esmanhotto, E. / Castellani, N. / Dalgaty, T. / Nodin, J -F. et al. | 2019
- 35.6.1
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High-Density Multiple Bits-per-Cell 1T4R RRAM Array with Gradual SET/RESET and its Effectiveness for Deep LearningHsieh, E.R. / Zheng, X. / Nelson, M. / Le, B.Q. / Wong, H.-S.P. / Mitra, S. / Wong, S. / Giordano, M. / Hodson, B. / Levy, A. et al. | 2019
- 35.7.1
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Metal-oxide based, CMOS-compatible ECRAM for Deep Learning AcceleratorKim, Seyoung / Ott, John A. / Ando, Takashi / Miyazoe, Hiroyuki / Narayanan, Vijay / Rozen, John / Todorov, Teodor / Onen, Murat / Gokmen, Tayfun / Bishop, Douglas et al. | 2019
- 35.8.1
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Co Active Electrode Enhances CBRAM Performance and Scaling PotentialBelmonte, A. / Witters, T. / Covello, A. / Vereecke, G. / Franquet, A. / Spampinato, V. / Kundu, S. / Mao, M. / Hody, H. / Kar, G. S. et al. | 2019
- 36.1.1
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Design-Technology Co-Optimization of Anti-Fuse Memory on Intel 22nm FinFET TechnologyChao, Yu-Lin / Su, Chen-Yi / Ramey, Stephen M. / Bhattacharya, Uddalak / Sell, Bernhard / Zhang, Ying / Kulkarni, Sarvesh H. / Cha, Soonwoo / Paulson, Leif R. / Rajarshi, Salil M. et al. | 2019
- 36.2.1
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Variability sources in nanoscale bulk FinFETs and TiTaN- a promising low variability WFM for 7/5nm CMOS nodesBhoir, Mandar S. / Chiarella, Thomas / Ragnarsson, Lars A. / Mitard, Jerome / Horiguchi, Naoto / Mohapatra, Nihar R. et al. | 2019
- 36.3.1
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Key Technology Enablers of Innovations in the AI and 5G EraWu, Shien-Yang et al. | 2019
- 36.4.1
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Ultra-scaled Conformal Scavenging Electrode with Superior Tunability for Short-channel RMG FinFET Workfunction and all-ALD 3D-compatible ReRAMRozen, J. / Suu, K. / Hatanaka, M. / Narayanan, V. / Ogawa, Y. / Ando, T. / Bao, R. / Cartier, E. / Honda, K. / Lee, K.-C. et al. | 2019
- 36.5.1
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Novel forksheet device architecture as ultimate logic scaling device towards 2nmWeckx, P. / Gupta, M. / Oniki, Y. / Ragnarsson, L.-A. / Horiguchi, N. / Spessot, A. / Verkest, D. / Ryckaert, J. / Litta, E. Dentoni / Yakimets, D. et al. | 2019
- 36.6.1
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Machine Learning-enhanced Multi-dimensional Co-Optimization of Sub-10nm Technology Node OptionsCeyhan, A. / Quijas, J. / Jain, S. / Liu, H.-Y / Gifford, W. E. / Chakravarty, S. et al. | 2019
- 36.7.1
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5nm CMOS Production Technology Platform featuring full-fledged EUV, and High Mobility Channel FinFETs with densest 0.021µm2 SRAM cells for Mobile SoC and High Performance Computing ApplicationsYeap, Geoffrey / Chen, X. / Yang, B. R. / Lin, C. P. / Yang, F. C. / Leung, Y. K. / Lin, D. W. / Chen, C. P. / Yu, K. F. / Chen, D. H. et al. | 2019
- 37.1.1
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Sub-Thermionic Scalable III-V Tunnel Field-Effect Transistors Integrated on Si (100)Convertino, C. / Moselund, K. E. / Zota, C. B. / Baumgartner, Y. / Staudinger, P. / Sousa, M. / Mauthe, S. / Caimi, D. / Czornomaz, L. / Ionescu, A. M. et al. | 2019
- 37.2.1
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Co-integrated Subthermionic 2D/2D WSe2/SnSe2 Vertical Tunnel FET and WSe2 MOSFET on same flake: towards a 2D/2D vdW Dual-Transport Steep Slope FETOliva, N. / Capua, L. / Cavalieri, M. / Ionescu, A. M. et al. | 2019
- 37.3.1
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Experimental demonstration of integrated magneto-electric and spin-orbit building blocks implementing energy-efficient logicLin, Chia-Ching / DC, Mahendra / Liu, Huichu / Oguz, Kaan / Walker, Emily S. / Plombon, John / Buford, Benjamin / Naylor, Carl H. / Wang, Jian-Ping / Casanova, Felix et al. | 2019
- 37.4.1
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Self-organized Pairs of Ge Double Quantum Dots with Tunable Sizes and Spacings Enable Room-Temperature Operation of Qubit and Single-Electron DevicesPeng, Kang-Ping / Chen, Ching-Lun / Tang, Ying-Tsan / Kuo, David / George, Thomas / Lin, Horng-Chih / Li, Pei-Wen et al. | 2019
- 37.5.1
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A Probabilistic Approach to Quantum Inspired AlgorithmsChowdhury, S. / Datta, S. / Camsari, K. Y. et al. | 2019
- 37.6.1
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High-speed low-energy heat signal processing via digital-compatible binary switch with metal-insulator transitionsYajima, T. / Tanaka, T. / Samata, Y. / Uchida, K. / Toriumi, A. et al. | 2019
- 37.7.1
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Gate reflectometry for probing charge and spin states in linear Si MOS split-gate arraysHutin, L. / Lundberg, T. / Chatterjee, A. / Crippa, A. / Li, J. / Maurand, R. / Jehl, X. / Sanquer, M. / Gonzalez-Zalba, M. F. / Kuemmeth, F. et al. | 2019
- 37.8.1
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Experimental Demonstration of Phase Transition Nano-Oscillator Based Ising MachineDutta, S. / Khanna, A. / Gomez, J. / Ni, K. / Toroczkai, Z. / Datta, S. et al. | 2019
- 38.1.1
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Optimal Design Methods to Transform 3D NAND Flash into a High-Density, High-Bandwidth and Low-Power Nonvolatile Computing in Memory (nvCIM) Accelerator for Deep-Learning Neural Networks (DNN)Lue, Hang-Ting / Hsu, Po-Kai / Wei, Ming-Liang / Yeh, Teng-Hao / Du, Pei-Ying / Chen, Wei-Chen / Wang, Keh-Chung / Lu, Chih-Yuan et al. | 2019
- 38.2.1
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Storage Reliability of Multi-bit Flash Oriented to Deep Neural NetworkXiang, Y. C. / Kang, J. F. / Huang, P. / Yang, H. Z. / Wang, K. L. / Han, R. Z. / Shen, W. S. / Feng, Y. L. / Liu, C. / Liu, X. Y. et al. | 2019
- 38.3.1
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A 3D NAND Flash Ready 8-Bit Convolutional Neural Network Core Demonstrated in a Standard Logic ProcessKim, M. / Liu, M. / Everson, L. / Park, G. / Jeon, Y. / Kim, S. / Lee, S. / Song, S. / Kim, C. H. et al. | 2019
- 38.4.1
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High-Density and Highly-Reliable Binary Neural Networks Using NAND Flash Memory Cells as Synaptic DevicesLee, Sung-Tae / Kim, Hyeongsu / Bae, Jong-Ho / Yoo, Honam / Choi, Nag Yong / Kwon, Dongseok / Lim, Suhwan / Park, Byung-Gook / Lee, Jong-Ho et al. | 2019
- 38.5.1
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Complementary Memory Cell Based on Field-Programmable Ferroelectric Diode for Ultra-Low Power Current-SA Free BNN ApplicationsLuo, Qing / Gong, Tiancheng / Xu, Xiaoxin / Yuan, Peng / Li, Xiaoyan / Tai, Lu / Liu, Qi / Lv, Hangbing / Liu, Ming / Chen, Bing et al. | 2019
- 38.6.1
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A 2TnC ferroelectric memory gain cell suitable for compute-in-memory and neuromorphic applicationSlesazeck, Stefan / Ravsher, Taras / Havel, Viktor / Breyer, Evelyn T. / Mulaosmanovic, Halid / Mikolajick, Thomas et al. | 2019
- 38.7.1
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Memory-Logic Hybrid Gate with 3D-Stackable Complementary Latches for FinFET-based Neural NetworksLee, Chieh / Chih, Yue-Der / Chang, Jonathan / Lin, Chrong Jung / King, Ya-Chin et al. | 2019
- 39.1.1
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State-of-the-art TCAD: 25 years ago and todayStettler, M. / Slepko, A. / Smith, S. / Tiwari, V. / Weber, C. / Weber, J. R. / Cea, S. / Hasan, S. / Jiang, L. / Kaushik, A. et al. | 2019
- 39.2.1
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Efficient Variability- and Reliability-aware Device-Circuit Co-Design: From Trap Behaviors to Circuit PerformanceChen, Wangyong / Cai, Linlin / Du, Gang / Liu, Xiaoyan et al. | 2019
- 39.3.1
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Role of correlation in systematic variation modelingRoy, Ananda S. / Dongaonkar, Sourabh / Mudanai, Sivakumar P. et al. | 2019
- 39.4.1
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An Empirically Validated Virtual Source FET Model for Deeply Scaled Cool CMOSChakraborty, Wriddhi / Ni, Kai / Smith, Jeffrey / Raychowdhury, Arijit / Datta, Suman et al. | 2019
- 39.5.1
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Multiphysics Simulation & Design of Silicon Quantum Dot Qubit DevicesMohiyaddin, F. A. / Chan, BT / Ivanov, Ts. / Spessot, A. / Matagne, P. / Lee, J. / Govoreanu, B. / Raduimec, I. P. / Simion, G. / Stuyck, N. I. Dumoulin et al. | 2019
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IEDM 2019 Committees| 2019
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IEDM 2019 Career Luncheon| 2019
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IEDM 2019 Conference Highlights| 2019
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IEDM 2019 Welcome| 2019
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[Copyright notice]| 2019